diff --git a/verilog/rtl/UART_GFA.v b/verilog/rtl/UART_GFA.v
new file mode 100644
index 0000000..c501664
--- /dev/null
+++ b/verilog/rtl/UART_GFA.v
@@ -0,0 +1,63 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+module UART_GFA(
+  input                 clk_g,
+  input                 rst_g,
+  input         [31:0]  komut,
+  input                 komut_gecerli,
+  input                 veri_hazir,
+  input                 RX,
+  output                TX,
+  output        reg     komut_hazir,
+  output        [31:0]  veri,
+  output                veri_gecerli 
+);
+   
+  wire ver_hazir;
+  wire ver_gecerli = komut_gecerli && (komut[2:0] == 3'b001);
+  wire [7:0] ver_veri = komut[31:24];
+  
+  UART_verici verici(
+    .clk_g(clk_g),
+    .rst_g(rst_g),
+    .ver_veri(ver_veri),
+    .ver_gecerli(ver_gecerli),
+    .TX(TX),
+    .hazir(ver_hazir)
+  );
+  
+  wire al_gecerli;
+  wire [7:0] al_veri;
+  
+  assign veri = {24'b0, al_veri};
+  assign veri_gecerli = al_gecerli;
+  
+  UART_alici alici(
+    .clk_g(clk_g)             ,
+    .rst_g(rst_g)             ,
+    .RX(RX)                   ,
+    
+    .al_veri(al_veri)         ,
+    .al_gecerli(al_gecerli)      
+  );
+
+  always @* begin
+    komut_hazir           =       ver_hazir;
+  end
+      
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/UART_alici.v b/verilog/rtl/UART_alici.v
new file mode 100644
index 0000000..4217461
--- /dev/null
+++ b/verilog/rtl/UART_alici.v
@@ -0,0 +1,151 @@
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module UART_alici(
+  input           clk_g           ,
+  input           rst_g           ,
+  input           RX              ,
+  
+  output  [7:0]   al_veri         ,
+  output  reg     al_gecerli
+        
+  );
+  
+  `ifdef FAST_UART
+   localparam UART_SAAT = 16;
+  `else
+   localparam UART_SAAT = 2083;
+  `endif
+
+  /*
+  50 MHz için UART_SAAT = 5208 (20ns*5208 = 104160ns = 9601 bps)
+  20 MHz için UART_SAAT = 2083 (50ns*2083 = 104150ns = 9602 bps)
+  */
+    
+  localparam BOSTA          = 0;
+  localparam START_BITI_AL  = 1;
+  localparam VERI_AL        = 2;
+  localparam DUR            = 3;
+
+  reg [7:0] veri_ns, veri_r;    
+  reg [1:0] durum_ns, durum_r;
+  reg [31:0] baud_sayac_ns, baud_sayac_r;
+  reg [2:0] RX_ek_ns, RX_ek_r; 
+  
+  wire      saat_ac     = baud_sayac_r == UART_SAAT;
+  wire      ornekle1    = baud_sayac_r == (UART_SAAT/16 * 7);
+  wire      ornekle2    = baud_sayac_r == (UART_SAAT/16 * 8);
+  wire      ornekle3    = baud_sayac_r == (UART_SAAT/16 * 9);
+  
+  reg       RX_r1, RX_r2;
+  
+  reg       RX_ornek1_r, RX_ornek1_ns;
+  reg       RX_ornek2_r, RX_ornek2_ns;
+  reg       RX_ornek3_r, RX_ornek3_ns;
+  
+  wire      RX_ornek_cogunluk = (RX_ornek1_r & RX_ornek2_r) | 
+                                (RX_ornek2_r & RX_ornek3_r) | 
+                                (RX_ornek1_r & RX_ornek3_r);
+  
+  // yari kararli durumdan kurtulmak icin RX'i
+  // iki kez yazmaca yaz
+  always @(posedge clk_g) begin
+    RX_r1                      <=                   RX;
+    RX_r2                      <=                   RX_r1;
+  end
+  
+  assign al_veri                =                   veri_r;
+  
+  always @* begin
+    durum_ns                    =                   durum_r;
+    veri_ns                     =                   veri_r ;
+    baud_sayac_ns               =                   baud_sayac_r;
+    RX_ek_ns                    =                   RX_ek_r;
+    RX_ornek1_ns                =                   RX_ornek1_r;
+    RX_ornek2_ns                =                   RX_ornek2_r;
+    RX_ornek3_ns                =                   RX_ornek3_r;
+    
+    al_gecerli                  =                   1'b0;
+    
+    if (ornekle1) begin
+      RX_ornek1_ns              =                   RX_r2;
+    end
+    if (ornekle2) begin
+      RX_ornek2_ns              =                   RX_r2;
+    end
+    if (ornekle3) begin
+      RX_ornek3_ns              =                   RX_r2;
+    end        
+
+    if (durum_r != BOSTA)
+      baud_sayac_ns             =                   baud_sayac_r + 1;
+    
+    case (durum_r)
+      BOSTA: begin
+        if (RX_r2 == 1'b0) // start
+          durum_ns              =                   START_BITI_AL;
+          baud_sayac_ns         =                   32'd0; 
+      end
+      START_BITI_AL: begin
+        if (saat_ac) begin
+          if (RX_ornek_cogunluk == 1'b0)
+            durum_ns            =                   VERI_AL;
+          else
+            durum_ns            =                   BOSTA;          
+        end      
+      end
+      VERI_AL: begin
+        if (saat_ac) begin
+          veri_ns[RX_ek_r]      =                   RX_ornek_cogunluk;        
+          if (RX_ek_r == 3'b111) begin 
+            RX_ek_ns            =                   3'b000;
+            durum_ns            =                   DUR;
+          end
+          else begin
+            RX_ek_ns            =                   RX_ek_r + 1;
+          end
+        end
+      end
+      DUR: begin
+//        if (saat_ac) begin
+//          durum_ns              =                   BOSTA;
+//          al_gecerli            =                   1'b1;    
+//        end
+        if (baud_sayac_r > (UART_SAAT/16 * 9)) begin
+          durum_ns              =                   BOSTA;
+          baud_sayac_ns         =                   32'd0;
+          al_gecerli            =                   1'b1;    
+        end
+      end
+    endcase
+  
+    if (saat_ac) begin
+      baud_sayac_ns             =                   32'd0;        
+    end          
+  end
+  
+  always @(posedge clk_g) begin
+    if (rst_g) begin
+      veri_r                      <=                  0;
+      durum_r                     <=                  BOSTA;
+      baud_sayac_r                <=                  0;
+      RX_ek_r                     <=                  0;    
+      RX_ornek1_r                 <=                  0;
+      RX_ornek2_r                 <=                  0;
+      RX_ornek3_r                 <=                  0;
+    end
+    else begin
+      veri_r                      <=                  veri_ns;
+      durum_r                     <=                  durum_ns;
+      baud_sayac_r                <=                  baud_sayac_ns;
+      RX_ek_r                     <=                  RX_ek_ns;
+      RX_ornek1_r                 <=                  RX_ornek1_ns;
+      RX_ornek2_r                 <=                  RX_ornek2_ns;
+      RX_ornek3_r                 <=                  RX_ornek3_ns;
+    end
+  end   
+  
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/UART_verici.v b/verilog/rtl/UART_verici.v
new file mode 100644
index 0000000..beee7d4
--- /dev/null
+++ b/verilog/rtl/UART_verici.v
@@ -0,0 +1,116 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+module UART_verici(
+  input           clk_g           ,
+  input           rst_g           ,
+  
+  input   [7:0]   ver_veri        ,
+  input           ver_gecerli     ,
+ 
+  output reg      TX              ,
+  output          hazir 
+  );
+  
+  `ifdef FAST_UART
+   localparam UART_SAAT = 16;
+  `else
+   localparam UART_SAAT = 2083;
+  `endif
+
+  /*
+  50 MHz için UART_SAAT = 5208 (20ns*5208 = 104160ns = 9601 bps)
+  20 MHz için UART_SAAT = 2083 (50ns*2083 = 104150ns = 9602 bps)
+  */
+    
+  localparam BOSTA  = 0;
+  localparam BASLA  = 1;
+  localparam VER    = 2;
+  localparam DUR    = 3;
+
+  reg [7:0] veri_ns, veri_r;    
+  reg [1:0] durum_ns, durum_r;
+  reg [31:0] baud_sayac_ns, baud_sayac_r;
+  reg [2:0] TX_ek_ns, TX_ek_r; 
+  
+  wire      saat_ac   = baud_sayac_r == UART_SAAT;
+  
+  assign    hazir     = durum_r == BOSTA;
+  
+  always @* begin
+    durum_ns                    =                   durum_r;
+    veri_ns                     =                   veri_r ;
+    baud_sayac_ns               =                   baud_sayac_r;
+    TX                          =                   1'b1;
+    TX_ek_ns                    =                   TX_ek_r;
+    case (durum_r)
+      BOSTA: begin
+        if (ver_gecerli) begin
+          veri_ns               =                   ver_veri;
+          durum_ns              =                   BASLA;
+        end        
+      end
+      BASLA: begin
+        TX                      =                   1'b0;
+        if (saat_ac) begin
+          durum_ns              =                   VER;
+        end
+      end
+      VER: begin
+        TX                      =                   veri_r[TX_ek_r];
+        if (saat_ac) begin
+          if (TX_ek_r == 3'b111) begin 
+            TX_ek_ns            =                   3'b000;
+            durum_ns            =                   DUR;
+          end
+          else begin
+            TX_ek_ns            =                   TX_ek_r + 1;
+          end
+        end
+      end
+      DUR: begin
+        TX                      =                   1'b1; //dur?
+        if (saat_ac) begin
+          durum_ns              =                   BOSTA;    
+        end
+      end 
+    endcase
+  
+    if (durum_r != BOSTA) begin
+      baud_sayac_ns             =                   baud_sayac_ns + 1;
+    end
+  
+    if (saat_ac) begin
+      baud_sayac_ns             =                   32'd0;        
+    end          
+  end
+  
+  always @(posedge clk_g) begin
+    if (rst_g) begin
+      durum_r                     <=                  BOSTA;
+      baud_sayac_r                <=                  0;
+      TX_ek_r                     <=                  0;  
+      veri_r                      <=                  0;  
+    end
+    else begin
+      veri_r                      <=                  veri_ns;
+      durum_r                     <=                  durum_ns;
+      baud_sayac_r                <=                  baud_sayac_ns;
+      TX_ek_r                     <=                  TX_ek_ns;
+    end
+  end   
+    
+endmodule
diff --git a/verilog/rtl/adres_tekleyici.v b/verilog/rtl/adres_tekleyici.v
new file mode 100644
index 0000000..6013b9a
--- /dev/null
+++ b/verilog/rtl/adres_tekleyici.v
@@ -0,0 +1,280 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module adres_tekleyici(
+    input                                               clk_g                                           ,
+    input                                               rst_g                                           ,
+    // C0 <-> Adres Tekleyici
+    
+    output                                              c0_oku_hazir_c                                  ,
+    output          [31:0]                              c0_oku_veri_c                                   ,
+    output                                              c0_oku_veri_gecerli_c                           ,
+    output                                              c0_yaz_hazir_c                                  ,
+   
+    input           [31:0]                              c0_oku_adres_g                                  ,
+    input                                               c0_oku_gecerli_g                                ,
+    input           [31:0]                              c0_yaz_veri_g                                   ,
+    input           [3:0]                               c0_yaz_gecerli_g                                ,
+    input           [31:0]                              c0_yaz_adres_g                                  ,
+
+    // C0 <-> Disarisi (UART + Veri Bellegi
+    output          [12:0]                              vb_addra_c                                      ,
+    output          [31:0]                              vb_dina_c                                       ,
+    input           [31:0]                              vb_douta_g                                      ,
+    output    reg                                       vb_ena_c                                        ,
+    output    reg   [3:0]                               vb_wea_c                                        ,
+
+    output    reg   [3:0]                               bb_wea_c                                        ,
+    output    reg                                       bb_ena_c                                        ,
+    output          [31:0]                              bb_dina_c                                       ,
+    output          [31:0]                              bb_addra_c                                      ,
+
+ 
+    output          [31:0]                              s_axi_araddr_c                                  ,
+    input                                               s_axi_arready_g                                 ,                                   
+    output    reg                                       s_axi_arvalid_c                                 ,
+    output          [31:0]                              s_axi_awaddr_c                                  ,
+    input                                               s_axi_awready_g                                 ,
+    output    reg                                       s_axi_awvalid_c                                 ,
+    output                                              s_axi_bready_c                                  ,
+    input           [1:0]                               s_axi_bresp_g                                   ,
+    input                                               s_axi_bvalid_g                                  ,
+    input           [31:0]                              s_axi_rdata_g                                   ,
+    output    reg                                       s_axi_rready_c                                  ,
+    input           [1:0]                               s_axi_rresp_g                                   ,
+    input                                               s_axi_rvalid_g                                  ,
+    output          [31:0]                              s_axi_wdata_c                                   ,
+    input                                               s_axi_wready_g                                  ,
+    output    reg   [3:0]                               s_axi_wstrb_c                                   ,
+    output    reg                                       s_axi_wvalid_c                                  
+    
+    );
+    
+    // TODO b kanali ile ilgilenmeyebiliriz? bready hep 1 olur
+    localparam      AXI_BOSTA_S         =               0                                               ;            
+    localparam      AXI_OKU_AR_S        =               1                                               ;            
+    localparam      AXI_OKU_R_S         =               2                                               ;            
+    localparam      AXI_YAZ_AW_W_S      =               3                                               ;            
+    localparam      AXI_YAZ_AW_S        =               4                                               ;            
+    localparam      AXI_YAZ_W_S         =               5                                               ;            
+   
+    localparam      BRAM_BOSTA_S        =               0                                               ;
+    localparam      BRAM_OKU_S          =               1                                               ;
+    localparam      BRAM_OKU_BEKLE_S    =               2                                               ;
+    localparam      BRAM_YAZ_S          =               3                                               ;
+   
+   
+    reg             [2:0]                               axi_durum_r                                     ;
+    reg             [2:0]                               axi_durum_ns_r                                  ;
+    reg             [1:0]                               bram_durum_r                                    ;
+    reg             [1:0]                               bram_durum_ns_r                                 ;
+   
+    reg                                                 yaz_bb_r                                        ;
+    reg                                                 yaz_bb_ns_r                                     ;
+   
+    (*dont_touch = "true"*) reg             [31:0]                              adres_r                                         ;
+    (*dont_touch = "true"*) reg             [31:0]                              adres_ns_r                                      ;
+
+    (*dont_touch = "true"*) reg             [31:0]                              yaz_veri_r                                      ;
+    (*dont_touch = "true"*) reg             [31:0]                              yaz_veri_ns_r                                   ;
+    reg             [3:0]                               yaz_maske_r                                     ;
+    reg             [3:0]                               yaz_maske_ns_r                                  ;
+   
+    wire                                                yaz_axi_istegi_w                                ;
+    wire                                                oku_axi_istegi_w                                ;
+    
+    wire                                                yaz_vb_w                                        ;
+    wire                                                yaz_bb_w                                        ;
+    
+    // TODO: bu daha da genellenebilir, su anda duragan bir adres eslemesi varsayiyor
+    assign          yaz_axi_istegi_w        =           c0_yaz_adres_g >= 32'h8000_0000                 ;
+    assign          oku_axi_istegi_w        =           c0_oku_adres_g >= 32'h8000_0000                 ;
+    
+    assign          yaz_bb_w                =           (c0_yaz_adres_g >= `BB_TABAN_ADR) &&          
+                                                        (c0_yaz_adres_g < 32'h4000_0000)                ;    
+    
+    // TODO: yalniz bir hazir sinyali?
+    assign          c0_yaz_hazir_c          =           axi_durum_r == 2'b00 && bram_durum_r == 2'b00   ;
+    assign          c0_oku_hazir_c          =           axi_durum_r == 2'b00 && bram_durum_r == 2'b00   ;
+
+    assign          c0_oku_veri_c           =           axi_durum_r == AXI_OKU_R_S                      ?
+                                                        s_axi_rdata_g         :     vb_douta_g          ;             
+    assign          c0_oku_veri_gecerli_c   =           (axi_durum_r == AXI_OKU_R_S && s_axi_rvalid_g)  ||
+                                                        (bram_durum_r == BRAM_OKU_BEKLE_S);
+  
+    assign          s_axi_araddr_c          =           adres_r                                         ;
+    assign          s_axi_awaddr_c          =           adres_r                                         ;
+    assign          s_axi_wdata_c           =           yaz_veri_r                                      ;
+
+    assign          vb_addra_c              =           adres_r                                         ;
+    assign          vb_dina_c               =           yaz_veri_r                                      ;
+    assign          bb_dina_c               =           yaz_veri_r                                      ;
+
+    assign          vb_addra_c              =           adres_r                                         ;
+    assign          bb_addra_c              =           adres_r                                         ;
+    assign          vb_dina_c               =           yaz_veri_r                                      ;
+
+    assign          s_axi_bready_c          =           1'b1                                            ;
+  
+    always @* 
+    begin
+        axi_durum_ns_r                      =           axi_durum_r                                     ;
+        bram_durum_ns_r                     =           bram_durum_r                                    ;
+        adres_ns_r                          =           adres_r                                         ;
+        yaz_veri_ns_r                       =           yaz_veri_r                                      ;
+        yaz_maske_ns_r                      =           yaz_maske_r                                     ;
+        s_axi_arvalid_c                     =           1'b0                                            ;
+        s_axi_awvalid_c                     =           1'b0                                            ;
+        s_axi_rready_c                      =           1'b0                                            ;
+        s_axi_wstrb_c                       =           4'b0                                            ;
+        s_axi_wvalid_c                      =           1'b0                                            ;
+        vb_ena_c                            =           1'b0                                            ;
+        vb_wea_c                            =           4'b0                                            ;
+        bb_wea_c                            =           4'b0                                            ;
+        bb_ena_c                            =           1'b0                                            ;
+        yaz_bb_ns_r                         =           yaz_bb_r                                        ;
+        // Su anda herhangi bir veri aktarimi gerceklestirilmiyor
+        if ((axi_durum_r == AXI_BOSTA_S) && (bram_durum_r == BRAM_BOSTA_S)) begin            
+            if (c0_oku_gecerli_g) 
+            begin
+                if (oku_axi_istegi_w) 
+                begin
+                    axi_durum_ns_r          =           AXI_OKU_AR_S                                    ;
+                    adres_ns_r              =           c0_oku_adres_g      -       32'h8000_0000       ;
+                end
+                else 
+                begin
+                    bram_durum_ns_r         =           BRAM_OKU_S                                      ;
+                    // BRAM word adresleme kullaniyor
+                    adres_ns_r              =           c0_oku_adres_g      >>      2                   ;                
+                end    
+            end
+            else if (c0_yaz_gecerli_g != 0)
+            begin
+                yaz_veri_ns_r               =           c0_yaz_veri_g                                   ;
+                yaz_maske_ns_r              =           c0_yaz_gecerli_g                                ;
+                if (yaz_axi_istegi_w) 
+                begin
+                    axi_durum_ns_r          =           AXI_YAZ_AW_W_S                                  ;
+                    adres_ns_r              =           c0_yaz_adres_g      -       32'h8000_0000       ;
+                end
+                else 
+                begin
+                    bram_durum_ns_r         =           BRAM_YAZ_S                                      ;
+                    // BRAM word adresleme kullaniyor
+                    adres_ns_r              =           (c0_yaz_adres_g - `VB_TABAN_ADR) >> 2           ;
+                    if (yaz_bb_w) begin
+                      yaz_bb_ns_r           =           1'b1                                            ;
+                      adres_ns_r            =           (c0_yaz_adres_g - `BB_TABAN_ADR) >> 2           ;
+                    end
+                end            
+            end
+        end
+        else 
+        begin
+            // axi arayuzunde veri aktarimi gerceklestiriliyor
+            if (axi_durum_r != AXI_BOSTA_S) 
+            begin
+                case (axi_durum_r)
+                    AXI_OKU_AR_S: begin
+                        s_axi_arvalid_c         =       1'b1                                            ;
+                        if(s_axi_arready_g)
+                            axi_durum_ns_r      =       AXI_OKU_R_S                                     ;
+                    end
+                    AXI_OKU_R_S: begin
+                        s_axi_rready_c          =       1'b1                                            ;
+                        if(s_axi_rvalid_g)
+                            axi_durum_ns_r      =       AXI_BOSTA_S                                     ;                                           
+                    end
+                    // https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-UART-Lite-v2-0-is-never-ready/td-p/1064124
+                    AXI_YAZ_AW_W_S: begin
+                        s_axi_awvalid_c         =       1'b1                                            ;
+                        s_axi_wvalid_c          =       1'b1                                            ;
+                        s_axi_wstrb_c           =       yaz_maske_r                                     ;                     
+                        if(s_axi_awready_g && s_axi_wready_g)
+                            axi_durum_ns_r      =       AXI_BOSTA_S                                     ;                        
+                        else if (s_axi_awready_g) 
+                            axi_durum_ns_r      =       AXI_YAZ_W_S                                     ;
+                        else if (s_axi_wready_g)
+                            axi_durum_ns_r      =       AXI_YAZ_AW_S                                    ;                        
+                    end
+                    AXI_YAZ_AW_S: begin
+                        s_axi_awvalid_c         =       1'b1                                            ;
+                        if(s_axi_awready_g)
+                            axi_durum_ns_r      =       AXI_BOSTA_S                                     ;                     
+                    end                        
+                    AXI_YAZ_W_S: begin
+                        s_axi_wstrb_c           =       yaz_maske_r                                     ;
+                        s_axi_wvalid_c          =       1'b1                                            ;
+                        if(s_axi_wready_g)
+                            axi_durum_ns_r      =       AXI_BOSTA_S                                     ;                     
+                    end    
+                endcase
+            end
+            // veri belleginden veri okunuyor veya veri bellegine (ya da buyruk bellegine) yaziliyor
+            else 
+            begin
+                case (bram_durum_r)
+                    BRAM_OKU_S: begin
+                        vb_ena_c                =       1'b1                                            ;
+                        bram_durum_ns_r         =       BRAM_OKU_BEKLE_S                                ;       
+                    end
+                    BRAM_OKU_BEKLE_S: begin
+                        bram_durum_ns_r         =       BRAM_BOSTA_S                                    ;
+                    end
+                    BRAM_YAZ_S: begin
+                        yaz_bb_ns_r             =       1'b0                                            ;
+                        if (yaz_bb_r) begin
+                          bb_ena_c              =       1'b1                                            ;
+                          bb_wea_c              =       yaz_maske_r                                     ;                          
+                        end else begin
+                          vb_ena_c              =       1'b1                                            ;
+                          vb_wea_c              =       yaz_maske_r                                     ;                        
+                        end
+                        bram_durum_ns_r         =       BRAM_BOSTA_S                                    ;
+                    end                        
+                endcase           
+            end
+        end    
+    end
+    
+    always @(posedge clk_g) 
+    begin
+        if (rst_g) 
+        begin
+            axi_durum_r                 <=          AXI_BOSTA_S                                         ;
+            bram_durum_r                <=          BRAM_BOSTA_S                                        ;
+            adres_r                     <=          0                                                   ;
+            yaz_veri_r                  <=          0                                                   ;        
+            yaz_maske_r                 <=          0                                                   ;
+            yaz_bb_r                    <=          0                                                   ;        
+        end
+        else begin
+            axi_durum_r                 <=          axi_durum_ns_r                                      ;
+            bram_durum_r                <=          bram_durum_ns_r                                     ;
+            adres_r                     <=          adres_ns_r                                          ;
+            yaz_veri_r                  <=          yaz_veri_ns_r                                       ;
+            yaz_maske_r                 <=          yaz_maske_ns_r                                      ;
+            yaz_bb_r                    <=          yaz_bb_ns_r                                         ;                                       
+        end
+        
+    end
+    
+endmodule
diff --git a/verilog/rtl/aritmetik_mantik_birimi.v b/verilog/rtl/aritmetik_mantik_birimi.v
new file mode 100644
index 0000000..fce552d
--- /dev/null
+++ b/verilog/rtl/aritmetik_mantik_birimi.v
@@ -0,0 +1,47 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "mikroislem.vh"
+`endif
+
+module aritmetik_mantik_birimi(
+    input         [11:0]    islev_kodu_g                                         ,
+    input         [31:0]    islec1_g                                             ,
+    input         [31:0]    islec2_g                                             ,
+    output reg    [31:0]    sonuc_c
+    );
+    
+    always@* begin
+        sonuc_c             = 0                                                  ;
+        case(islev_kodu_g)
+            `ADD:   sonuc_c = islec1_g + islec2_g                                ;
+            `SUB:   sonuc_c = islec1_g - islec2_g                                ;
+            `AND:   sonuc_c = islec1_g & islec2_g                                ;
+            `OR:    sonuc_c = islec1_g | islec2_g                                ;
+            `XOR:   sonuc_c = islec1_g ^ islec2_g                                ;
+            `SLT:   sonuc_c = ($signed(islec1_g) < $signed(islec2_g))            ; 
+            `SLTU:  sonuc_c = (islec1_g < islec2_g)                              ; 
+            `SLL:   sonuc_c = islec1_g << islec2_g[4:0]                          ; 
+            `SRL:   sonuc_c = $signed({1'b0, islec1_g}) >>> islec2_g[4:0]        ; 
+            `SRA:   sonuc_c = $signed({islec1_g[31], islec1_g}) >>> islec2_g[4:0]; 
+            `LUI:   sonuc_c = islec2_g[19:0]  << 12                              ; // islec2 = anlik
+            `AUIPC: sonuc_c = islec1_g + (islec2_g[19:0]  << 12)                 ; //islec1=ps, islec2=anlik
+        endcase
+    end
+
+    
+endmodule
diff --git a/verilog/rtl/axil_interconnect.v b/verilog/rtl/axil_interconnect.v
new file mode 100644
index 0000000..012b549
--- /dev/null
+++ b/verilog/rtl/axil_interconnect.v
@@ -0,0 +1,137 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module axi_interconnect #(
+    parameter                       SLAVE_NUM   = 16, //maximum 16 olabilir
+    parameter [32*SLAVE_NUM - 1:0]  bases       = 0,
+    parameter [32*SLAVE_NUM - 1:0]  ranges      = 0   
+    ) (
+        // Masterside WAC
+        input [`ADRES_BIT - 1:0]                    m_axi_awaddr,
+        input                                       m_axi_awvalid,
+        input [2:0]                                 m_axi_awprot,
+        output reg                                  m_axi_awready,
+        // Masterside WDC
+        input [`VERI_BIT - 1:0]                     m_axi_wdata,
+        input [3:0]                                 m_axi_wstrb,
+        input                                       m_axi_wvalid,
+        output reg                                  m_axi_wready,
+        // Masterside WRC
+        input                                       m_axi_bready,
+        output reg [1:0]                            m_axi_bresp,
+        output reg                                  m_axi_bvalid,
+        // Masterside RAC
+        input [`ADRES_BIT - 1:0]                    m_axi_araddr,
+        input                                       m_axi_arvalid,
+        input [2:0]                                 m_axi_arprot,
+        output reg                                  m_axi_arready,
+        // Masterside RDC
+        input                                       m_axi_rready,
+        output reg [`VERI_BIT - 1:0]                m_axi_rdata,   
+        output reg [1:0]                            m_axi_rresp,
+        output reg                                  m_axi_rvalid,
+        // Slaveside WAC
+        input [SLAVE_NUM - 1:0]                     s_axi_awready,
+        output reg [`ADRES_BIT*SLAVE_NUM - 1:0]     s_axi_awaddr,
+        output reg [SLAVE_NUM - 1:0]                s_axi_awvalid,
+        output reg [3*SLAVE_NUM - 1:0]              s_axi_awprot,
+        // Slaveside WDC
+        input [SLAVE_NUM - 1:0]                     s_axi_wready,
+        output reg [`VERI_BIT*SLAVE_NUM - 1:0]      s_axi_wdata,
+        output reg [4*SLAVE_NUM - 1:0]              s_axi_wstrb,
+        output reg [SLAVE_NUM - 1:0]                s_axi_wvalid,
+        // Slaveside WRC
+        input [2*SLAVE_NUM - 1:0]                   s_axi_bresp,
+        input [SLAVE_NUM - 1:0]                     s_axi_bvalid,
+        output reg [SLAVE_NUM - 1:0]                s_axi_bready,
+        // Slaveside RAC
+        input [SLAVE_NUM - 1:0]                     s_axi_arready,
+        output reg [`ADRES_BIT*SLAVE_NUM - 1:0]     s_axi_araddr,
+        output reg [SLAVE_NUM - 1:0]                s_axi_arvalid,
+        output reg [3*SLAVE_NUM - 1:0]              s_axi_arprot,
+        // Slaveside RDC
+        input [`VERI_BIT*SLAVE_NUM - 1:0]           s_axi_rdata,
+        input [2*SLAVE_NUM - 1:0]                   s_axi_rresp,
+        input [SLAVE_NUM - 1:0]                     s_axi_rvalid,
+        output reg [SLAVE_NUM - 1:0]                s_axi_rready
+    );
+    
+    wire [SLAVE_NUM - 1:0]  slave_write;
+    wire [SLAVE_NUM - 1:0]  slave_read;
+        
+    genvar s;
+    for( s = 0; s < SLAVE_NUM; s = s + 1) begin
+        assign slave_write[s] = (m_axi_awvalid || m_axi_wvalid || m_axi_bready) ? ((m_axi_awaddr <= (ranges[s*32+:32] + bases[s*32+:32] - 1) && m_axi_awaddr >= bases[s*32+:32])? `HIGH: `LOW): `LOW;   
+        assign slave_read[s] = (m_axi_arvalid || m_axi_rready)? ((m_axi_araddr <= (ranges[s*32+:32] + bases[s*32+:32] - 1) && m_axi_araddr >= bases[s*32+:32])? `HIGH: `LOW): `LOW;
+    end
+    
+    reg[3:0] write_id;
+    reg[3:0] read_id;
+    
+    integer i;
+    always @* begin
+        write_id  = 0;
+        read_id   = 0;
+        for( i = 0; i < SLAVE_NUM; i = i + 1) begin
+            if(slave_write[i]) begin
+                write_id = i;
+                s_axi_awaddr[`ADRES_BIT*i+:`ADRES_BIT]   = m_axi_awaddr;
+                s_axi_awprot[3*i+:3]                     = m_axi_awprot;
+                s_axi_awvalid[i]                         = m_axi_awvalid;
+                s_axi_wdata[`VERI_BIT*i+:`VERI_BIT]      = m_axi_wdata;
+                s_axi_wstrb[`VERI_BIT/8*i+:`VERI_BIT/8]  = m_axi_wstrb;
+                s_axi_wvalid[i]                          = m_axi_wvalid;
+                s_axi_bready[i]                          = m_axi_bready;
+            end else begin
+                s_axi_awaddr[`ADRES_BIT*i+:`ADRES_BIT]   = {`ADRES_BIT{1'b0}};
+                s_axi_awprot[3*i+:3]                     = {3{1'b0}};
+                s_axi_awvalid[i]                         = {1'b0};
+                s_axi_wdata[`VERI_BIT*i+:`VERI_BIT]      = {`VERI_BIT{1'b0}};
+                s_axi_wstrb[`VERI_BIT/8*i+:`VERI_BIT/8]  = {`VERI_BIT/8{1'b0}};
+                s_axi_wvalid[i]                          = {1'b0};
+                s_axi_bready[i]                          = {1'b0};    
+            end
+            if(slave_read[i]) begin
+                read_id = i;
+                s_axi_araddr[`ADRES_BIT*i+:`ADRES_BIT]   = m_axi_araddr;
+                s_axi_arprot[3*i+:3]                     = m_axi_arprot;
+                s_axi_arvalid[i]                         = m_axi_arvalid;    
+                s_axi_rready[i]                          = m_axi_rready;
+            end else begin
+                s_axi_araddr[`ADRES_BIT*i+:`ADRES_BIT]   = {`ADRES_BIT{1'b0}};
+                s_axi_arprot[3*i+:3]                     = {3{1'b0}};
+                s_axi_arvalid[i]                         = {1'b0};    
+                s_axi_rready[i]                          = {1'b0};            
+            end
+        end
+        m_axi_awready = s_axi_awready[write_id];
+        m_axi_wready = s_axi_wready[write_id];
+        m_axi_bvalid = s_axi_bvalid[write_id];
+        m_axi_bresp = s_axi_bresp[write_id*2+:2];
+        m_axi_arready = s_axi_arready[read_id];
+        m_axi_rdata = s_axi_rdata[read_id*`VERI_BIT+:`VERI_BIT];
+        m_axi_rresp = s_axi_rresp[read_id*2+:2];
+        m_axi_rvalid = s_axi_rvalid[read_id];
+    end
+    
+    
+    
+    
+endmodule
diff --git a/verilog/rtl/axil_slave_gfa.v b/verilog/rtl/axil_slave_gfa.v
new file mode 100644
index 0000000..ab4a9b7
--- /dev/null
+++ b/verilog/rtl/axil_slave_gfa.v
@@ -0,0 +1,208 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module axi_slave_gfi (
+    // AXI4 LITE SLAVE signals
+    // Global Signals
+    input                       ACLK,
+    input                       ARESET,
+    // Write Address Channel
+    input [`ADRES_BIT - 1:0]    AWADDR,
+    input                       AWVALID,
+    input [2:0]                 AWPROT,
+    output                      AWREADY,
+    // Write Data Channel
+    input [`VERI_BIT - 1:0]     WDATA,
+    input [`VERI_BIT/8 - 1:0]   WSTRB,
+    input                       WVALID,
+    output                      WREADY,
+    // Write Response Channel
+    input                       BREADY,
+    output                      BVALID,
+    output [1:0]                BRESP,
+    // Read Address Channel
+    input [`ADRES_BIT - 1:0]    ARADDR,
+    input                       ARVALID,
+    input [2:0]                 ARPROT,
+    output                      ARREADY,
+    // Read Data Channel
+    input                       RREADY,
+    output [`VERI_BIT - 1:0]    RDATA,
+    output                      RVALID,
+    output [1:0]                RRESP,
+    
+    // Genel FIFO Aray�z�
+    // Komut Kanali
+    input                       komut_hazir,
+    output                      komut_gecerli,
+    output [`VERI_BIT - 1:0]    komut,
+    // Veri Kanali
+    input [`VERI_BIT - 1:0]     veri,
+    input                       veri_gecerli,
+    output                      veri_hazir
+    );
+    
+    // AXI4 LITE SLAVE Connections
+    localparam [1:0]
+        YAZ_IDLE = 2'd0,
+        YAZ_DATA = 2'd1,
+        YAZ_RESP = 2'd2;
+    localparam [0:0]
+        OKU_IDLE = 1'd0,
+        OKU_DATA = 1'd1;
+    localparam [0:0]
+        KOMUT_IDLE = 1'd0,
+        KOMUT_DATA = 1'd1;
+                    
+    reg [1:0] yaz_state, yaz_state_ns;
+    reg oku_state, oku_state_ns;
+    reg komut_state, komut_state_ns;
+    
+    reg bvalid_r, bvalid_ns_r;
+    reg rvalid_r, rvalid_ns_r;
+    wire [`VERI_BIT - 1:0] strb_data;
+    
+    // Genel FIFO Aray�z� Sinyaller
+    reg veri_reg_bos, veri_reg_bos_ns;
+    reg [`VERI_BIT - 1:0] veri_reg, veri_reg_ns;
+     
+    reg komut_reg_bos, komut_reg_bos_ns;
+    reg [`VERI_BIT - 1:0] komut_reg, komut_reg_ns;
+    
+    reg komut_gecerli_r, komut_gecerli_ns_r;
+    
+
+    // Applying WSTRB to WDATA before pushing into reg
+    genvar i;
+    for(i = 0; i < `VERI_BIT/8; i = i + 1)
+    begin
+        assign strb_data[i*8 +: 8] = WSTRB[i]? WDATA[i*8 +: 8]: 8'hff;
+    end
+    
+    // AXI4 LITE SLAVE Logic
+    assign AWREADY = (komut_reg_bos)? `HIGH: `LOW;
+    assign ARREADY = (~veri_reg_bos)? `HIGH: `LOW;
+    assign WREADY = (komut_reg_bos)? `HIGH: `LOW;
+    assign BVALID = bvalid_r;
+    assign BRESP = 2'b00;
+    assign RDATA = veri_reg;
+    assign RVALID = rvalid_r;
+    assign RRESP = 2'b00;
+    
+    // Genel FIFO Aray�z� Mant?k
+    assign komut_gecerli = komut_gecerli_r;
+    assign komut = komut_reg;
+    assign veri_hazir = (veri_reg_bos)? `HIGH: `LOW;
+
+    always@* begin
+        yaz_state_ns = yaz_state;
+        oku_state_ns = oku_state;
+        komut_state_ns = komut_state;
+        komut_gecerli_ns_r = komut_gecerli_r;
+        veri_reg_bos_ns = veri_reg_bos;
+        komut_reg_bos_ns = komut_reg_bos;
+        veri_reg_ns = veri_reg;
+        komut_reg_ns = komut_reg;
+        rvalid_ns_r = rvalid_r;
+        bvalid_ns_r = bvalid_r;
+        
+        case(yaz_state)
+            YAZ_IDLE: begin
+                if(komut_reg_bos && WVALID) begin
+                    komut_reg_bos_ns = `LOW;
+                    komut_reg_ns = strb_data;
+                    yaz_state_ns = YAZ_DATA;
+                end else begin
+                    yaz_state_ns = YAZ_IDLE;
+                end
+            end
+            YAZ_DATA: begin
+                //if(BREADY) begin // her zaman 1 set ettiğimiz için yoruma aldık
+                    bvalid_ns_r = `HIGH;
+                    yaz_state_ns = YAZ_RESP;
+                //end
+            end
+            YAZ_RESP: begin
+                bvalid_ns_r = `LOW;
+                yaz_state_ns = YAZ_IDLE;
+            end
+        endcase
+        
+        case(oku_state)
+            OKU_IDLE: begin
+                if(RREADY && ~veri_reg_bos) begin
+                    rvalid_ns_r = `HIGH;
+                    veri_reg_bos_ns = `HIGH;
+                    oku_state_ns = OKU_DATA;
+                end
+            end
+            OKU_DATA: begin
+                rvalid_ns_r = `LOW;
+                oku_state_ns = OKU_IDLE;
+            end
+        endcase
+        
+        case(komut_state)
+            KOMUT_IDLE: begin
+                if(komut_hazir && ~komut_reg_bos) begin
+                    komut_gecerli_ns_r = `HIGH;
+                    komut_state_ns = KOMUT_DATA;
+                end
+            end
+            KOMUT_DATA: begin
+                komut_reg_bos_ns = `HIGH;
+                komut_gecerli_ns_r = `LOW;
+                komut_state_ns = KOMUT_IDLE;
+            end
+        endcase
+
+        if(veri_gecerli && veri_reg_bos) begin
+            veri_reg_bos_ns = `LOW;
+            veri_reg_ns = veri;
+        end
+    end
+    
+    always@(posedge ACLK) begin
+        if(ARESET) begin
+            komut_gecerli_r     <= `LOW;
+            yaz_state           <= YAZ_IDLE;
+            oku_state           <= OKU_IDLE;
+            komut_state         <= KOMUT_IDLE;
+            komut_reg           <= 0;
+            veri_reg            <= 0;
+            veri_reg_bos        <= `HIGH;
+            komut_reg_bos       <= `HIGH;
+            rvalid_r            <= `LOW;
+            bvalid_r            <= `LOW;
+        end else begin
+            komut_gecerli_r     <= komut_gecerli_ns_r;
+            yaz_state           <= yaz_state_ns;
+            oku_state           <= oku_state_ns;
+            komut_state         <= komut_state_ns;
+            komut_reg           <= komut_reg_ns;
+            veri_reg            <= veri_reg_ns;
+            veri_reg_bos        <= veri_reg_bos_ns;
+            komut_reg_bos       <= komut_reg_bos_ns;
+            rvalid_r            <= rvalid_ns_r;
+            bvalid_r            <= bvalid_ns_r;
+        end
+    end
+
+endmodule
diff --git a/verilog/rtl/baslangic_bellegi.v b/verilog/rtl/baslangic_bellegi.v
new file mode 100644
index 0000000..8de36b9
--- /dev/null
+++ b/verilog/rtl/baslangic_bellegi.v
@@ -0,0 +1,91 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+module baslangic_bellegi(
+  input                             clk_g                                 ,
+  input                             rst_g                                 ,
+ 
+  input           [31:0]            adres_g                               ,
+  output          [31:0]            buyruk_c                              ,
+  input                             ena_g                         
+);
+
+  wire            [31:0]            buyruklar     [40:0]                  ;
+  reg             [31:0]            buyruk_r                              ;
+  reg             [31:0]            buyruk_ns                             ;
+
+  assign buyruk_c                   =         buyruk_r                    ;
+    
+  assign buyruklar[0]               =         32'H800000B7                ;
+  assign buyruklar[1]               =         32'H00010537                ;
+  assign buyruklar[2]               =         32'H40000A37                ;
+  assign buyruklar[3]               =         32'H0000A103                ;
+  assign buyruklar[4]               =         32'H0000A183                ;
+  assign buyruklar[5]               =         32'H0000A203                ;
+  assign buyruklar[6]               =         32'H0000A283                ;
+  assign buyruklar[7]               =         32'H00028313                ;
+  assign buyruklar[8]               =         32'H00831313                ;
+  assign buyruklar[9]               =         32'H00436333                ;
+  assign buyruklar[10]              =         32'H00831313                ;
+  assign buyruklar[11]              =         32'H00336333                ;
+  assign buyruklar[12]              =         32'H00831313                ;
+  assign buyruklar[13]              =         32'H00236333                ;
+  assign buyruklar[14]              =         32'H00000393                ;
+  assign buyruklar[15]              =         32'H00008103                ;
+  assign buyruklar[16]              =         32'H00250023                ;
+  assign buyruklar[17]              =         32'H00138393                ;
+  assign buyruklar[18]              =         32'H00150513                ;
+  assign buyruklar[19]              =         32'H00638463                ;
+  assign buyruklar[20]              =         32'HFEDFF06F                ;
+  assign buyruklar[21]              =         32'H0000A103                ;
+  assign buyruklar[22]              =         32'H0000A183                ;
+  assign buyruklar[23]              =         32'H0000A203                ;
+  assign buyruklar[24]              =         32'H0000A283                ;
+  assign buyruklar[25]              =         32'H00028313                ;
+  assign buyruklar[26]              =         32'H00831313                ;
+  assign buyruklar[27]              =         32'H00436333                ;
+  assign buyruklar[28]              =         32'H00831313                ;
+  assign buyruklar[29]              =         32'H00336333                ;
+  assign buyruklar[30]              =         32'H00831313                ;
+  assign buyruklar[31]              =         32'H00236333                ;
+  assign buyruklar[32]              =         32'H00000393                ;
+  assign buyruklar[33]              =         32'H00008103                ;
+  assign buyruklar[34]              =         32'H002A0023                ;
+  assign buyruklar[35]              =         32'H00138393                ;
+  assign buyruklar[36]              =         32'H001A0A13                ;
+  assign buyruklar[37]              =         32'H00638463                ;
+  assign buyruklar[38]              =         32'HFEDFF06F                ;
+  assign buyruklar[39]              =         32'H00010537                ;
+  assign buyruklar[40]              =         32'H00050067                ;                       
+                                                    
+  always @* begin                                 
+    buyruk_ns                       =         buyruklar[(adres_g>>2)]     ;
+  end
+  
+  always @(posedge clk_g) begin
+    if (rst_g)
+      buyruk_r                      <=        buyruklar[0]                ;
+    else begin
+      if(ena_g) 
+        buyruk_r                    <=        buyruk_ns                   ;
+      else
+        buyruk_r                    <=        buyruk_r                    ;
+      
+    end        
+  end
+  
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/bellek_islem_birimi.v b/verilog/rtl/bellek_islem_birimi.v
new file mode 100644
index 0000000..9cc9ff8
--- /dev/null
+++ b/verilog/rtl/bellek_islem_birimi.v
@@ -0,0 +1,214 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+//,,,,,,,,,,,,,,.,,,,,,,,,.,,,,,,,,,,,,,,,,,,,,...,.,..,,,,..,..,,...............,......................................................................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.,.,...,,,.,,,..,,,,........,.....,........,.........................................................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,,,,,,,.,,,,,,,,,,,,.......,,,....,,,,..,,..,,.......................................................................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.,.,,...,,,.................,.........................................................
+//,,,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,.,,,,,,,,.,..,...,,,,...,,.,...,.......,...........................,..................................................
+//.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,....,..,...,.....,,,,,.......,.............,.........,.........................................................
+//,,,,,,,,,,,,.,,,,,,,,,,,,,,,,,,,.,,,.,.,,,,,,...,,......,,.............,......................,....,..................................................
+//,,,,,,,,,,..,,,,,,,,,,,,,,,,,,,,,,,,,,,..,,,,,,.,..,,...,,.,,..........,..........................,...................................................
+//.,,,,,...,,,,,,,.,,,,,,,.,,,,,,,.,,,,,.,.,,,,,,,,,,.,,,,,,Ismail Emir Yuksel.........,,.......,,,..............................................
+//,,,,,,,,.,,...,,,,,,.,,,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,.,,,,,.......,..,,,....,.................,,.,.,..................................................
+//,,,,,,,,,,,,,..,,,,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,,,,,,,.,.,,....,,,*,*,,,,,,,*,.......,,..,.,..,,,.,.,,..,..,..,.......................................
+//,,,,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/#%&&&&%#(#(#/,,,...........,,.,,,,,,,.,,,,.,,..,..,...................................
+//,,,,,,..,,,,,,,,.,,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,,,,,,,,,,*#%&&&@@@@@@@&@&@@&%**,,,.....,,...,.,,,,,,,,.,,,,,,,.,...,...,..............................
+//,,,,,,,,.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/%@@@@@@@&&&&&&&@@@@@&&%,,,,.,...,.,,,,,,,,,,,,,,,,,,,,,,,,,,...,..,..........................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*&@@@&%(((//(((((((((((%@@@@&%,.,,,,,,,,,,,,,,,.,,,,,,,,,,,,,,,,,,...............................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*@@@@%(/////////////////***/%@@@@(,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..............................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,@@@@(///////////////////*****/&@@@(,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..,...........................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,(@@&#//////(((////////////*****/%@@&,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..,.........................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*@&#/(&&&&%%%#((/////(#%&%%%%%*,(&&&,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,,,,,........................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,&%/((((###%%%#(//*/(#%%##(/*,**,#&#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..,......................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,&(//(#####%%#((//*/(#%%###%%*,,,#&,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,,,,,,.....,...................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,&//////((((((/(//***/((((///***,%%,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.,.......................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,#//////////(##//(//,,*,#(///***,,,(,/*,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.........................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,#//(/////(##(#&&&&%&&%#((#(//*,,,,(,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.....,..................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*(#%(///(#&%%########((##%#(**,**(((*,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.......................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,(%##((#%%&%(((##(((/(#%%#(*////%*,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,....................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*%%#####(((##%%%#//**/(#/(#(((#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.......................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,(&%%%%%##((#%%%#((((###%###%(,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,......................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,#&&&%%%%%%%%&&%%%%%##%%%%%/,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..,,,,................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/&&&&&%%&&&&&&%%%%%%%&%%/,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,,,.,................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*(#%&&&&&&&&%%%%%&%%#(/*,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,,.,,................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,(((((##%&&&%%%#(*******,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,.,....................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*(((((((((###((/**********&&#,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,...,.,...,............
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,&&@&&(((((((((((((((/***//****/%&@&@&&&#*,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,................
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*&&@@@@@@@@&((((((((((((((/////****/%&&@&&&@@@&&&&&&&%(,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,.............
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,/&&&&&@@@&@@@@@@@@@@%(((((((((((((((///((#&&&&@@&&&@@@&&&&&&&&&&&&&%(,,,,,,,,,,,,,,,,,,,,,,,,,,,,,..,.............
+//,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,*%&&&&&&&@&@&@&@@@&@@@@@@@@@@&&((((((((((((#&&&&&@&&&@&&&&&&&&&&&&&&&&&&&&&%%*,,,,,,,,,,,,,,,,,,,,,,,,,,,,.,............
+//,,,,,,,,,,,,,,,,,,,,,,,,,,*(&&&&&&&@&&&&&@&@&@@@&&@@@@@@@@@@@@@@@@@@@@@@@@@@&&@@&&@&&&&&&&&&&&&&@@&&&&&&&&&%%,,,,,,,,,,,,,,,,,,,,,,,,,,.,,............
+//,,,,,,,,,,,,,,,,,,,,,,,,,%&&&&&&&&&&&&&&&&&&&&&@&@&&@@@@@@@@@@@@&@@@@@@&&@@@&&@&&&&&&&&&&&@&&&&&&@&&&&&&&%&&%%*,,,,,,,,,,,,,,,,,,,,,,,,,.,............
+//,,,,,,,,,,,,,,,,,,,,,,,,%&&&&&&&&&&&&&&&&&@@&@&&&&&&&&&@&&&@@@@@@@&&&@&&&&@&&&&&&&@&&&&&@&&&&&&&&&&&&&%&%&&&%%&#,,,,,,,,,,,,,,,,,,,,,,,...............
+//,,,,,,,,,,,,,,,,,,,,,,*%&&&&&&&&&&&&&&&&&&&&&&&&&@&@&&&&@&@&&@@@@@&&@@&&&&@&&&&&&&&&&&&&&&&&&&&&&&&&&&&&%&@&%%%&%,,,,,,,,,,,,,,,,,,,,,,,..............
+//,,,,,,,,,,,,,,,,,,,,,*%&&&&&&&&&&&&&@&&&@&&&&&&&&@@&&&&&&&&@&&&&&&@&&@&&&@&&&&&&&&&&&&&&&&&&&&&&&&&&&%&%&&&&%%%&&%,,,,,,,,,,,,,,,,,,,,,.,,............
+//,,,,,,,,,,,,,,,,,,,,*%&&&&&&&@&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&@&&@&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&%&%%@&&&&&%&&&%,,,,,,,,,,,,,,,,,,,,,,.............
+//,,,,,,,,,,,,,,,,,****&&&&@&&@@@&&&&&&&&&&&&&&@&&&&&&@&&&&&&&&@&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&%&%%%&@@&%&&&@&&&%,,,,,,,,,,,,,,,,,,,,,.............
+//,,,,,,,,,,,,,,,,,,*,/&&&&&&&&@@@@&&&&&&&&@@&&&&&&&&&&&@&&&&&&&&&&&&@&&@&&@&&&&@&&&&@&&&&&&&&&&&&&&%%%%%@&&@%&&&&&&&&(,,,,,,,,,,,,,,,,,,,,.............
+//,,,,,,,,,,,,,,,,****#%&&&@@@@@@&@@&&&&&&&&@@&@@&@&&@&@&&&&&&@&&&&@&&@@&&&&&&&&&&&&&&&&&&&&&&&&&&%%%%%&&@&&&&&&@&&&@&%/,,,,,,,,,,,,,,,,,,,.,...........
+//,,,,,,,,,,,,*,,**,,*%%&&&&@@@@@&@@&&&&&&&@@&&&&@&&&&&&&&@&&&&&&&@@@&&&&@&&@&&&&&&&&&&&&&&&&&&&&&&%%%%&@@@&&&&&&&&@@&&%/,,,,,,,,,,,,,,,,,,,............
+//.,,,,,,,,,,,,,,,****%&&&@&@@@@@@@@@&&&&&&&&&&&&&&&&&&&&&&&@&&&&&&@@&@&&&&&&&&&&&@&&&&&&&&&&&&&&%%%%%&&@@&&&&&&&&&@@&&%%*,,,,,,,,,,,,,,,,,,............
+//.,,,,,,,,,,,,,,,,***%&&&@&@@@@@&@@@&&&&&&&&&&&&&&@&@&&@&&&&&&@&&&&@@&&&@&&@&&&&@&&&&&&&&&&&&%&%%%%%%@@@@&&&&&&&&@@&&&&%%*,,,,,,,,,,,,,,,,.............
+//.,,,,,,,,,,,,,,*,**/&&&@&@@@@@@@@@@@&@@&&&&&&&&&&&@@@@@&&&&&&&&&&&&&&&&&&&&@&&&@@&&&&&&&&&&&&&%%%%%%&@@&&&&&&@&&@&&&&&&&%*,,,,,,,,,,,,,,,,,...........
+//.,,,,,,,,,,,,,,,,*/&&&@@@@@@@@@@@@@@@@@@&&&&@&&&@&@&&&&@&&@&&&&&@&&&@&@&&&@@&&&&&&&&&&&&&&&&&%%%%%%&@@@@&&&@@&&&&&@&&&&&%#,,,,,,,,,,,,,,,,............
+//.,,,,,,,,,,,,,,,,*&&&@@@@@@@@@@@@@@@@@&@&&&&&&&&&@&&@&&&@&&&&&&&&&&@&@@&&&&&&&&@&&@&&&&&&&%%&%%%%%%@@@@@@&@@@@@@@@@&&&/,,,,,,,,,,,,,,,,,,.,...........
+//.,,,,,,,,,,,,,,*,#&&&&&@@@@@@@@@@@@@@@@&&@&&&&@@&@&&&&&&&&&&&&&&&&&&&&&&&&&@@&&&&&&&&&&&&&&%%%%%%%%%@@@@@@@&@@&&/,,,,,,,,,,,,,,,,,,,,,,,,.............
+//.,,,,,,,,,,,,,,,,*,/&@@@@@@@@@@@@@@@@@@&&&&&&@@&&&&&&&@&&@&&@&&&&&&@&&&&@&@@&&&&&&&&&&&&&&&&%%%%%%*&@@@@&#(//**,,,,,,,,,,,,,,,,,,,,,,,,,,.............
+//.,,,,,,,,,,,,,*,**,*(((((((((##%&@@&#@@@@&&@&@@&&&@@@&@&&&&@&&&&&&&&&&&&&&&&@&&&&&&&&&&&&&&&&%%%%#**%&%##((//**,,,,,,,,,,,,,,,,,,,,,,,,,,,..,.........
+//.,,,,,,,,,,,,,**,***(((((((((((###%%*@@@&@&@&&&&&&&@@@&&&&&&&&&&&&&@@@&&&&&&&&&&&&&&&&&&&&&&&%%%%(,*/&%###((/***,,,,,,,,,,,,,,,,,,,,,,,,,,............
+//.,,,,,,,,,,,*,**,***((((((((((###%%/*#&&&&@@&&&&&&&@@@&@&&@&&&&&&&&&&&@&&&&&&&&&&&&&&&&&&&&&&&%%%/**,%%%##((///**,,,,,,,,,,,,,,,,,,,,,,,.,,...........
+//.,,,,,,,,,,,,,,****/(((((((((####%%***&&&&@&@&&&&&&@@&&&&&&&&@&&&&&&&@@@@&&&&&&@&&&&&&&&&&&&&&&%%****(%%###(((//**,,,,,,,,,,,,,,,,,,,,,..,............
+//.,,,,,,,,,,*,,*****(((((((((####%%*****&&&&@&&&&&&&@&@&&&&&&&&&&&@&@@&@@&&&&&&&&&&&&&%&&&&&&&&&&#*****%%%#####((/*,,,,,,,,,,,,,,,,,,,,,,.,............
+//.,,,,,,,,,,,,,,****((((((((####%%%*****&&&@&&&&&&&&@@&@&&@&&&&&&&&&&&&&&@@&&&&&&@&&&&&&&&&&&&&&&%&**,*%%%######(/*,,,,,,,,,,,,,,,,,,,,,...............
+// SRAM Researcher, Architecturer, Computer Scientist/Electrical Engineer
+// Hobbies: Cryptocurrency Enthusiast, DogeCoin
+// Language: Verilog, C, Turkish, English, Nihongo, BOOTLOADER
+
+module bellek_islem_birimi#(parameter GECIKME = 5)
+    (
+    input                   clk_g                                                ,
+    input                   rst_g                                                ,
+    input         [2:0]     bellek_buyrugu                                       ,
+    input         [31:0]    islec1_g                                             ,
+    input         [31:0]    islec2_g                                             ,
+    input         [31:0]    anlik_g                                              ,
+    input                   bellek_isaretli                                      ,
+    input         [2:0]     bellek_turu                                          ,
+    input                   bellek_hazir_g                                       ,
+    input         [31:0]    oku_veri_g                                           ,
+    input                   oku_veri_gecerli_g                                   ,
+    output  reg             bitti_c                                              ,           
+    output  reg   [31:0]    oku_veri_c                                           , 
+    output  reg   [31:0]    adres_bib_c                                          ,
+    output  reg             oku_gecerli_bib_c                                    ,
+    output  reg             yaz_gecerli_bib_c                                    ,
+    output  reg   [31:0]    yaz_veri_bib_c                                       ,
+    output  reg   [3:0]     yaz_veri_bib_maske_c                                       
+    
+    );
+    localparam FENCE  = 3'b001,
+               KAYDET = 3'b010,
+               YUKLE  = 3'b100;
+           
+      
+    localparam SB  = 3'b001,
+               SH  = 3'b010,
+               SW  = 3'b100;
+     
+    
+    localparam LW    = 5'b00001,
+               LH    = 5'b00010,
+               LB    = 5'b00100,
+               LHU   = 5'b01000,
+               LBU   = 5'b10000;
+                          
+    localparam BOSTA = 2'b10,
+               BEKLE = 2'b01;       
+           
+           
+    reg          [4:0]    oku_islem_turu                = 0                  ;       
+    reg                   islem_basladi_mi              = 0                  ;
+    
+    
+    reg          [1:0]    bib_durum_r = 0, bib_durum_ns = 0                          ;
+    
+    always@* begin
+       bib_durum_ns                 = bib_durum_r                          ;
+       oku_gecerli_bib_c            = 1'b0                                 ;
+       yaz_gecerli_bib_c            = 1'b0                                 ;
+       yaz_veri_bib_maske_c         = 4'b0                                 ;
+       yaz_veri_bib_c               = islec2_g                             ;
+       
+       adres_bib_c                  = 0                                    ;
+       oku_veri_c                   = 0                                    ;
+       bitti_c                      = 0                                    ;
+       
+       case(bellek_buyrugu)
+           FENCE: begin
+               // HICBIR SEY YAPMA
+           end
+           KAYDET: begin
+                   //anlik deger $signed olarak belirtilmemis
+                   adres_bib_c = islec1_g + { {20{anlik_g[11]}}, anlik_g[11:0] };
+
+           end
+           YUKLE: begin
+                   //anlik deger $signed olarak belirtilmemis
+                   adres_bib_c = islec1_g + { {20{islec2_g[11]}}, islec2_g[11:0] };
+                   oku_islem_turu = {bellek_turu[0],bellek_turu[1],bellek_turu[2]} << 2*$unsigned(~bellek_isaretli); // kontrol ettim, simdilik problem yok gibi.
+                   case(oku_islem_turu)
+                        LW:  oku_veri_c = oku_veri_g;
+                        
+                        LH:  oku_veri_c = {{16{oku_veri_g[{adres_bib_c[1], 4'b0000} + 15]}},
+                                             oku_veri_g[{adres_bib_c[1], 4'b0000} +: 16]};
+                                             
+                        LHU: oku_veri_c = {{16{1'b0}},
+                                             oku_veri_g[{adres_bib_c[1], 4'b0000} +: 16]};
+                                             
+                        LB:  oku_veri_c = {{24{oku_veri_g[{adres_bib_c[1:0], 3'b000} + 7]}},
+                                             oku_veri_g[{adres_bib_c[1:0], 3'b000} +:8]};
+                                             
+                        LBU: oku_veri_c = {{24{1'b0}},
+                                                oku_veri_g[{adres_bib_c[1:0], 3'b000} +:8]};
+                    endcase
+           end
+       endcase       
+       
+       case(bib_durum_r)
+            BOSTA: begin
+                if (bellek_hazir_g) begin
+                  if (bellek_buyrugu == YUKLE) begin
+                    bib_durum_ns = BEKLE;
+                    oku_gecerli_bib_c = 1'b1;
+                  end
+                  else begin
+                    if (bellek_buyrugu == KAYDET) begin
+                      case(bellek_turu)
+                           SW: yaz_veri_bib_maske_c = 4'b1111;
+                           SH: begin
+                            yaz_veri_bib_maske_c = {adres_bib_c[1], adres_bib_c[1], ~adres_bib_c[1], ~adres_bib_c[1]};
+                            yaz_veri_bib_c = islec2_g << (adres_bib_c[1] * 16);                          
+                           end
+                           SB: begin
+                            yaz_veri_bib_maske_c[adres_bib_c[1:0]] = 1'b1;
+                            yaz_veri_bib_c = islec2_g << (adres_bib_c[1:0] * 8);                      
+                           end
+                      endcase
+                      yaz_gecerli_bib_c = 1'b1;
+                    end
+                    bitti_c = 1'b1;
+                  end
+                end
+            end // BOSTA
+            BEKLE: begin
+              if (oku_veri_gecerli_g) begin
+                bitti_c = 1'b1;
+                bib_durum_ns = BOSTA;
+              end
+            end
+       endcase
+
+    end
+    
+    always @(posedge clk_g) begin
+       if (rst_g)
+         bib_durum_r <= BOSTA;
+       else
+         bib_durum_r <= bib_durum_ns;
+    end
+               
+endmodule
diff --git a/verilog/rtl/buyruk_bellegi_sram.v b/verilog/rtl/buyruk_bellegi_sram.v
new file mode 100644
index 0000000..9a6644a
--- /dev/null
+++ b/verilog/rtl/buyruk_bellegi_sram.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+
+
+module buyruk_bellegi_sram
+(
+    input           [`BB_ADRES_BIT-1:0]             addra                   ,
+    input                                           clka                    ,
+    input           [31:0]                          dina                    ,
+    input                                           ena                     ,
+    input           [3:0]                           wea                     ,
+                
+    output          [31:0]                          douta                   ,
+
+    // To SRAM outside c0's macro
+    output                                          csb0                    ,
+    output                                          web0                    ,
+    output          [3:0]                           wmask0                  ,
+    output          [`BB_ADRES_BIT-1:0]             addr0                   ,
+    output          [31:0]                          din0                    ,
+    input           [31:0]                          dout0                   ,
+
+    output                                          csb1                    ,
+    output          [`BB_ADRES_BIT-1:0]             addr1                   ,
+    input           [31:0]                          dout1                         
+
+);
+
+    assign      csb0        =           ~(ena&(|wea))       ;
+    assign      web0        =           ~(|wea)             ;
+    assign      wmask0      =           wea                 ;
+
+    assign      addr0       =           addra               ;
+    assign      din0        =           dina                ;
+    //assign      dout0       =           32'b0           ;
+
+    assign      csb1        =           ~(ena&(~(|wea)))    ;
+    assign      addr1       =           addra               ;
+    assign      douta       =           dout1               ;
+
+
+endmodule
diff --git a/verilog/rtl/c0_system.v b/verilog/rtl/c0_system.v
new file mode 100644
index 0000000..754c41f
--- /dev/null
+++ b/verilog/rtl/c0_system.v
@@ -0,0 +1,455 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`default_nettype none
+
+module c0_system(
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+        input                                           clk_g                   ,
+        input                                           rst_g                   ,
+        
+        output          tx,
+        input           rx,
+        output          io_gecerli,
+        output [31:0]   io_ps,
+        output [37:0]   io_oeb,
+
+        output                                          vb_csb0                 ,
+        output                                          vb_web0                 ,
+        output          [3:0]                           vb_wmask0               ,
+        output          [12:0]                          vb_addr0                ,
+        output          [31:0]                          vb_din0                 ,
+        input           [31:0]                          vb_dout0                ,
+
+        output                                          vb_csb1                 ,
+        output          [12:0]                          vb_addr1                ,
+        input           [31:0]                          vb_dout1                ,
+
+        output                                          bb_csb0                 ,
+        output                                          bb_web0                 ,
+        output          [3:0]                           bb_wmask0               ,
+        output          [`BB_ADRES_BIT-1:0]             bb_addr0                ,
+        output          [31:0]                          bb_din0                 ,
+        input           [31:0]                          bb_dout0                ,
+
+        output                                          bb_csb1                 ,
+        output          [`BB_ADRES_BIT-1:0]             bb_addr1                ,
+        input           [31:0]                          bb_dout1                                   
+    );
+    assign io_oeb = {(`MPRJ_IO_PADS-1){rst_g}};
+
+    //==============================================================================
+    //                        Bellek Adresi Tekleyici ve C0
+    //==============================================================================
+    
+    wire                                                c0_oku_hazir_w                                                  ;
+    wire           [31:0]                               c0_oku_veri_w                                                   ;
+    wire                                                c0_oku_veri_gecerli_w                                           ;
+    wire                                                c0_yaz_hazir_w                                                  ;
+                                                                                                      
+    wire                                                c0_oku_gecerli_w                                                ;
+    wire           [31:0]                               c0_yaz_veri_w                                                   ;
+    wire           [3:0]                                c0_yaz_gecerli_w                                                ;
+    wire           [31:0]                               c0_adres_w                                                  ;
+
+    //==============================================================================
+    //                  C0 Cekirdegi, On Taraf ve Kesme Denetleyici
+    //==============================================================================
+    
+    wire                                                bb_buy_gecerli_g_w                                              ;
+    wire           [`BUYRUK_BIT-1:0]                    bb_buy_g_w                                                      ;
+    wire           [`BB_ADRES_BIT-1:0]                  bb_buy_ps_g_w                                                   ;
+    wire                                                gc_hazir_c_w                                                    ;
+    wire           [`BB_ADRES_BIT-1:0]                  bb_buy_istek_adres_c_w                                          ;
+    wire                                                bb_buy_istek_c_w                                                ; 
+    
+    wire                                                kesme_g_w                                                       ;
+    wire                                                zamanlayici_kesme_g_w                                           ;
+    
+    //==============================================================================
+    //                                Buyruk Bellegi
+    //==============================================================================
+        
+    wire           [`BB_ADRES_BIT-1:0]                  bb_addra_w                                                      ;                                        
+    wire           [`BB_ADRES_BIT-1:0]                  bat_bb_addra_w                                                  ;                                        
+    wire           [`BB_ADRES_BIT-1:0]                  ot_bb_addra_w                                                   ;                                        
+    wire                                                bb_clka_w                                                       ;                                      
+    wire           [31:0]                               bb_dina_w                                                       ;                                     
+    wire           [31:0]                               bb_douta_w                                                      ;                                      
+    wire                                                ot_bb_ena_w                                                     ;                                     
+    wire                                                bat_bb_ena_w                                                    ;                                     
+    wire                                                bb_ena_w                                                        ;                                     
+    wire           [3:0]                                bb_wea_w                                                        ;                                       
+
+        
+    wire           [`BB_ADRES_BIT-1:0]                  basbel_addra_w                                                  ;                                        
+    wire           [31:0]                               basbel_douta_w                                                  ;
+    wire                                                basbel_ena_w                                                    ;
+    
+    //==============================================================================
+    //                                 Veri Bellegi
+    //==============================================================================
+        
+    wire           [12:0]                               vb_addra_w                                                      ;                                        
+    wire                                                vb_clka_w                                                       ;                                      
+    wire           [31:0]                               vb_dina_w                                                       ;                                     
+    wire           [31:0]                               vb_douta_w                                                      ;                                      
+    wire                                                vb_ena_w                                                        ;                                     
+    wire           [3:0]                                vb_wea_w                                                        ;        
+
+    //==============================================================================
+    //                                AXI SISTEMI
+    //==============================================================================
+                             
+    wire                                                interrupt_w                                                     ;                                     
+    wire           [31:0]                               s_axi_araddr_w                                                  ;                                      
+    wire                                                s_axi_arready_w                                                 ;                                     
+    wire                                                s_axi_arvalid_w                                                 ; 
+    wire           [2:0]                                s_axi_arprot_w                                                  ;
+    wire           [31:0]                               s_axi_awaddr_w                                                  ;
+    wire           [2:0]                                s_axi_awprot_w                                                  ;
+    wire                                                s_axi_awready_w                                                 ;
+    wire                                                s_axi_awvalid_w                                                 ;
+    wire                                                s_axi_bready_w                                                  ;
+    wire           [1:0]                                s_axi_bresp_w                                                   ;
+    wire                                                s_axi_bvalid_w                                                  ;
+    wire           [31:0]                               s_axi_rdata_w                                                   ;
+    wire                                                s_axi_rready_w                                                  ;
+    wire           [1:0]                                s_axi_rresp_w                                                   ;
+    wire                                                s_axi_rvalid_w                                                  ;
+    wire           [31:0]                               s_axi_wdata_w                                                   ;
+    wire                                                s_axi_wready_w                                                  ;
+    wire           [3:0]                                s_axi_wstrb_w                                                   ;
+    wire                                                s_axi_wvalid_w                                                  ;
+    wire                                                s_axi_aclk_w                                                    ;
+    wire                                                s_axi_aresetn_w                                                 ;
+
+    adres_tekleyici bat
+    (
+        .clk_g                                          (clk_g)                                                         ,
+        .rst_g                                          (rst_g)                                                         ,
+                                                        
+        .c0_oku_hazir_c                                 (c0_oku_hazir_w)                                                ,
+        .c0_oku_veri_c                                  (c0_oku_veri_w)                                                 ,
+        .c0_oku_veri_gecerli_c                          (c0_oku_veri_gecerli_w)                                         ,
+        .c0_yaz_hazir_c                                 (c0_yaz_hazir_w)                                                ,
+                                                        
+        .c0_oku_adres_g                                 (c0_adres_w)                                                    ,
+        .c0_oku_gecerli_g                               (c0_oku_gecerli_w)                                              ,
+        .c0_yaz_veri_g                                  (c0_yaz_veri_w)                                                 ,
+        .c0_yaz_gecerli_g                               (c0_yaz_gecerli_w)                                              ,
+        .c0_yaz_adres_g                                 (c0_adres_w)                                                    ,
+                                                        
+        .vb_addra_c                                     (vb_addra_w)                                                    ,
+        .vb_dina_c                                      (vb_dina_w)                                                     ,
+        .vb_douta_g                                     (vb_douta_w)                                                    ,
+        .vb_ena_c                                       (vb_ena_w)                                                      ,
+        .vb_wea_c                                       (vb_wea_w)                                                      ,
+
+        .bb_wea_c                                       (bb_wea_w)                                                      ,
+        .bb_ena_c                                       (bat_bb_ena_w)                                                  ,
+        .bb_addra_c                                     (bat_bb_addra_w)                                                ,
+        .bb_dina_c                                      (bb_dina_w)                                                     ,
+
+        .s_axi_araddr_c                                 (s_axi_araddr_w)                                                ,                                    
+        .s_axi_arready_g                                (s_axi_arready_w)                                               ,                                     
+        .s_axi_arvalid_c                                (s_axi_arvalid_w)                                               ,
+        .s_axi_awaddr_c                                 (s_axi_awaddr_w)                                                ,
+        .s_axi_awready_g                                (s_axi_awready_w)                                               ,
+        .s_axi_awvalid_c                                (s_axi_awvalid_w)                                               ,
+        .s_axi_bready_c                                 (s_axi_bready_w)                                                ,
+        .s_axi_bresp_g                                  (s_axi_bresp_w)                                                 ,        
+        .s_axi_bvalid_g                                 (s_axi_bvalid_w)                                                ,
+        .s_axi_rdata_g                                  (s_axi_rdata_w)                                                 ,
+        .s_axi_rready_c                                 (s_axi_rready_w)                                                ,
+        .s_axi_rresp_g                                  (s_axi_rresp_w)                                                 ,    
+        .s_axi_rvalid_g                                 (s_axi_rvalid_w)                                                ,
+        .s_axi_wdata_c                                  (s_axi_wdata_w)                                                 ,
+        .s_axi_wready_g                                 (s_axi_wready_w)                                                ,
+        .s_axi_wstrb_c                                  (s_axi_wstrb_w)                                                 ,
+        .s_axi_wvalid_c                                 (s_axi_wvalid_w)        
+    );
+
+    localparam SLAVE_NUM = 1;
+    localparam [32*SLAVE_NUM - 1:0] bases = {32'h00000000};
+    localparam [32*SLAVE_NUM - 1:0] ranges = {32'h7fffffff};
+    
+    // INTER - SLAVE connections
+    // Write Address Channel
+    wire [SLAVE_NUM - 1:0]              AWVALID_s_w;
+    wire [SLAVE_NUM - 1:0]              AWREADY_s_w;
+    wire [`ADRES_BIT*SLAVE_NUM - 1:0]   AWADDR_s_w;
+    wire [3*SLAVE_NUM - 1:0]            AWPROT_s_w;
+    // Write Data Channel
+    wire [SLAVE_NUM - 1:0]              WVALID_s_w;
+    wire [SLAVE_NUM - 1:0]              WREADY_s_w;
+    wire [`VERI_BIT*SLAVE_NUM - 1:0]    WDATA_s_w;
+    wire [`VERI_BIT/8*SLAVE_NUM - 1:0]  WSTRB_s_w;
+    // Write Response Channel
+    wire [SLAVE_NUM - 1:0]              BVALID_s_w;
+    wire [SLAVE_NUM - 1:0]              BREADY_s_w;
+    wire [2*SLAVE_NUM - 1:0]            BRESP_s_w;
+    // Read Address Channel
+    wire [SLAVE_NUM - 1:0]              ARVALID_s_w;
+    wire [SLAVE_NUM - 1:0]              ARREADY_s_w;
+    wire [`ADRES_BIT*SLAVE_NUM - 1:0]   ARADDR_s_w;
+    wire [3*SLAVE_NUM - 1:0]            ARPROT_s_w;
+    // Read Data Channel
+    wire [SLAVE_NUM - 1:0]              RVALID_s_w;
+    wire [SLAVE_NUM - 1:0]              RREADY_s_w;
+    wire [`VERI_BIT*SLAVE_NUM - 1:0]    RDATA_s_w;
+    wire [2*SLAVE_NUM - 1:0]            RRESP_s_w;
+    
+    // SLAVE - PERIPHERAL connections
+    // Komut Kanali
+    wire [SLAVE_NUM - 1:0]              komut_hazir_p_w;
+    wire [SLAVE_NUM - 1:0]              komut_gecerli_p_w;
+    wire [`VERI_BIT*SLAVE_NUM - 1:0]    komut_p_w;
+    // Veri Kanali
+    wire [SLAVE_NUM - 1:0]              veri_hazir_p_w;
+    wire [SLAVE_NUM - 1:0]              veri_gecerli_p_w;
+    wire [`VERI_BIT*SLAVE_NUM - 1:0]    veri_p_w;    
+    
+    // INTERCONNECT
+    axi_interconnect #(.SLAVE_NUM(SLAVE_NUM),
+                       .bases(bases),
+                       .ranges(ranges)) 
+        interconnect0 (
+        // Masterside WAC
+        .m_axi_awaddr                                   (s_axi_awaddr_w),
+        .m_axi_awprot                                   (s_axi_awprot_w),
+        .m_axi_awvalid                                  (s_axi_awvalid_w),
+        .m_axi_awready                                  (s_axi_awready_w),
+        // Masterside WDC                                
+        .m_axi_wdata                                    (s_axi_wdata_w),
+        .m_axi_wstrb                                    (s_axi_wstrb_w),
+        .m_axi_wvalid                                   (s_axi_wvalid_w),
+        .m_axi_wready                                   (s_axi_wready_w),
+        // Masterside WRC                                
+        .m_axi_bresp                                    (s_axi_bresp_w),
+        .m_axi_bvalid                                   (s_axi_bvalid_w),
+        .m_axi_bready                                   (s_axi_bready_w),
+        // Masterside RAC                                
+        .m_axi_araddr                                   (s_axi_araddr_w),
+        .m_axi_arvalid                                  (s_axi_arvalid_w),
+        .m_axi_arready                                  (s_axi_arready_w),
+        .m_axi_arprot                                   (s_axi_arprot_w),
+        // Masterside RDC                                
+        .m_axi_rdata                                    (s_axi_rdata_w),
+        .m_axi_rresp                                    (s_axi_rresp_w),
+        .m_axi_rvalid                                   (s_axi_rvalid_w),
+        .m_axi_rready                                   (s_axi_rready_w),
+        // Slaveside WAC
+        .s_axi_awaddr                                   (AWADDR_s_w),
+        .s_axi_awprot                                   (AWPROT_s_w),
+        .s_axi_awvalid                                  (AWVALID_s_w),
+        .s_axi_awready                                  (AWREADY_s_w),
+        // Slaveside WDC
+        .s_axi_wdata                                    (WDATA_s_w),
+        .s_axi_wstrb                                    (WSTRB_s_w),
+        .s_axi_wvalid                                   (WVALID_s_w),
+        .s_axi_wready                                   (WREADY_s_w),
+        // Slaveside WRC
+        .s_axi_bresp                                    (BRESP_s_w),
+        .s_axi_bvalid                                   (BVALID_s_w),
+        .s_axi_bready                                   (BREADY_s_w),
+        // Slaveside RAC
+        .s_axi_araddr                                   (ARADDR_s_w),
+        .s_axi_arvalid                                  (ARVALID_s_w),
+        .s_axi_arready                                  (ARREADY_s_w),
+        .s_axi_arprot                                   (ARPROT_s_w),
+        // Slaveside RDC
+        .s_axi_rdata                                    (RDATA_s_w),
+        .s_axi_rresp                                    (RRESP_s_w),
+        .s_axi_rvalid                                   (RVALID_s_w),
+        .s_axi_rready                                   (RREADY_s_w)
+    );
+    
+    // SLAVE
+    genvar s;
+    generate
+        for(s = 0; s < SLAVE_NUM; s = s + 1) begin
+            axi_slave_gfi axi_slave(
+                .ACLK(clk_g),
+                .ARESET(rst_g),
+                .AWADDR(AWADDR_s_w[s*`ADRES_BIT +: `ADRES_BIT]),
+                .AWVALID(AWVALID_s_w[s]),
+                .AWPROT(AWPROT_s_w[s*3 +: 3]),
+                .AWREADY(AWREADY_s_w[s]),
+                .WDATA(WDATA_s_w[s*`VERI_BIT +: `VERI_BIT]),
+                .WSTRB(WSTRB_s_w[s*`VERI_BIT/8 +: `VERI_BIT/8]),
+                .WVALID(WVALID_s_w[s]),
+                .WREADY(WREADY_s_w[s]),
+                .BREADY(BREADY_s_w[s]),
+                .BVALID(BVALID_s_w[s]),
+                .BRESP(BRESP_s_w[s*2 +: 2]),
+                .ARADDR(ARADDR_s_w[s*`ADRES_BIT +: `ADRES_BIT]),
+                .ARVALID(ARVALID_s_w[s]),
+                .ARPROT(ARPROT_s_w[s*3 +: 3]),
+                .ARREADY(ARREADY_s_w[s]),
+                .RREADY(RREADY_s_w[s]),
+                .RDATA(RDATA_s_w[s*`VERI_BIT +: `VERI_BIT]),
+                .RVALID(RVALID_s_w[s]),
+                .RRESP(RRESP_s_w[s*2 +: 2]),
+                .komut_hazir(komut_hazir_p_w[s]),
+                //.komut_hazir(komut_hazir_tb[s]),
+                .komut_gecerli(komut_gecerli_p_w[s]),
+                .komut(komut_p_w[s*`VERI_BIT +: `VERI_BIT]),
+                .veri(veri_p_w[s*`VERI_BIT +: `VERI_BIT]),
+                //.veri(veri_tb[s*`VERI_BIT +: `VERI_BIT]),
+                .veri_gecerli(veri_gecerli_p_w[s]),
+                //.veri_gecerli(veri_gecerli_tb[s]),
+                .veri_hazir(veri_hazir_p_w[s])
+            );
+        end
+    endgenerate    
+    
+    UART_GFA uart(
+        .clk_g                                          (clk_g)                                                         ,
+        .rst_g                                          (rst_g)                                                           ,
+        
+        .komut_hazir                                    (komut_hazir_p_w[0])                                              ,
+        .komut_gecerli                                  (komut_gecerli_p_w[0])                                            ,
+        .komut                                          (komut_p_w[0 +: `VERI_BIT])                                       ,
+        .veri                                           (veri_p_w[0 +: `VERI_BIT])                                        ,    
+        .veri_gecerli                                   (veri_gecerli_p_w[0])                                             ,
+        .veri_hazir                                     (veri_hazir_p_w[0])                                               ,
+        
+        .RX                                             (rx)                                                            ,
+        .TX                                             (tx)
+    );
+
+    //==============================================================================
+    //                                CEKIRDEK & BELLEKLER
+    //==============================================================================    
+
+
+    cekirdek c0
+    (
+        .clk_g                                          (clk_g)                                                         ,
+        .rst_g                                          (rst_g)                                                         ,
+        .bb_buy_gecerli_g                               (bb_buy_gecerli_g_w)                                            ,
+        .bb_buy_g                                       (bb_buy_g_w)                                                    ,
+        .bb_buy_ps_g                                    (bb_buy_ps_g_w)                                                 ,
+ 
+        .bb_buy_istek_adres_c                           (bb_buy_istek_adres_c_w)                                        ,
+        .bb_buy_istek_c                                 (bb_buy_istek_c_w)                                              ,
+        
+        .gc_hazir_c                                     (gc_hazir_c_w)                                                  ,        
+        .kesme_g                                        (kesme_g_w)                                                     ,
+        .zamanlayici_kesme_g                            (zamanlayici_kesme_g_w)                                         ,
+        
+        .oku_hazir_g                                    (c0_oku_hazir_w)                                                ,
+        .oku_veri_g                                     (c0_oku_veri_w)                                                 ,
+        .oku_veri_gecerli_g                             (c0_oku_veri_gecerli_w)                                         ,
+        .yaz_hazir_g                                    (c0_yaz_hazir_w)                                                ,
+                                                         
+        .adres_c                                        (c0_adres_w)                                                    ,
+        .oku_gecerli_c                                  (c0_oku_gecerli_w)                                              ,
+        .yaz_veri_c                                     (c0_yaz_veri_w)                                                 ,
+        .yaz_gecerli_c                                  (c0_yaz_gecerli_w)                                              ,
+        .io_gecerli                                     (io_gecerli)                                          ,
+        .io_ps                                          (io_ps)  
+    );
+
+    assign                                              bb_clka_w         =       clk_g                                 ;
+    
+
+    baslangic_bellegi basbel
+    (
+      .clk_g                                            (clk_g)                                                         ,
+      .rst_g                                            (rst_g)                                                         ,
+      
+      .adres_g                                          (basbel_addra_w)                                                ,
+      .buyruk_c                                         (basbel_douta_w)                                                ,
+      .ena_g                                            (basbel_ena_w)
+    );
+
+    assign                                              bb_ena_w        =       bat_bb_ena_w | ot_bb_ena_w              ;
+    assign                                              bb_addra_w      =       (bb_wea_w != 0) ?
+                                                                                bat_bb_addra_w : (ot_bb_addra_w  >> 2)  ;    
+
+    // la_data_in'i buraya sentez aracini kandirmak icin bagliyoruz.
+    buyruk_bellegi_sram bb
+    (
+        .addra                                          (bb_addra_w)                                                    ,
+        .clka                                           (bb_clka_w)                                                     ,
+        .dina                                           (bb_dina_w)                                                     ,
+        .douta                                          (bb_douta_w)                                                    ,
+        .ena                                            (bb_ena_w)                                                      ,
+        .wea                                            (bb_wea_w)                                                      ,
+
+        .csb0                                           (bb_csb0)                                                       ,
+        .web0                                           (bb_web0)                                                       ,
+        .wmask0                                         (bb_wmask0)                                                     ,
+        .addr0                                          (bb_addr0)                                                      ,
+        .din0                                           (bb_din0)                                                       ,
+        .dout0                                          (bb_dout0)                                                      ,
+
+        .csb1                                           (bb_csb1)                                                       ,
+        .addr1                                          (bb_addr1)                                                      ,
+        .dout1                                          (bb_dout1)                                          
+    );
+    
+    assign                                              vb_clka_w       =       clk_g                                   ;
+    
+    
+    veri_bellegi_sram vb
+    (
+        .addra                                          (vb_addra_w)                                                    ,
+        .clka                                           (vb_clka_w)                                                     ,
+        .dina                                           (vb_dina_w)                                                     ,
+        .douta                                          (vb_douta_w)                                                    ,
+        .ena                                            (vb_ena_w)                                                      ,
+        .wea                                            (vb_wea_w)                                                      ,
+        
+        .csb0                                           (vb_csb0)                                                       ,
+        .web0                                           (vb_web0)                                                       ,
+        .wmask0                                         (vb_wmask0)                                                     ,
+        .addr0                                          (vb_addr0)                                                      ,
+        .din0                                           (vb_din0)                                                       ,
+        .dout0                                          (vb_dout0)                                                      ,
+
+        .csb1                                           (vb_csb1)                                                       ,
+        .addr1                                          (vb_addr1)                                                      ,
+        .dout1                                          (vb_dout1)                                          
+    );
+    on_taraf ot
+    (
+        .clk_g                                          (clk_g)                                                         ,
+        .rst_g                                          (rst_g)                                                         ,
+                                                                                                               
+        .gc_hazir_g                                     (gc_hazir_c_w)                                                  ,
+        .bb_buy_gecerli_c                               (bb_buy_gecerli_g_w)                                            ,
+        .bb_buy_c                                       (bb_buy_g_w)                                                    ,
+        .bb_buy_ps_c                                    (bb_buy_ps_g_w)                                                 ,
+        
+        .bb_buy_istek_adres_g                            (bb_buy_istek_adres_c_w)                                       ,
+        .bb_buy_istek_g                                  (bb_buy_istek_c_w)                                             ,                 
+        
+        .bb_addra_c                                     (ot_bb_addra_w)                                                    ,                                       
+        .bb_douta_g                                     (bb_douta_w)                                                    ,                                      
+        .bb_ena_c                                       (ot_bb_ena_w)                                                      ,
+
+        .basbel_addra_c                                 (basbel_addra_w)                                                ,                                       
+        .basbel_douta_g                                 (basbel_douta_w)                                                ,  
+        .basbel_ena_c                                   (basbel_ena_w)                                                   
+    );
+    
+endmodule
+
+`default_nettype wire
diff --git a/verilog/rtl/cekirdek.v b/verilog/rtl/cekirdek.v
new file mode 100644
index 0000000..b22e795
--- /dev/null
+++ b/verilog/rtl/cekirdek.v
@@ -0,0 +1,287 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module cekirdek(
+    `ifdef BASYS3
+    output          [15:0]                              fpga_demo_signal                                     ,
+    `endif
+
+    `ifdef GL_RTL_SIM
+    output                                              io_gecerli                                     ,
+    output          [`PS_BIT-1:0]                       io_ps                                     ,
+    `endif
+
+    input                                               clk_g                                                ,
+    input                                               rst_g                                                ,
+    
+    //    Buyruk Bellegi <-> GetirCoz
+    input                                               bb_buy_gecerli_g                                     ,
+    input           [`BUYRUK_BIT-1:0]                   bb_buy_g                                             ,
+    input           [`BB_ADRES_BIT-1:0]                 bb_buy_ps_g                                          ,
+    output                                              gc_hazir_c                                           ,
+    output          [`BB_ADRES_BIT-1:0]                 bb_buy_istek_adres_c                                 ,
+    output                                              bb_buy_istek_c                                       ,
+    
+    //    Kesme Denetleyicisi <-> DDB
+    input                                               kesme_g                                              ,
+    input                                               zamanlayici_kesme_g                                  ,  
+
+    //    Veri bellegi <-> C0
+    //    TODO: bunlar baglanmadi  
+    input                                               oku_hazir_g                                          ,
+    input           [31:0]                              oku_veri_g                                           ,
+    input                                               oku_veri_gecerli_g                                   ,
+    input                                               yaz_hazir_g                                          ,
+                                                                                                               
+    output                                              oku_gecerli_c                                        ,
+    output          [31:0]                              yaz_veri_c                                           ,
+    output          [3:0]                               yaz_gecerli_c                                        ,
+    output          [31:0]                              adres_c
+
+    
+    );
+    
+    //==============================================================================
+    //                                  GETIR-COZ
+    //==============================================================================
+
+   (* dont_touch = "true" *) wire                                                bb_buy_gecerli_w                                      ;
+    wire            [`BUYRUK_BIT-1:0]                   bb_buy_w                                              ;
+   (* dont_touch = "true" *) wire            [`BB_ADRES_BIT-1:0]                 bb_buy_ps_w                                           ;
+    wire                                                gc_hazir_w                                            ;
+    wire            [`UIS_BIT-1:0]                      gc_uis_w                                              ;  
+    wire                                                gc_odd_w                                              ;
+    wire            [31:0]                              gc_odd_ps_w                                           ;
+
+    //==============================================================================
+    //                             YAZMAC-OKU-YURUT
+    //==============================================================================
+    
+   (* dont_touch = "true" *) wire            [31:0]                              oku_veri_w                                            ;
+   (* dont_touch = "true" *) wire                                                oku_veri_gecerli_w                                    ;
+    wire                                                yaz_hazir_w                                           ;
+    wire                                                oku_hazir_w                                           ;
+    wire            [31:0]                              yo_ky1_veri_w                                         ;
+    wire            [31:0]                              yo_ky2_veri_w                                         ;
+
+    wire            [`UIS_BIT-1:0]                      yoy_uis_w                                             ; 
+    (* dont_touch = "true" *) wire                                                oku_gecerli_w                                         ;
+    wire                                                gc_duraklat_w                                         ;
+    wire            [31:0]                              siradaki_ps_w                                         ;
+    wire            [`ODD_BIT-1:0]                      yoy_odd_kod_w                                         ; 
+    wire                                                yoy_odd_w                                             ;
+    // @ismail bellek islemlerinde oddye yol acan buyruklarina adresi lazim
+    wire            [31:0]                              yoy_odd_adres_w                                       ;
+    // @ismail odd ps degeri lazim
+    wire            [31:0]                              yoy_odd_ps_w                                          ;
+    wire                                                gc_bosalt_w                                           ;
+    wire            [31:0]                              yaz_veri_w                                            ;
+    wire            [3:0]                               yaz_gecerli_w                                         ;
+    (* dont_touch = "true" *) wire            [31:0]                              adres_w                                               ; 
+    wire            [4:0]                               yo_ky1_adres_w                                        ;
+    wire            [4:0]                               yo_ky2_adres_w                                        ;
+
+    //==============================================================================
+    //                              DENETIM-DURUM-BIRIMI
+    //==============================================================================   
+    wire                                                kesme_w                                               ;
+    wire                                                zamanlayici_kesme_w                                   ;
+    wire            [`ODD_BIT-1:0]                      odd_kod_w                                             ;
+    wire            [`PS_BIT-1:0]                       odd_ps_w                                              ;
+    wire            [`ADRES_BIT-1:0]                    odd_adres_w                                           ;
+                                                                                               
+    wire                                                ddy_oku_gecerli_w                                     ;
+    wire            [11:0]                              ddy_oku_adres_w                                       ;
+    wire                                                ddy_yaz_gecerli_w                                     ;
+    wire            [11:0]                              ddy_yaz_adres_w                                       ;
+    wire            [31:0]                              ddy_yaz_veri_w                                        ;
+    wire            [31:0]                              ddy_oku_veri_w                                        ;
+                                                                                                
+    wire                                                odd_ps_al_gecerli_w                                   ;
+    wire            [`PS_BIT-1:0]                       odd_ps_al_w                                           ;  
+
+    //==============================================================================
+    //                                  YAZMAC-YAZ
+    //==============================================================================
+
+    wire                                                yo_yaz_w                                              ;
+    wire            [`HY_BIT - 1: 0]                    yo_yaz_hedef_w                                        ;
+    wire            [`HY_DEGER_BIT - 1: 0]              yo_yaz_veri_w                                         ;      
+
+    //==============================================================================
+    //                                  GETIR-COZ                                   
+    //==============================================================================
+    
+    assign                                              bb_buy_gecerli_w      =       bb_buy_gecerli_g        ;                                        
+    assign                                              bb_buy_w              =       bb_buy_g                ;                                        
+    assign                                              bb_buy_ps_w           =       bb_buy_ps_g             ;                                        
+
+    assign                                              gc_hazir_c            =       gc_hazir_w              ;
+
+    getir_coz gc
+    (
+        .clk_g                                          (clk_g)                                               ,                                                        
+        .rst_g                                          (rst_g)                                               ,       
+        .bb_buy_gecerli_g                               (bb_buy_gecerli_w)                                    , 
+        .bb_buy_g                                       (bb_buy_w)                                            , 
+        .bb_buy_ps_g                                    (bb_buy_ps_w)                                         , 
+        .gc_hazir_c                                     (gc_hazir_w)                                          , 
+        .gc_duraklat_g                                  (gc_duraklat_w)                                       , 
+        .gc_bosalt_g                                    (gc_bosalt_w)                                         , 
+        .gc_uis_c                                       (gc_uis_w)                                            ,   
+        .gc_odd_c                                       (gc_odd_w)                                            ,           
+        .gc_odd_ps_c                                    (gc_odd_ps_w)                                                    
+    );
+
+    //==============================================================================
+    //                             YAZMAC-OKU-YURUT
+    //==============================================================================   
+
+    assign                                              oku_veri_w            =       oku_veri_g              ;
+    assign                                              oku_veri_gecerli_w    =       oku_veri_gecerli_g      ;
+    assign                                              yaz_hazir_w           =       yaz_hazir_g             ;
+    assign                                              oku_hazir_w           =       oku_hazir_g             ;
+
+    assign                                              adres_c               =       adres_w                 ;
+    assign                                              oku_gecerli_c         =       oku_gecerli_w           ;
+    assign                                              yaz_veri_c            =       yaz_veri_w              ;
+    assign                                              yaz_gecerli_c         =       yaz_gecerli_w           ;
+
+    
+    yazmac_oku_yurut yoy
+    (
+        .clk_g                                          (clk_g)                                               ,
+        .rst_g                                          (rst_g)                                               ,
+        .gc_uis_g                                       (gc_uis_w)                                            ,  
+        .oku_veri_g                                     (oku_veri_w)                                          ,
+        .oku_veri_gecerli_g                             (oku_veri_gecerli_w)                                  ,
+        .yo_ky1_veri_g                                  (yo_ky1_veri_w)                                       ,
+        .yo_ky2_veri_g                                  (yo_ky2_veri_w)                                       ,
+        .ddy_oku_veri_g                                 (ddy_oku_veri_w)                                      ,
+        .bellek_hazir_g                                 (yaz_hazir_w && oku_hazir_w)                          ,
+
+        .yoy_uis_c                                      (yoy_uis_w)                                           , 
+        .oku_gecerli_c                                  (oku_gecerli_w)                                       ,
+        .gc_duraklat_c                                  (gc_duraklat_w)                                       ,
+        .siradaki_ps_c                                  (siradaki_ps_w)                                       ,
+        .yoy_odd_kod_c                                  (yoy_odd_kod_w)                                       , 
+        .yoy_odd_ps_c                                   (yoy_odd_ps_w)                                        , 
+        .yoy_odd_adres_c                                (yoy_odd_adres_w)                                     , 
+        .yoy_odd_c                                      (yoy_odd_w)                                           ,
+        .gc_bosalt_c                                    (gc_bosalt_w)                                         ,
+        .yaz_veri_c                                     (yaz_veri_w)                                          ,
+        .yaz_veri_maske_c                               (yaz_gecerli_w)                                       ,
+        .adres_c                                        (adres_w)                                             , 
+        .yo_ky1_adres_c                                 (yo_ky1_adres_w)                                      ,
+        .yo_ky2_adres_c                                 (yo_ky2_adres_w)                                      ,
+        .ddy_oku_adres_c                                (ddy_oku_adres_w)                                     ,                                                 
+        .ddy_oku_gecerli_c                              (ddy_oku_gecerli_w)                     
+    );
+ 
+    //==============================================================================
+    //                              DENETIM-DURUM-BIRIMI
+    //==============================================================================  
+
+    assign                                              kesme_w               =       kesme_g                 ;
+    assign                                              zamanlayici_kesme_w   =       zamanlayici_kesme_g     ;
+    
+    assign                                              odd_kod_w             =       yoy_odd_kod_w           ;
+                                        
+    assign                                              odd_ps_w              =       yoy_odd_w               ?
+                                                            yoy_odd_ps_w      :       gc_odd_ps_w             ;
+    
+    assign                                              odd_adres_w          =       yoy_odd_adres_w         ;
+
+    assign                                              bb_buy_istek_adres_c  =       odd_ps_al_gecerli_w     ?
+                                                            odd_ps_al_w       :       siradaki_ps_w           ;
+    
+    assign                                              bb_buy_istek_c        =       odd_ps_al_gecerli_w     |
+                                                                                      gc_bosalt_w             ; 
+                                        
+    
+    denetim_durum_birimi ddb
+    (
+        .clk_g                                          (clk_g)                                               ,
+        .rst_g                                          (rst_g)                                               ,
+        
+        .kesme_g                                        (kesme_w)                                             ,
+        .zamanlayici_kesme_g                            (zamanlayici_kesme_w)                                 ,
+        .gc_odd_g                                       (!yoy_odd_w && gc_odd_w)                              ,
+        .yoy_odd_g                                      (yoy_odd_w)                                           ,
+        .odd_kod_g                                      (odd_kod_w)                                           ,
+        .odd_ps_g                                       (odd_ps_w)                                            ,
+        .odd_adres_g                                    (odd_adres_w)                                         ,
+        
+        .oku_gecerli_g                                  (ddy_oku_gecerli_w)                                   ,
+        .oku_adres_g                                    (ddy_oku_adres_w)                                     ,
+        .yaz_gecerli_g                                  (ddy_yaz_gecerli_w)                                   ,
+        .yaz_adres_g                                    (ddy_yaz_adres_w)                                     ,
+        .yaz_veri_g                                     (ddy_yaz_veri_w)                                      ,
+        .oku_veri_c                                     (ddy_oku_veri_w)                                      ,
+        
+        .odd_ps_al_gecerli_c                            (odd_ps_al_gecerli_w)                                 ,
+        .odd_ps_al_c                                    (odd_ps_al_w)                   
+    );   
+
+
+    //==============================================================================
+    //                                  YAZMAC-YAZ
+    //==============================================================================
+    
+    yazmac_yaz yy
+    (
+        `ifdef GL_RTL_SIM
+        .io_gecerli                                     (io_gecerli)                                               ,
+        .io_ps                                          (io_ps)                                               ,
+        `endif
+
+        .clk_g                                          (clk_g)                                               ,
+        .yoy_uis_g                                      (yoy_uis_w)                                           ,
+
+        .yo_yaz_c                                       (yo_yaz_w)                                            ,
+        .yo_yaz_hedef_c                                 (yo_yaz_hedef_w)                                      ,
+        .yo_yaz_veri_c                                  (yo_yaz_veri_w)                                       ,
+        
+        .ddy_yaz_c                                      (ddy_yaz_gecerli_w)                                   ,
+        .ddy_yaz_hedef_c                                (ddy_yaz_adres_w)                                     ,
+        .ddy_yaz_veri_c                                 (ddy_yaz_veri_w)                                       
+    );
+
+    //==============================================================================
+    //                                  YAZMAC-OBEGI
+    //==============================================================================
+
+    yazmac_obegi yo     (
+        `ifdef BASYS3
+        .fpga_demo_signal                               (fpga_demo_signal)                                    ,
+        `endif
+        
+        .clk_g                                          (clk_g)                                               ,
+        .rst_g                                          (rst_g)                                               ,
+        .ky1_adres_g                                    (yo_ky1_adres_w)                                      ,
+        .ky2_adres_g                                    (yo_ky2_adres_w)                                      ,
+        .hy_adres_g                                     (yo_yaz_hedef_w)                                      , 
+        .hy_deger_g                                     (yo_yaz_veri_w)                                       ,
+        .yaz_g                                          (yo_yaz_w)                                            ,
+        .ky1_deger_c                                    (yo_ky1_veri_w)                                       ,
+        .ky2_deger_c                                    (yo_ky2_veri_w)
+    );
+                         
+endmodule
diff --git a/verilog/rtl/dallanma_birimi.v b/verilog/rtl/dallanma_birimi.v
new file mode 100644
index 0000000..2dcd343
--- /dev/null
+++ b/verilog/rtl/dallanma_birimi.v
@@ -0,0 +1,75 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "mikroislem.vh"
+`endif
+
+module dallanma_birimi(
+    input         [7:0]     islev_kodu_g                                   , // ?slev tipi girisi
+    input         [31:0]    ps_g                                           , //Program sayaci girisi
+    input         [31:0]    islec1_g                                       , //?lk islec
+    input         [31:0]    islec2_g                                       , //?kinci islec
+    input         [31:0]    anlik_g                                        ,  // Dallanma buyruklari icin anlik girisi
+    output reg    [31:0]    jal_sonuc_c                                    , // JAL ve JALR buyruklari icin hedef yazmaci degeri
+    output reg              dallanma_sonuc_c                               , //Dallanma buyruklari icin atliyorsa 1'b1, atlamiyorsa 1'b0 veren cikis
+    output reg    [31:0]    ps_c                                             //Guncellenmis program sayaci cikisi
+    );
+    
+    always@* begin
+        ps_c              = 0        ;
+        dallanma_sonuc_c  = 0        ;
+        jal_sonuc_c       = 0        ;
+        case(islev_kodu_g)
+            `JAL: begin
+                jal_sonuc_c = ps_g + 3'b100                                ;
+                ps_c        = ps_g + $signed(islec2_g)                     ; 
+            end
+            `JALR: begin
+            //ayrica risc-v'te anlik degeri 2'nin kati yapmak icin en anlamsiz bitin 0 
+            //yapilma olayi kodlanmamis
+                jal_sonuc_c      = ps_g + 3'b100; 
+                //burada iki islece de signed koydum ama emin degilim
+                ps_c             =  ($signed(islec1_g) +  $signed(islec2_g)) & -2 ;
+            end
+            `BEQ: begin
+                dallanma_sonuc_c =  $signed(islec1_g) ==  $signed(islec2_g);
+                ps_c             = ps_g +  $signed(anlik_g)                ;
+            end 
+            `BNE: begin
+                dallanma_sonuc_c =  $signed(islec1_g) != $signed(islec2_g) ;
+                ps_c             = ps_g +  $signed(anlik_g)                ;
+            end 
+            `BLT: begin
+                dallanma_sonuc_c = ($signed(islec1_g) < $signed(islec2_g)) ;
+                ps_c             = ps_g +  $signed(anlik_g)                ;
+            end 
+            `BLTU: begin
+                dallanma_sonuc_c =  islec1_g < islec2_g                    ;
+                ps_c             = ps_g +  $signed(anlik_g)                ;
+            end 
+            `BGE: begin
+                dallanma_sonuc_c = ($signed(islec1_g) >= $signed(islec2_g)); 
+                ps_c             = ps_g +  $signed(anlik_g)                ;
+            end 
+            `BGEU: begin
+                dallanma_sonuc_c =  islec1_g >= islec2_g                   ;
+                ps_c             = ps_g +  $signed(anlik_g)                ;
+            end 
+        endcase
+
+    end
+endmodule
diff --git a/verilog/rtl/denetim_durum_birimi.v b/verilog/rtl/denetim_durum_birimi.v
new file mode 100644
index 0000000..62e2bf0
--- /dev/null
+++ b/verilog/rtl/denetim_durum_birimi.v
@@ -0,0 +1,211 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps 
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module denetim_durum_birimi
+    (
+    input                               clk_g                                                               ,
+    input                               rst_g                                                               ,
+
+    // YOY, GC, Sistem <-> DDB
+    input                               kesme_g                                                             ,
+    input                               zamanlayici_kesme_g                                                 ,
+    input                               gc_odd_g                                                            ,
+    input                               yoy_odd_g                                                           ,
+    input        [`ODD_BIT-1:0]         odd_kod_g                                                           ,
+    input        [`PS_BIT-1:0]          odd_ps_g                                                            ,
+    input        [`ADRES_BIT-1:0]       odd_adres_g                                                         ,
+
+    // YOY <-> Denetim Durum Yazmaclari
+    input                               oku_gecerli_g                                                       ,
+    input        [11:0]                 oku_adres_g                                                         ,
+    input                               yaz_gecerli_g                                                       ,
+    input        [11:0]                 yaz_adres_g                                                         ,
+    input        [31:0]                 yaz_veri_g                                                          ,
+    output       [31:0]                 oku_veri_c                                                          ,
+
+    // DDB <-> Buyruk Bellegi
+    output                              odd_ps_al_gecerli_c                                                 ,
+    output       [`PS_BIT-1:0]          odd_ps_al_c                                                          
+    );
+
+    // ===================================================================================================
+    // ========================================= CSR YAZMACLARI ==========================================
+
+    // TODO, bunlar duzgunce doldurulabilir
+    // hartid == 0, cunku tek bir hardware threadimiz (tek cekirdek/tek thread) var
+    // ================================== INFORMATION REGISTERS ===========================================
+    wire          [31:0]                mvendorid_w         =       32'h00000000                            ;
+    wire          [31:0]                marchid_w           =       32'h00000000                            ;
+    wire          [31:0]                mimpid_w            =       32'h00000000                            ;
+    wire          [31:0]                mhartid_w           =       32'h00000000                            ;
+
+    // ======================================= TRAP SETUP ================================================
+    // MISA yazmacini read only bir sekilde implement ediyoruz.
+    // Aslinda bu yazmac WARL, write-any-read-legal, yani herhangi bir deger yazilabilir
+    // ancak okunan degerler legal olmali. Yazma yapildiginda exception'a yol acmayacak
+    // read-only bir yazmac bu tanimlamaya uyuyor.
+    wire          [31:0]                misa_w = 32'b010000_000001000000X100100000000; // TODO X: User-level interrupts
+    // Bunlar 0, trap handling isini usera birakmayacagiz.
+    reg           [31:0]                medeleg_w           =       32'b00000000                            ;
+    reg           [31:0]                mideleg_w           =       32'h00000000                            ;
+    // XS & FS = 0 (FP ve additional state gerektiren extensionlarimiz yok)
+    // SD = 0, yukaridakilerden oturu
+    // SIE, SPIE, UIE, UPIE = 0
+    // MPIE = machine previous interrupt enable? interrupt trapi oldugunda: MPIE = MIE, MIE = 0, MPP = M
+    // MPP = machine previous privilege mode?
+    // MRET calisinca: MIE = MPIE, MPIE = 1, MPP = M
+
+    reg           [31:0]                mstatus_r, mstatus_ns_r                                             ;
+    // machine interrupt enable/pending registerlari
+    //  bit3: software interrupt e/p
+    //  bit7: timer interrupt e/p
+    //  bit11: external interrupt e/p
+    // mie ve mip'te ayni iki bit set ise (yani interrupt enable ve interrupt geldi) interrupt handle edilir
+    reg           [31:0]                mie_r, mie_ns_r                                                     ;
+    reg           [31:0]                mip_r, mip_ns_r                                                     ;
+    // Trap vector. Bunu bootloader dolduracak.
+    reg           [31:0]                mtvec_r, mtvec_ns_r                                                 ;
+    reg           [31:0]                mcounteren_r, mcounteren_ns_r                                       ;
+    // ===================================== TRAP HANDLING ===============================================
+    // Galiba context switch yapildiginda context switchlenen verinin bellekteki adresine isaret ediyor
+    reg           [31:0]                mscratch_r, mscratch_ns_r                                           ;
+    // trap'a yol acan buyrugun program sayaci
+    reg           [31:0]                mepc_r, mepc_ns_r                                                   ;
+    reg           [31:0]                mcause_r, mcause_ns_r                                               ;
+    // load/store/if faultlarinda, page-faultlarda, misaligned load/storelarda sanal adresi kaydeden yazmac
+    reg           [31:0]                mtval_r, mtval_ns_r                                                 ;
+    // ==================================== COUNTERS/TIMERS ==============================================
+    reg           [31:0]                mcycle_r, mcycle_ns_r                                               ;
+    reg           [31:0]                minstret_r, minstret_ns_r                                           ;
+    
+    // ===================================================================================================
+    // ====================================== DURUM DEGISKENLERI =========================================    
+
+    reg                                 odd_ps_al_gecerli_r                                                 ;
+    reg           [31:0]                oku_veri_r                                                          ;
+
+    // ===================================================================================================
+    // ========================================MODUL TANIMLAMASI==========================================
+
+
+    assign                              odd_ps_al_c             = odd_kod_g == `KDD_MRET ? mepc_r : mtvec_r ;
+    assign                              odd_ps_al_gecerli_c     = odd_ps_al_gecerli_r                       ;
+    assign                              oku_veri_c              = oku_veri_r                                ;
+
+
+    // TODOlar (oncelige gore): 
+    //      - interruptlari handle et
+    //      - privilege duzeyini tutan register priv-spec'te belirtilmemis
+    //              bunu yine de tutmamiz gerekiyor mu?
+    //      - instret'i fonksiyonel hale getir
+    always @* begin
+        odd_ps_al_gecerli_r            =               0                                                    ;
+        mie_ns_r                       =               mie_r                                                ;
+        mip_ns_r                       =               mip_r                                                ;
+        mtvec_ns_r                     =               mtvec_r                                              ;
+        mcounteren_ns_r                =               mcounteren_r                                         ;
+        mscratch_ns_r                  =               mscratch_r                                           ;
+        mepc_ns_r                      =               mepc_r                                               ;
+        mcause_ns_r                    =               mcause_r                                             ;
+        mtval_ns_r                     =               mtval_r                                              ;
+        mcycle_ns_r                    =               mcycle_r + 1'b1                                      ;
+        minstret_ns_r                  =               minstret_r                                           ;
+        mstatus_ns_r                   =               mstatus_r                                            ;
+        oku_veri_r                     =               0                                                    ;
+  
+        // Kural disi durum denetimi
+        if (gc_odd_g) begin
+            mepc_ns_r                  =               odd_ps_g                                             ;
+            mtval_ns_r                 =               32'b0                                                ;
+            mcause_ns_r                =               `KDD_YB                                              ;
+            odd_ps_al_gecerli_r        =               `HIGH                                                ;
+        end
+        else if (yoy_odd_g) begin
+            if (odd_kod_g == `KDD_MRET) begin
+                mstatus_ns_r[`MSTATUS_MIE]          =        mstatus_r[`MSTATUS_MPIE]                       ;
+                mstatus_ns_r[`MSTATUS_MPIE]         =        `HIGH                                          ;
+                mstatus_ns_r[`MSTATUS_MPP +: 2]     =        `PRIV_MACHINE                                  ;
+            end 
+            mepc_ns_r                  =               odd_ps_g                                             ;
+            mtval_ns_r                 =               odd_adres_g                                          ;
+            mcause_ns_r                =               odd_kod_g                                            ;
+            odd_ps_al_gecerli_r        =               `HIGH                                                ;
+        end
+
+        // Okuma islemi
+        if(oku_gecerli_g) begin  
+            case (oku_adres_g)
+                `DDY_MSCRATCH: oku_veri_r       =       mscratch_r                                          ;
+                `DDY_MEPC:     oku_veri_r       =       mepc_r                                              ;
+                `DDY_MTVEC:    oku_veri_r       =       mtvec_r                                             ;
+                `DDY_MCAUSE:   oku_veri_r       =       mcause_r                                            ;
+                `DDY_MTVAL:    oku_veri_r       =       mtval_r                                             ;
+                `DDY_MSTATUS:  oku_veri_r       =       mstatus_r                                           ;
+                `DDY_MIP:      oku_veri_r       =       mip_r                                               ;
+                `DDY_MIE:      oku_veri_r       =       mie_r                                               ;
+                `DDY_MCYCLE:   oku_veri_r       =       mcycle_r                                            ;
+                `DDY_MTIME:    oku_veri_r       =       minstret_r                                          ;  
+            endcase     
+        end             
+        
+        // Yazma islemi     
+        if(yaz_gecerli_g) begin     
+            case (yaz_adres_g)      
+                `DDY_MSCRATCH: mscratch_ns_r    =       yaz_veri_g                                          ;
+                `DDY_MEPC:     mepc_ns_r        =       yaz_veri_g                                          ;
+                `DDY_MTVEC:    mtvec_ns_r       =       yaz_veri_g                                          ;
+                `DDY_MCAUSE:   mcause_ns_r      =       yaz_veri_g                                          ;
+                `DDY_MTVAL:    mtval_ns_r       =       yaz_veri_g                                          ;
+                `DDY_MSTATUS:  mstatus_ns_r     =       yaz_veri_g                                          ;
+                `DDY_MIP:      mip_ns_r         =       yaz_veri_g                                          ;
+                `DDY_MIE:      mie_ns_r         =       yaz_veri_g                                          ;           
+            endcase
+        end
+
+    end
+
+    always @ (posedge clk_g) begin  
+        if(rst_g) begin
+            mepc_r                              <=      0                                                   ;
+            mstatus_r                           <=      0                                                   ;
+            mcause_r                            <=      0                                                   ;
+            mtval_r                             <=      0                                                   ;
+            mtvec_r                             <=      0                                                   ;
+            mip_r                               <=      0                                                   ;
+            mie_r                               <=      0                                                   ;
+            mcycle_r                            <=      0                                                   ;
+            minstret_r                          <=      0                                                   ;
+            mscratch_r                          <=      0                                                   ;
+        end
+        else begin
+            mepc_r                              <=      mepc_ns_r                                           ;
+            mstatus_r                           <=      mstatus_ns_r                                        ;
+            mcause_r                            <=      mcause_ns_r                                         ;
+            mtval_r                             <=      mtval_ns_r                                          ;
+            mtvec_r                             <=      mtvec_ns_r                                          ;
+            mip_r                               <=      mip_ns_r                                            ;
+            mie_r                               <=      mie_ns_r                                            ;
+            mcycle_r                            <=      mcycle_ns_r                                         ;
+            minstret_r                          <=      minstret_ns_r                                       ;
+            mscratch_r                          <=      mscratch_ns_r                                       ;
+        end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/getir_coz.v b/verilog/rtl/getir_coz.v
new file mode 100644
index 0000000..1c9ec36
--- /dev/null
+++ b/verilog/rtl/getir_coz.v
@@ -0,0 +1,385 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`include "mikroislem.vh"
+`endif
+
+module getir_coz
+    (
+    input                               clk_g                                                               ,
+    input                               rst_g                                                               ,
+
+    // Buyruk bellegi <-> GetirCoz
+    input                               bb_buy_gecerli_g                                                    ,
+    input        [`BUYRUK_BIT-1:0]      bb_buy_g                                                            ,
+    input        [`BB_ADRES_BIT-1:0]    bb_buy_ps_g                                                         ,
+    output                              gc_hazir_c                                                          ,
+
+    // GetirCoz <-> YazmacOkuYurut
+    input                               gc_duraklat_g                                                       ,
+    input                               gc_bosalt_g                                                         ,
+    output       [`UIS_BIT-1:0]         gc_uis_c                                                            ,  
+
+    // GetirCoz <-> DDY birimi
+    output                              gc_odd_c                                                            ,
+    output      [`BB_ADRES_BIT-1:0]     gc_odd_ps_c                                                                      
+    );
+
+    // ===================================================================================================
+    // ========================================MODUL TANIMLAMASI==========================================
+    // ===================================================================================================
+
+    // Getirilen buyruk
+    wire         [`BUYRUK_BIT-1:0]       buyruk_w          = bb_buy_g                                       ;
+
+    // Buyruk cozmek icin gereken sinyaller
+    wire         [`BUY_ISKODU_BIT-1:0]   iskodu_w          = buyruk_w[`BUY_ISKODU +: `BUY_ISKODU_BIT]       ;
+    wire         [`BUY_HY_BIT-1:0]       hy_w              = buyruk_w[`BUY_HY +: `BUY_HY_BIT]               ;
+    wire         [`BUY_KY1_BIT-1:0]      ky1_w             = buyruk_w[`BUY_KY1 +: `BUY_KY1_BIT]             ;
+    wire         [`BUY_KY2_BIT-1:0]      ky2_w             = buyruk_w[`BUY_KY2 +: `BUY_KY2_BIT]             ;
+    wire         [`BUY_F7_BIT-1:0]       f7_w              = buyruk_w[`BUY_F7 +: `BUY_F7_BIT]               ;
+    wire         [`BUY_F3_BIT-1:0]       f3_w              = buyruk_w[`BUY_F3 +: `BUY_F3_BIT]               ;
+
+    // Mikroislem sinyalleri
+    wire                                     gecerli_w                                                      ;
+    reg          [`YURUT_KODU_BIT - 1: 0]    yurut_kodu_r                                                   ;
+    reg          [`ISLEV_KODU_BIT - 1: 0]    islev_kodu_r                                                   ;
+    reg          [`IS1_SEC_BIT - 1: 0]       is1_sec_r                                                      ;
+    reg          [`IS2_SEC_BIT - 1: 0]       is2_sec_r                                                      ;
+    reg          [`ANLIK_DEGER_BIT - 1: 0]   anlik_deger_r                                                  ; 
+    reg                                      yukle_buyrugu_r                                                ;
+    reg                                      kaydet_buyrugu_r                                               ;
+    reg                                      fence_buyrugu_r                                                ;
+    reg                                      bellek_turu_w_r                                                ;
+    reg                                      bellek_turu_hw_r                                               ;
+    reg                                      bellek_isaretli_r                                              ;
+    reg                                      bellek_turu_b_r                                                ;
+    reg          [`PS_BIT - 1: 0]            ps_r                                                           ;
+
+    reg          [`UIS_BIT - 1: 0]           gc_uis_r                                                       ;
+    reg          [`UIS_BIT - 1: 0]           yazmac_gc_uis_r                                                ;
+
+    // Comb. devrede hesaplanan sinyaller
+    reg          [31:0]                      i_anlik                                                        ;
+    reg          [31:0]                      u_anlik                                                        ;
+    reg          [31:0]                      j_anlik                                                        ;
+    reg          [31:0]                      s_anlik                                                        ;
+    reg          [31:0]                      b_anlik                                                        ;
+
+    wire                                     yanlis_buyruk_w                                                ;
+
+    // denetim sayilabilecek sinyaller
+    assign                                  gecerli_w               =       bb_buy_gecerli_g && ~gc_bosalt_g;
+    assign                                  yanlis_buyruk_w         =       islev_kodu_r == 0               ;
+    assign                                  gc_hazir_c              =       !gc_duraklat_g;
+    assign                                  gc_uis_c                =       yazmac_gc_uis_r                 ;    
+    assign                                  gc_odd_c                =       gecerli_w && yanlis_buyruk_w    ;
+    assign                                  gc_odd_ps_c             =       ps_r                            ;
+
+    // Cozmek icin kocaman bir if else/switch agaci koyacagiz.
+    // Ataberk: Raven-SoC'deki kod da bu (^) sekilde.
+    always @* begin
+        gc_uis_r                        =               yazmac_gc_uis_r                                     ;
+        // Tum reglerin degerlerini belirle, latch olusturmak istemiyoruz.
+        //gecerli_w                       =               0                                                   ;
+        yurut_kodu_r                    =               0                                                   ;
+        islev_kodu_r                    =               0                                                   ;
+        is1_sec_r                       =               0                                                   ;
+        is2_sec_r                       =               0                                                   ;
+        anlik_deger_r                   =               0                                                   ;
+        yukle_buyrugu_r                 =               0                                                   ;
+        kaydet_buyrugu_r                =               0                                                   ;
+        fence_buyrugu_r                 =               0                                                   ;
+        bellek_turu_w_r                 =               0                                                   ;
+        bellek_turu_hw_r                =               0                                                   ;
+        bellek_turu_b_r                 =               0                                                   ;
+        bellek_isaretli_r               =               0                                                   ;
+        ps_r                            =               bb_buy_ps_g                                         ;
+
+        
+
+        // -------------------------- anlik deger hesapla --------------------------
+        // TODO: asagidakileri kontrol et
+        i_anlik = buyruk_w[`I_ANLIK_ISARET] ? {{20{1'b1}}, 
+                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]} 
+                                            : 
+                                              {{20{1'b0}},
+                                                buyruk_w[`I_ANLIK+:`I_ANLIK_BIT]};
+        u_anlik = buyruk_w[`U_ANLIK+:`U_ANLIK_BIT];
+        
+        // J, S ve B tipi anliklar icin tum indisleri `define'lamak kafa
+        // karistirici olabilir, o yuzden yoklar
+        // Asagidaki bit alanlari icin riscv tanimlamasina bakabilirsiniz.
+        j_anlik = { (buyruk_w[19] ? {11{1'b1}} : {11{1'b0}}),
+                    buyruk_w[19], 
+                    buyruk_w[12+:8],
+                    buyruk_w[20],
+                    buyruk_w[21+:10],
+                    1'b0
+                  };
+        s_anlik = { (buyruk_w[31] ? {20{1'b1}} : {20{1'b0}}),
+                    buyruk_w[25+:7],
+                    buyruk_w[7+:5]
+                  };
+        b_anlik = { (buyruk_w[31] ? {19{1'b1}} : {19{1'b0}}),
+                    buyruk_w[31],
+                    buyruk_w[7],
+                    buyruk_w[25+:6],
+                    buyruk_w[8+:4],
+                    1'b0
+                  };
+        
+        // --------------------------- islec sec -----------------------------------
+        if (iskodu_w == 7'h3 || iskodu_w == 7'h67 || iskodu_w == 7'h13) begin
+            is1_sec_r = `IS1_SEC_KY1;
+            is2_sec_r = `IS2_SEC_AD;
+            anlik_deger_r = i_anlik;
+        end
+        
+        if (iskodu_w == 7'h37) begin
+            is1_sec_r = `IS1_SEC_0;
+            is2_sec_r = `IS2_SEC_AD;
+            anlik_deger_r = u_anlik;
+        end
+        
+        if (iskodu_w == 7'h17) begin
+            is1_sec_r = `IS1_SEC_PS;
+            is2_sec_r = `IS2_SEC_AD;
+            anlik_deger_r = u_anlik;
+        end
+
+        if (iskodu_w == 7'h6f) begin
+            is1_sec_r = `IS1_SEC_PS;
+            is2_sec_r = `IS2_SEC_AD;
+            anlik_deger_r = j_anlik;
+        end
+
+        if (iskodu_w == 7'h63) begin
+            is1_sec_r = `IS1_SEC_KY1;
+            is2_sec_r = `IS2_SEC_KY2;
+            anlik_deger_r = b_anlik;
+        end
+
+        if (iskodu_w == 7'h23) begin
+            is1_sec_r = `IS1_SEC_KY1;
+            is2_sec_r = `IS2_SEC_KY2;
+            anlik_deger_r = s_anlik;
+        end
+
+        if (iskodu_w == 7'h33) begin
+            is1_sec_r = `IS1_SEC_KY1;
+            is2_sec_r = `IS2_SEC_KY2;
+        end
+        
+        if (iskodu_w == 7'h73) begin
+            is1_sec_r = `IS1_SEC_KY1;
+            is2_sec_r = `IS2_SEC_AD;
+        end
+        
+        // -------------------- yurut ve islev kodu belirle ------------------------
+        // TODO: hint parallel case
+        case (iskodu_w)
+            7'h37: begin // LUI 
+                yurut_kodu_r = `YURUT_KODU_AMB;
+                islev_kodu_r = `LUI;
+            end 
+            7'h17: begin // AUIPC
+                yurut_kodu_r = `YURUT_KODU_AMB;
+                islev_kodu_r = `AUIPC;            
+            end
+            7'h13: begin
+                yurut_kodu_r = `YURUT_KODU_AMB;
+                case (f3_w)
+                3'h0: islev_kodu_r = `ADD; 
+                3'h1: islev_kodu_r = `SLL;
+                3'h2: islev_kodu_r = `SLT;
+                3'h3: islev_kodu_r = `SLTU;
+                3'h4: islev_kodu_r = `XOR;
+                3'h5: islev_kodu_r = f7_w[5] ? `SRA : `SRL; 
+                3'h6: islev_kodu_r = `OR;
+                3'h7: islev_kodu_r = `AND;
+                endcase
+            end
+            7'h33: begin
+                if (f7_w[0]) begin
+                    yurut_kodu_r = f3_w < 3'h4 ? `YURUT_KODU_TCB : `YURUT_KODU_TBB;
+                    case (f3_w)
+                    3'h0: islev_kodu_r = `MUL; 
+                    3'h1: islev_kodu_r = `MULH;
+                    3'h2: islev_kodu_r = `MULHSU;
+                    3'h3: islev_kodu_r = `MULHU;
+                    3'h4: islev_kodu_r = `DIV;
+                    3'h5: islev_kodu_r = `DIVU; 
+                    3'h6: islev_kodu_r = `REM;
+                    3'h7: islev_kodu_r = `REMU;
+                    endcase                
+                end
+                else begin
+                    yurut_kodu_r = `YURUT_KODU_AMB;
+                    case (f3_w)
+                    3'h0: islev_kodu_r = f7_w[5] ? `SUB : `ADD; 
+                    3'h1: islev_kodu_r = `SLL;
+                    3'h2: islev_kodu_r = `SLT;
+                    3'h3: islev_kodu_r = `SLTU;
+                    3'h4: islev_kodu_r = `XOR;
+                    3'h5: islev_kodu_r = f7_w[5] ? `SRA : `SRL; 
+                    3'h6: islev_kodu_r = `OR;
+                    3'h7: islev_kodu_r = `AND;
+                    endcase                
+                end
+            end
+            7'h6f: begin
+                yurut_kodu_r = `YURUT_KODU_DB;
+                islev_kodu_r = `JAL;
+            end
+            7'h67: begin
+                yurut_kodu_r = `YURUT_KODU_DB;
+                islev_kodu_r = `JALR;
+            end
+            7'h63: begin
+                yurut_kodu_r = `YURUT_KODU_DB;
+                case (f3_w)
+                3'h0: islev_kodu_r = `BEQ; 
+                3'h1: islev_kodu_r = `BNE;
+                3'h4: islev_kodu_r = `BLT;
+                3'h5: islev_kodu_r = `BGE; 
+                3'h6: islev_kodu_r = `BLTU;
+                3'h7: islev_kodu_r = `BGEU;
+                endcase
+            end
+            7'h03: begin
+                yurut_kodu_r = `YURUT_KODU_BIB;
+                yukle_buyrugu_r = 1'b1;
+                case (f3_w)
+                3'h0: begin
+                islev_kodu_r = `LB;
+                bellek_turu_b_r = 1'b1;
+                bellek_isaretli_r = 1'b1; 
+                end
+                3'h1: begin
+                islev_kodu_r = `LH;
+                bellek_turu_hw_r = 1'b1;
+                bellek_isaretli_r = 1'b1; 
+                end
+                3'h2: begin
+                islev_kodu_r = `LW;
+                bellek_turu_w_r = 1'b1;
+                bellek_isaretli_r = 1'b1; 
+                end
+                3'h4: begin
+                islev_kodu_r = `LBU;
+                bellek_turu_b_r = 1'b1;
+                end
+                3'h5: begin
+                islev_kodu_r = `LHU;
+                bellek_turu_hw_r = 1'b1;
+                end
+                endcase           
+            end
+            7'h23: begin
+                yurut_kodu_r = `YURUT_KODU_BIB;
+                kaydet_buyrugu_r = 1'b1;
+                case (f3_w)
+                3'h0: begin
+                islev_kodu_r = `SB;
+                bellek_turu_b_r = 1'b1;
+                end
+                3'h1: begin
+                islev_kodu_r = `SH;
+                bellek_turu_hw_r = 1'b1;
+                end
+                3'h2: begin
+                islev_kodu_r = `SW;
+                bellek_turu_w_r = 1'b1;
+                end
+                endcase           
+            end    
+            7'h0f: begin
+                yurut_kodu_r = `YURUT_KODU_BIB;
+                fence_buyrugu_r = 1'b1;
+                if (f3_w == 0) islev_kodu_r = `FENCE;
+            end  
+            7'h73: begin
+                // CSR
+                yurut_kodu_r = `YURUT_KODU_CSR;
+                if (f3_w == 0) begin
+                    yurut_kodu_r = `YURUT_KODU_SISTEM;
+                    if (ky2_w == 'h1) islev_kodu_r = `EBREAK;
+                    if (ky2_w == 'h0) islev_kodu_r = `ECALL;
+                    if (ky2_w == 'h2) begin 
+                        if (f7_w == 'h0) islev_kodu_r = `URET;
+                        if (f7_w == 'h18) islev_kodu_r = `MRET;
+                    end
+                end
+                if (f3_w == 'h1)  islev_kodu_r = `CSRRW;
+                if (f3_w == 'h2)  islev_kodu_r = `CSRRS;
+                if (f3_w == 'h3)  islev_kodu_r = `CSRRC;
+                if (f3_w == 'h5)  islev_kodu_r = `CSRRWI;
+                if (f3_w == 'h6)  islev_kodu_r = `CSRRSI;
+                if (f3_w == 'h7)  islev_kodu_r = `CSRRCI;
+            end        
+        endcase
+
+        // ------------------------------ denetim ----------------------------------
+        // ancak ve ancak islev kodu belirlenmediyse
+        // yanlis buyruk oddsi olusur
+        
+        
+        
+        gc_uis_r[`GECERLI]                              = gecerli_w  && ~yanlis_buyruk_w;
+        // TODO: if icinde olmasi davranisi degistiriyor mu?
+        if (gecerli_w) begin
+            // mikroislem sinyallerini bagla
+            // TODO: DDB alanlarini doldur
+            gc_uis_r[`YURUT_KODU+:`YURUT_KODU_BIT]      = yurut_kodu_r;
+            gc_uis_r[`ISLEV_KODU+:`ISLEV_KODU_BIT]      = islev_kodu_r;
+            gc_uis_r[`IS1_SEC+:`IS1_SEC_BIT]            = is1_sec_r;
+            gc_uis_r[`IS2_SEC+:`IS2_SEC_BIT]            = is2_sec_r;
+            gc_uis_r[`ANLIK_DEGER+:`ANLIK_DEGER_BIT]    = anlik_deger_r;
+            gc_uis_r[`KY1+:`KY1_BIT]                    = ky1_w;
+            gc_uis_r[`KY2+:`KY2_BIT]                    = ky2_w;
+            gc_uis_r[`YUKLE_BUYRUGU]                    = yukle_buyrugu_r;
+            gc_uis_r[`KAYDET_BUYRUGU]                   = kaydet_buyrugu_r;
+            gc_uis_r[`FENCE_BUYRUGU]                    = fence_buyrugu_r;
+            gc_uis_r[`BELLEK_TURU_W]                    = bellek_turu_w_r;
+            gc_uis_r[`BELLEK_TURU_HW]                   = bellek_turu_hw_r;
+            gc_uis_r[`BELLEK_TURU_B]                    = bellek_turu_b_r;
+            gc_uis_r[`BELLEK_ISARETLI]                  = bellek_isaretli_r;
+            gc_uis_r[`HY+:`HY_BIT]                      = hy_w;
+            gc_uis_r[`PS+:`PS_BIT]                      = ps_r;
+            gc_uis_r[`DDY_ADRES+:`DDY_ADRES_BIT]        = i_anlik;
+            gc_uis_r[`DDY_ANLIK+:`DDY_ANLIK_BIT]        = ky1_w;
+        end
+    end
+
+    always @(posedge clk_g) begin
+        if (rst_g) begin
+            //yazmac_gc_uis_r[`GECERLI] <= 1'b0;
+            yazmac_gc_uis_r <= 0;
+        end
+        else begin
+            if (gc_duraklat_g) begin
+                yazmac_gc_uis_r <= yazmac_gc_uis_r;
+            end
+            else begin
+                yazmac_gc_uis_r <= gc_uis_r;
+            end
+        end
+    end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/iki_bit_adimli_bolucu.v b/verilog/rtl/iki_bit_adimli_bolucu.v
new file mode 100644
index 0000000..9b8acd3
--- /dev/null
+++ b/verilog/rtl/iki_bit_adimli_bolucu.v
@@ -0,0 +1,164 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+
+module iki_bit_adimli_bolucu(
+    input                   rst_g,
+    input       [31:0]      a_g,
+    input       [31:0]      b_g,
+    input                   istek,
+    input                   isaretli,
+    input                   overflow,
+    input                   divbyzero,
+    input                   clk,
+    output      [31:0]      bolum,
+    output      [31:0]      kalan,
+    output      reg         bitti=0
+    );
+    
+    /*
+        İlk sayı sabit kalırken ikinci sayıyı 31 birim sola kaydırıyoruz kısaca 2^31 ile çarpmış oluyoruz.
+        Daha sonra ikinci sayıyı birinciden çıkarıyoruz. Çıkardığımızda negatif bir sayı çıkıyorsa o çarpım içinde yok demektir.
+        Var ise bölümü o basamaktaki değer bir oluyor ve ilk sayı yerine artık çıkarılmış halini kullanıyoruz.
+        Tek saat dönümü içinde iki bit iki bit ilerlemeli olduğu için bir kaydırılmış hali ile yine bir çıkarma ve kontrol işlemi yapıyoruz.
+        Negatif sayılar alınırken positif halleriyle alınıyor ve kalansızsa sadece sonucu negatife çeviriyoruz.
+        Kalan var ise sonuç negatifinin bir eksiği ve kalan ikinci sayıdan kalanın çıkarılması ile bulunuyor.
+    */
+    
+    localparam EVET = 1'b1;
+    localparam HAYIR = 1'b0;
+    
+    // bölme işlemine 2^31 sayısıyla başlıyor
+    localparam BOLME_BASLANGIC = 32'b1000_0000_0000_0000_0000_0000_0000_0000;
+    
+    reg [31:0] A, A_next;
+    reg [63:0] B, B_next;
+    reg [31:0] bolum, bolum_next;
+    reg [31:0] kalan, kalan_next;
+    
+    // o anda hangi basamakta olduğu değeri, ikinci de ikinci çıkarma işlemi için
+    reg [31:0] bolme_basamagi, bolme_basamagi_next = BOLME_BASLANGIC;
+    wire [31:0] ikinci_bolme_basamagi = {1'b0, bolme_basamagi[31:1]};
+    
+    reg hesaplaniyor = HAYIR, hesaplaniyor_next = HAYIR; 
+    reg sonuc_ver = HAYIR, sonuc_ver_next = HAYIR;
+    
+    reg bitti_next = 0;
+    
+    
+    wire A_negatif_mi = isaretli & a_g[31];
+    wire B_negatif_mi = isaretli & b_g[31];
+    
+    wire sonuc_negatif_mi = A_negatif_mi ^ B_negatif_mi;
+    
+    // sayının çıkarıldığı yer [32:0] olması bazı taşma durumları için
+    wire [32:0] ilk_cikarma_sonucu = A - B[31:0];
+    wire ilk_cikarma_sonucu_negatif_mi = ilk_cikarma_sonucu[32];
+    wire ilk_cikarma_b_de_tasma_var_mi = |B[63:32];
+    // eğer çıkarttığımızda pozitif bir sayı elde ediyorsak çıkarma işlemini yapmalıyız
+    wire ilk_cikarmayi_yap = ~ (ilk_cikarma_sonucu_negatif_mi | ilk_cikarma_b_de_tasma_var_mi);
+    // ilk çıkartmadan sonraki değer
+    wire [31:0] A_ilk_cikarma_sonrasi = ( ilk_cikarmayi_yap ? ilk_cikarma_sonucu[31:0] : A );
+    
+    // ikinci çıkartmada ikinci sayının bir kaydırılmış hali ve ona göre taşma sonucuna bakıyoruz
+    wire [32:0] ikinci_cikarma_sonucu = A_ilk_cikarma_sonrasi - B[32:1];
+    wire ikinci_cikarma_sonucu_negatif_mi = ikinci_cikarma_sonucu[32];
+    wire ikinci_cikarma_b_de_tasma_var_mi = |B[63:33];
+    wire ikinci_cikarmayi_yap = ~ (ikinci_cikarma_sonucu_negatif_mi | ikinci_cikarma_b_de_tasma_var_mi);
+    // ikinci çıkartmanın durumuna göre A'nın yeni durumunu atıyoruz
+    wire [31:0] A_ikinci_cikarma_sonrasi = ( ikinci_cikarmayi_yap ? ikinci_cikarma_sonucu[31:0] : A_ilk_cikarma_sonrasi );
+    
+    
+    always@ (*) begin
+        bitti_next = HAYIR;
+        hesaplaniyor_next = hesaplaniyor;
+        A_next = A;
+        B_next = B;
+        bolme_basamagi_next = bolme_basamagi;
+        sonuc_ver_next = sonuc_ver;
+        kalan_next = kalan;
+        bolum_next = bolum;
+        if (hesaplaniyor) begin
+            hesaplaniyor_next = ~bolme_basamagi[1];
+            sonuc_ver_next = bolme_basamagi[1]; // iki kaydıra kaydıra bitmeden bir önceki adımda olan bir
+            bitti_next = HAYIR;
+            A_next = A_ikinci_cikarma_sonrasi; // ilki hesaplanan çıkarma sonucunu alıyor
+            B_next = B >> 2; // ikinci sayıyı iki birim sağa kaydırıyoruz
+            bolme_basamagi_next = bolme_basamagi >> 2; // bölme basamağı da beraber sola kayıyor
+            case ( {ilk_cikarmayi_yap, ikinci_cikarmayi_yap} ) // çıkarma işlemini yapıp yapmamamıza göre o basamakları bölüme ekliyoruz
+                2'b00:
+                    bolum_next = bolum;
+                2'b01:
+                    bolum_next = bolum ^ ikinci_bolme_basamagi;
+                2'b10:
+                    bolum_next = bolum ^ bolme_basamagi;
+                2'b11:
+                    bolum_next = bolum ^ bolme_basamagi ^ ikinci_bolme_basamagi;
+            endcase
+        end
+        else if(sonuc_ver) begin // çıkartma işlemlerinden sonraki negatif hesaplama kısmı
+            hesaplaniyor_next = HAYIR;
+            sonuc_ver_next = HAYIR;
+            bitti_next = EVET;
+            if (divbyzero) begin
+                bolum_next = 32'hffffffff;
+                kalan_next = a_g;
+            end else if (overflow && isaretli) begin
+                bolum_next = 32'h80000000;
+                kalan_next = 32'h0;
+            end
+            else begin
+                bolum_next = sonuc_negatif_mi? -bolum: bolum;
+                kalan_next = A_negatif_mi? -A: A;
+            end
+        end
+        else if (istek) begin // yeni istek
+            hesaplaniyor_next = EVET;
+            sonuc_ver_next = HAYIR;
+            bitti_next = HAYIR;
+            A_next = ( A_negatif_mi ? -a_g : a_g ); // A'yı pozitif olarak al
+            B_next = ( B_negatif_mi ? {1'd0, -b_g, 31'd0} : {1'd0, b_g, 31'd0} ); // B 2^31 ile çarpılmış hali ile başlat
+            bolme_basamagi_next = BOLME_BASLANGIC; // bölme basamağını başlangıca sıfırla
+            kalan_next = 32'd0;
+            bolum_next = 32'd0;
+        end
+    end
+    
+    always@ (posedge clk) begin
+        if(rst_g) begin
+            A <= 0;
+            B <= 0;
+            kalan <= 0;
+            bolum <= 0;
+            bitti <= 0;
+            hesaplaniyor <= 0;
+            sonuc_ver <= 0;
+            bolme_basamagi <= 0;
+        end else begin
+            A <= A_next;
+            B <= B_next;
+            kalan <= kalan_next;
+            bolum <= bolum_next;
+            bitti <= bitti_next;
+            hesaplaniyor <= hesaplaniyor_next;
+            sonuc_ver <= sonuc_ver_next;
+            bolme_basamagi <= bolme_basamagi_next;
+        end
+    end
+    
+    
+    
+endmodule
diff --git a/verilog/rtl/iki_bit_adimli_carpici.v b/verilog/rtl/iki_bit_adimli_carpici.v
new file mode 100644
index 0000000..abd2596
--- /dev/null
+++ b/verilog/rtl/iki_bit_adimli_carpici.v
@@ -0,0 +1,114 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+
+module iki_bit_adimli_carpici(
+    input                   rst_g,
+    input       [31:0]      a_g,
+    input       [31:0]      b_g,
+    input                   istek,
+    input                   a_isaretli,
+    input                   b_isaretli,
+    input                   clk,
+    output      [63:0]      sonuc,
+    output      reg         bitti = 0
+    );
+    
+    /*
+        Çarpma her clock başı b'nin en küçük iki biti a ile çarpılarak çarpıma ekleniyor.
+        Sonraki adımda b'yi iki sağa kaydırıp a'yı iki sola kaydırarak yeni en küçük bitiyle olacak çarpımın asıl değerini koruyoruz.
+        Sayılar negatif veya pozitif olmasına bakılmaksızın pozitif olarak alınıyor.
+        Eğer sonuç negatif olması gerkiyorsa sonucu negatife çevirilmiş haliyle veriyor aksi halde normal kalıyor.
+        Örnek:
+            3   x   5   =   15
+            -2  x   -3  =   2   x   3   =   6
+            -2  x   4   = -(2   x   4)  =  -8
+    */
+    
+    localparam EVET = 1'b1;
+    localparam HAYIR = 1'b0;
+    
+    reg[63:0] A, A_next;
+    reg[31:0] B, B_next;
+    
+    reg[63:0] carpim, carpim_next;
+    
+    reg hesaplaniyor = HAYIR, hesaplaniyor_next;
+    
+    reg bitti_next = 0;
+    
+    
+    wire a_negatif_mi = a_isaretli & a_g[31];
+    wire b_negatif_mi = b_isaretli & b_g[31];
+    
+    wire sonuc_negatif_mi = a_negatif_mi ^ b_negatif_mi;
+    
+    // B'nin ilk biti ile A'nın çarpımı B'nin ilk bit 1 ise A'nın kendisi değilse sıfırdır
+    wire[63:0] ilk_bit_carpim = ( B[0] ? A : 64'd0 );
+    
+    // B'nin ikinci biti ile A'nın çarpımı B'nin ikinci biti 1 ise A'nın ikiyle çarpılmış/bir kaydırılmış halidir değilse 0
+    wire[63:0] ikinci_bit_carpim = ( B[1] ? {A[62:0], 1'd0} : 64'd0 );
+    
+    
+    reg[3:0] adim = 4'hf, adim_next = 4'h7; // sabit clock sayısı
+    
+    
+    always@ (*) begin
+        bitti_next = HAYIR;
+        hesaplaniyor_next = hesaplaniyor;
+        A_next = A;
+        B_next = B;
+        carpim_next = carpim;
+        adim_next = adim;
+        if (hesaplaniyor) begin
+            hesaplaniyor_next = |(adim);
+            bitti_next = (adim == 4'h0); // sabit clock sayısı // bitti_next = ~ (|B[31:2]) & ~bitti;
+            adim_next = adim - 1'b1; // sabit clock sayısı
+            A_next = A << 2;
+            B_next = B >> 2;
+            carpim_next = carpim + ilk_bit_carpim + ikinci_bit_carpim;
+        end
+        else if (istek) begin
+            hesaplaniyor_next = EVET;
+            A_next = ( a_negatif_mi ? {32'd0, -a_g} : {32'd0, a_g} ); // A 64 bit olduğu için yanına 0 ekliyoruz
+            B_next = ( b_negatif_mi ? -b_g : b_g );
+            carpim_next = 64'd0; // çarpımı sıfırla
+            bitti_next = HAYIR;
+            adim_next = 4'hf; // sabit clock sayısı
+        end
+    end
+    
+    always@ (posedge clk) begin
+        if(rst_g) begin
+            A <= 0;
+            B <= 0;
+            carpim <= 0;
+            bitti <= 0;
+            hesaplaniyor <= 0;;
+            adim <= 0;
+        end else begin
+            A <= A_next;
+            B <= B_next;
+            carpim <= carpim_next;
+            bitti <= bitti_next;
+            hesaplaniyor <= hesaplaniyor_next;;
+            adim <= adim_next; // sabit clock sayısı
+        end
+    end
+    
+    assign sonuc = ( sonuc_negatif_mi ? -carpim : carpim );
+    
+endmodule
diff --git a/verilog/rtl/mikroislem.vh b/verilog/rtl/mikroislem.vh
new file mode 100644
index 0000000..1d1c061
--- /dev/null
+++ b/verilog/rtl/mikroislem.vh
@@ -0,0 +1,161 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+///////////////////////////
+// Mikroislem sinyalleri//
+`define DDY_ADRES_BIT 12
+`define DDY_ADRES 185
+
+`define DDY_VERI_BIT 32
+`define DDY_VERI 153
+
+`define DDY_ANLIK_BIT 5
+`define DDY_ANLIK 148
+
+`define DDY_YAZ 147
+
+`define GECERLI 146
+
+`define YURUT_KODU_BIT 7
+`define YURUT_KODU 139
+`define YURUT_KODU_AMB 'h1
+`define YURUT_KODU_DB 'h2
+`define YURUT_KODU_BIB 'h4
+`define YURUT_KODU_TCB 'h8
+`define YURUT_KODU_TBB 'h10
+`define YURUT_KODU_CSR 'h20
+`define YURUT_KODU_SISTEM 'h40
+
+`define ISLEV_KODU_BIT 12
+`define ISLEV_KODU 127
+
+`define IS1_SEC_BIT 3
+`define IS1_SEC 124
+`define IS1_SEC_KY1 'h1
+`define IS1_SEC_PS 'h2
+`define IS1_SEC_0 'h4
+
+
+`define IS2_SEC_BIT 5
+`define IS2_SEC 119
+`define IS2_SEC_CSR_AD 'h10 // AD: Anlik deger
+`define IS2_SEC_0 'h8
+`define IS2_SEC_4 'h4
+`define IS2_SEC_AD 'h2
+`define IS2_SEC_KY2 'h1
+
+`define ANLIK_DEGER_BIT 32
+`define ANLIK_DEGER 87
+
+`define KY1_BIT 5
+`define KY1 82
+
+`define KY2_BIT 5
+`define KY2 77
+
+`define BELLEK_BUYRUGU_BIT 3
+`define BELLEK_BUYRUGU 74
+`define YUKLE_BUYRUGU 76
+`define KAYDET_BUYRUGU 75
+`define FENCE_BUYRUGU 74
+
+
+`define BELLEK_TURU_BIT 3
+`define BELLEK_TURU 71
+`define BELLEK_TURU_W 73
+`define BELLEK_TURU_HW 72
+`define BELLEK_TURU_B 71
+
+
+`define BELLEK_ISARETLI 70
+
+`define HY_YAZ 69
+
+`define HY_DEGER_BIT 32 
+`define HY_DEGER 37
+
+
+`define HY_BIT 5
+`define HY 32
+
+`define PS_BIT 32
+`define PS 0
+
+
+////////////////////////
+ // AMB islev kodlari//
+ `define ADD 'h1
+ `define SUB 'h2
+ `define AND 'h4
+ `define OR 'h8
+ `define XOR 'h10
+ `define SLT 'h20
+ `define SLTU 'h40
+ `define SLL 'h80
+ `define SRL 'h100
+ `define SRA 'h200
+ `define LUI 'h400
+ `define AUIPC 'h800
+////////////////////////
+ // DB islev kodlari //
+ `define JAL  'h1
+ `define JALR 'h2
+ `define BEQ  'h4
+ `define BNE  'h8
+ `define BLT  'h10
+ `define BLTU 'h20
+ `define BGE  'h40
+ `define BGEU 'h80
+/////////////////////////
+ // BIB islev kodlari //
+ `define LW    'h1 
+ `define LH    'h2 
+ `define LHU   'h4 
+ `define LB    'h8 
+ `define LBU   'h10
+ `define SW    'h20
+ `define SH    'h40
+ `define SB    'h80
+ `define FENCE 'h100
+ /////////////////////////////
+ // Bellk Buyrugu tanimlamalari//
+ `define FENCE_b 'h1
+ `define KAYDET_b 'h2
+ `define YUKLE_b 'h4
+ ///////////////////////////////
+//////////////////////////////
+ // CSR islev kodlari //
+ `define ECALL  'h1
+ `define EBREAK 'h2
+ `define URET   'h4
+ `define MRET   'h8
+ `define CSRRW  'h10
+ `define CSRRS  'h20
+ `define CSRRC  'h40 
+ `define CSRRWI  'h80
+ `define CSRRSI  'h100
+ `define CSRRCI  'h200
+/////////////////////////
+ // TCB islev kodlari //
+ `define MUL 'h1
+ `define MULH 'h2
+ `define MULHU 'h4
+ `define MULHSU 'h8
+/////////////////////////
+ // TBB islev kodlari //
+ `define DIV 'h1
+ `define DIVU 'h2
+ `define REM 'h4
+ `define REMU 'h8
+
diff --git a/verilog/rtl/on_taraf.v b/verilog/rtl/on_taraf.v
new file mode 100644
index 0000000..42bc1b9
--- /dev/null
+++ b/verilog/rtl/on_taraf.v
@@ -0,0 +1,126 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+//==============================================================================
+// On taraf buyruk bellegi ile C0 arasindaki haberlesmeyi denetler
+//==============================================================================
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`endif
+
+module on_taraf(
+
+    input                                                       clk_g                                                                                 ,
+    input                                                       rst_g                                                                                 ,
+    
+    // TODO buraya buyruk adresi gelecek
+    
+    
+    //      On_taraf <-> GC
+    input                                                       gc_hazir_g                                                                            ,
+    output                                                      bb_buy_gecerli_c                                                                      ,
+    output              [`BUYRUK_BIT-1:0]                       bb_buy_c                                                                              ,
+    output              [`BB_ADRES_BIT-1:0]                     bb_buy_ps_c                                                                           ,
+    input               [`BB_ADRES_BIT-1:0]                     bb_buy_istek_adres_g                                                                  ,
+    input                                                       bb_buy_istek_g                                                                        ,
+    
+    //      On_taraf <-> Buyruk Bellegi
+    output              [`BB_ADRES_BIT-1:0]                     bb_addra_c                                                                            ,                                       
+    input               [31:0]                                  bb_douta_g                                                                            ,                                      
+    output                                                      bb_ena_c                                                                              ,   
+    
+    //      On_taraf <-> Baslangic Bellegi
+    output              [`BB_ADRES_BIT-1:0]                     basbel_addra_c                                                                        ,                                       
+    input               [31:0]                                  basbel_douta_g                                                                        ,
+    output    reg                                               basbel_ena_c                      
+   
+    );
+    
+    reg                                                         gc_hazir_degildi_r                                                                    ;
+    reg                                                         gc_hazir_degildi_ns_r                                                                 ;
+    
+    wire                [`BB_ADRES_BIT-1:0]                     baslangic_adresi_w                  =           `BASLANGIC_ADRESI                     ;
+        
+    reg                 [`BB_ADRES_BIT-1:0]                     program_sayaci_r                                                                      ;                                                    
+    reg                 [`BB_ADRES_BIT-1:0]                     program_sayaci_ns_r                                                                   ;
+    
+    reg                                                         buyruk_gecerli_r                                                                      ;
+    reg                                                         buyruk_gecerli_ns_r                                                                   ;
+    
+    reg                 [31:0]                                  buyruk_r                                                                              ;
+    reg                 [31:0]                                  buyruk_ns_r                                                                           ;
+    
+    // TODO: bb_ena_c, baslangic bellegi de okunsa 1 oluyor, cok onemli olmamasi lazim
+    wire                                                        basbel_oku_w                        =           program_sayaci_r < `BB_TABAN_ADR      ;
+    assign                                                      bb_ena_c                            =           basbel_oku_w ? `LOW: basbel_ena_c;
+    
+    assign                                                      bb_buy_c                            =           basbel_oku_w                          ? 
+                                                                                                                  basbel_douta_g                      : 
+                                                                                                                  (gc_hazir_degildi_r)                ?
+                                                                                                                  buyruk_r : bb_douta_g               ;
+                                                                                                                  
+    assign                                                      bb_buy_ps_c                         =           program_sayaci_r    -   3'b100        ;
+    assign                                                      bb_buy_gecerli_c                    =           buyruk_gecerli_r                      ;
+    assign                                                      bb_addra_c                          =           program_sayaci_r - `BB_TABAN_ADR      ;
+    
+    assign                                                      basbel_addra_c                      =           program_sayaci_r - `BASBEL_TABAN_ADR  ;
+    
+    // TODO: iki portlu bram farkli calisiyor, ona gore kodu duzenle
+    // ena 1 olmayinca Z baglaniyor
+    
+    always @* begin
+        program_sayaci_ns_r                     =               program_sayaci_r                                                                      ;
+        buyruk_gecerli_ns_r                     =               buyruk_gecerli_r                                                                      ;
+        basbel_ena_c                            =               `LOW                                                                                  ;
+        buyruk_ns_r                             =               buyruk_r                                                                              ;
+        gc_hazir_degildi_ns_r                   =               !gc_hazir_g                                                                           ;
+        
+        if (!gc_hazir_degildi_r && (!gc_hazir_g)) // hazirdi, artik hazir degil
+            buyruk_ns_r                         =               bb_douta_g                                                                            ; 
+        
+        if (gc_hazir_g) 
+        begin
+            //buyruk_ns_r                         =               bb_douta_g                                                                            ;
+            basbel_ena_c                        =               `HIGH                                                                                 ;
+            buyruk_gecerli_ns_r                 =               `HIGH                                                                                 ;          
+            program_sayaci_ns_r                 =               program_sayaci_r                    +           3'b100                                ;
+            if (bb_buy_istek_g) 
+            begin
+                program_sayaci_ns_r             =               bb_buy_istek_adres_g                                                                  ;
+                buyruk_gecerli_ns_r             =               `LOW                                                                                  ;
+            end
+        end
+    end
+    
+    always @(posedge clk_g) begin
+        if (rst_g)
+        begin
+            program_sayaci_r                    <=              baslangic_adresi_w                                                                    ;
+            buyruk_gecerli_r                    <=              `LOW                                                                                  ;
+            buyruk_r                            <=              32'b0                                                                                 ;
+            gc_hazir_degildi_r                  <=              `LOW                                                                                  ;                   
+        end
+        else
+        begin
+            program_sayaci_r                    <=              program_sayaci_ns_r                                                                   ;
+            buyruk_gecerli_r                    <=              buyruk_gecerli_ns_r                                                                   ;
+            buyruk_r                            <=              buyruk_ns_r                                                                           ;
+            gc_hazir_degildi_r                  <=              gc_hazir_degildi_ns_r                                                                 ;
+        end    
+    end                                                                
+    
+endmodule
diff --git a/verilog/rtl/sabitler.vh b/verilog/rtl/sabitler.vh
new file mode 100644
index 0000000..3cd8027
--- /dev/null
+++ b/verilog/rtl/sabitler.vh
@@ -0,0 +1,99 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+//-----------Sim Parametreleri----
+`define FAST_UART
+//`define SIM_SRAM
+`define GL_RTL_SIM
+//------Sentez Parametreleri------
+//`define VCU108
+//`define BASYS3
+//-----------Diger----------------
+`define BASLANGIC_ADRESI 32'h0
+`define BASBEL_TABAN_ADR 32'h0 // baslangic bellegi (bootrom) taban adresi
+`define BB_TABAN_ADR 32'h1_0000 // buyruk bellegi baslangic adresi
+`define VB_TABAN_ADR 32'h4000_0000 // veri bellegi baslangic adresi
+
+`define HIGH 1
+`define LOW  0
+
+`define VERI_BIT  32
+//-----------Bellek---------------
+`define ADRES_BIT 32
+
+//-----------Mikroislem-----------
+`define UIS_BIT 197
+
+//-----------GetirCoz-------------
+`define BB_ADRES_BIT 32
+`define BUYRUK_BIT 32
+
+`define BUY_ISKODU 0
+`define BUY_ISKODU_BIT 7
+`define BUY_HY 7
+`define BUY_HY_BIT 5
+`define BUY_KY1 15
+`define BUY_KY1_BIT 5
+`define BUY_KY2 20
+`define BUY_KY2_BIT 5
+`define BUY_F7 25
+`define BUY_F7_BIT 7
+`define BUY_F3 12
+`define BUY_F3_BIT 3
+
+`define I_ANLIK 20
+`define I_ANLIK_BIT 12
+`define I_ANLIK_ISARET 31
+
+`define U_ANLIK 12
+`define U_ANLIK_BIT 20
+
+`define ODD_BIT 5
+
+//-------------DDY---------------
+
+// Kural disi durum kodlari
+`define KDD_HBA   32'd0   // hizasiz buyruk adresi
+`define KDD_YB    32'd2   // yanlis buyruk
+`define KDD_HYA   32'd4   // hizasiz yukle buyrugu
+`define KDD_HKA   32'd6   // hizasiz kaydet buyrugu
+`define KDD_MRET  32'd11  // makine modundan ortam cagrisi
+
+// Priv. mode degerleri
+`define PRIV_USER         2'd0
+`define PRIV_SUPER        2'd1
+`define PRIV_MACHINE      2'd3
+
+// Yazmac adresleri
+// TODO, bunlar uyumlu mu?
+`define DDY_MSTATUS       12'h300
+`define DDY_MISA          12'h301
+`define DDY_MEDELEG       12'h302
+`define DDY_MIDELEG       12'h303
+`define DDY_MIE           12'h304
+`define DDY_MTVEC         12'h305
+`define DDY_MSCRATCH      12'h340
+`define DDY_MEPC          12'h341
+`define DDY_MCAUSE        12'h342
+`define DDY_MTVAL         12'h343
+`define DDY_MIP           12'h344
+`define DDY_MCYCLE        12'hc00
+`define DDY_MTIME         12'hc01
+`define DDY_MTIMEH        12'hc81
+`define DDY_MHARTID       12'hF14
+
+// MSTATUS yazmac offsetleri
+`define MSTATUS_MIE       3       
+`define MSTATUS_MPIE      7 
+`define MSTATUS_MPP       11
\ No newline at end of file
diff --git a/verilog/rtl/tamsayi_bolme_birimi.v b/verilog/rtl/tamsayi_bolme_birimi.v
new file mode 100644
index 0000000..08b6c8a
--- /dev/null
+++ b/verilog/rtl/tamsayi_bolme_birimi.v
@@ -0,0 +1,98 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+
+module tamsayi_bolme_birimi(
+    input                 clk_g                                                         ,
+    input                 rst_g                                                         ,
+    input        [3:0]    islev_kodu_g                                                  ,
+    input        [31:0]   islec1_g                                                      ,
+    input        [31:0]   islec2_g                                                      ,
+    input                 hazir_g                                                     ,
+    output                bitti_c                                                       ,
+    output       [31:0]   sonuc_c
+    );
+    
+    
+    localparam DIV  = 4'h1; 
+    localparam DIVU = 4'h2; 
+    localparam REM  = 4'h4; 
+    localparam REMU = 4'h8; 
+    
+    reg basla, basla_next;
+
+    reg [3:0] islev_kodu_r, islev_kodu_ns_r;
+    reg [31:0] A, A_next, B, B_next;
+        
+    // DIV ve REM işlemleri işin işaretli gibi yap diğerleri için işaretsiz
+    wire isaretli = ( islev_kodu_r == DIV | islev_kodu_r == REM );
+    wire overflow = ((A == 32'h80000000) && (B == 32'hffffffff));
+    wire divbyzero = (B == 32'd0);
+    
+    // bölme ünitesi bölüm ve kalan/mod'u döndürüyor
+    wire [31:0] bolum;
+    wire [31:0] kalan;
+    
+    // işlemin bittiği clocku vermek için
+    wire bitti;
+    
+    iki_bit_adimli_bolucu bolme_birimi (
+        .rst_g(rst_g),
+        .a_g(A),
+        .b_g(B),
+        .istek(basla),
+        .isaretli(isaretli),
+        .overflow(overflow),
+        .divbyzero(divbyzero),
+        .clk(clk_g),
+        .bolum(bolum),
+        .kalan(kalan),
+        .bitti(bitti)
+    );
+    
+    always @* begin
+        islev_kodu_ns_r = (hazir_g)? islev_kodu_g: islev_kodu_r;
+        A_next = (hazir_g)? islec1_g: A;
+        B_next = (hazir_g)? islec2_g: B;
+        basla_next = hazir_g;
+    end
+    
+    always @(posedge clk_g) begin
+        if(rst_g) begin 
+            islev_kodu_r <= 0;
+            A <= 0;
+            B <= 0;
+            basla <= 0;
+        end else begin
+            islev_kodu_r <= islev_kodu_ns_r;
+            A <= A_next;
+            B <= B_next;
+            basla <= basla_next;
+        end
+    end
+    
+    // doğrudan bölme biriminin verdiği değeri atıyoruz
+    assign bitti_c = bitti;
+    
+    // DIV ve DIVU için bölümü diğerleri için kalanı veriyoruz
+    assign sonuc_c = ( islev_kodu_r == DIV | islev_kodu_r == DIVU ) ? bolum : kalan;
+    
+    
+    
+    
+    
+    
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/tamsayi_carpma_birimi.v b/verilog/rtl/tamsayi_carpma_birimi.v
new file mode 100644
index 0000000..fc37fed
--- /dev/null
+++ b/verilog/rtl/tamsayi_carpma_birimi.v
@@ -0,0 +1,90 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+
+module tamsayi_carpma_birimi(
+    input                 clk_g                                                         ,
+    input                 rst_g                                                         ,
+    input        [3:0]    islev_kodu_g                                                  ,
+    input        [31:0]   islec1_g                                                      ,
+    input        [31:0]   islec2_g                                                      ,
+    input                 hazir_g                                                     ,
+    output                bitti_c                                                       ,
+    output       [31:0]   sonuc_c
+    );
+    
+    localparam MUL      = 4'h1; 
+    localparam MULH     = 4'h2; 
+    localparam MULHU    = 4'h4;
+    localparam MULHSU   = 4'h8; 
+    
+    reg basla, basla_next;
+    reg [3:0] islev_kodu_r, islev_kodu_ns_r;
+    reg [31:0] A, A_next, B, B_next;
+    // MUL ve MULH işin işlemleri işaretli gibi yap diğerleri için işaretsiz
+    wire a_isaretli = ( islev_kodu_r == MUL | islev_kodu_r == MULH | islev_kodu_r == MULHSU);
+    wire b_isaretli = ( islev_kodu_r == MUL | islev_kodu_r == MULH );
+
+    // çarpma ünitesi sonucu 64 bit olarak döndürüyor
+    wire [63:0] carpim;
+    
+    // işlemin bittiği clocku vermek için
+    wire bitti;
+    
+    iki_bit_adimli_carpici carpma_birimi (
+        .a_g(A),
+        .b_g(B),
+        .istek(basla),
+        .a_isaretli(a_isaretli),
+        .b_isaretli(b_isaretli),
+        .clk(clk_g),
+        .sonuc(carpim),
+        .bitti(bitti)
+    );
+    
+    always @* begin
+        islev_kodu_ns_r = (hazir_g)? islev_kodu_g: islev_kodu_r;
+        A_next = (hazir_g)? islec1_g: A;
+        B_next = (hazir_g)? islec2_g: B;
+        basla_next = hazir_g;
+    
+    end
+    
+    
+    always @(posedge clk_g) begin
+        if(rst_g) begin 
+            islev_kodu_r <= 0;
+            A <= 0;
+            B <= 0;
+            basla <= 0;
+        end else begin
+            islev_kodu_r <= islev_kodu_ns_r;
+            A <= A_next;
+            B <= B_next;
+            basla <= basla_next;
+        end
+    end
+    
+    // doğrudan çarpma biriminin verdiği değeri atıyoruz
+    assign bitti_c = bitti;
+    
+    // MUL ve MULU için çarpımın ilk 32 basamağını yolla diğerleri için son 32 basamağı
+    assign sonuc_c = (islev_kodu_r == MUL) ? carpim[31:0] : carpim[63:32];
+    
+    
+    
+endmodule
+
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
deleted file mode 100644
index 3537de8..0000000
--- a/verilog/rtl/uprj_netlists.v
+++ /dev/null
@@ -1,28 +0,0 @@
-// SPDX-FileCopyrightText: 2020 Efabless Corporation
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//      http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-// SPDX-License-Identifier: Apache-2.0
-
-// Include caravel global defines for the number of the user project IO pads 
-`include "defines.v"
-`define USE_POWER_PINS
-
-`ifdef GL
-    // Assume default net type to be wire because GL netlists don't have the wire definitions
-    `default_nettype wire
-    `include "gl/user_project_wrapper.v"
-    `include "gl/user_proj_example.v"
-`else
-    `include "user_project_wrapper.v"
-    `include "user_proj_example.v"
-`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 26081e9..e1829b1 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -66,7 +66,29 @@
     output [`MPRJ_IO_PADS-1:0] io_oeb,
 
     // IRQ
-    output [2:0] irq
+    output [2:0] irq,
+
+    output                                          vb_csb0                 ,
+    output                                          vb_web0                 ,
+    output          [3:0]                           vb_wmask0               ,
+    output          [12:0]                          vb_addr0                ,
+    output          [31:0]                          vb_din0                 ,
+    input           [31:0]                          vb_dout0                ,
+
+    output                                          vb_csb1                 ,
+    output          [12:0]                          vb_addr1                ,
+    input           [31:0]                          vb_dout1                ,
+
+    output                                          bb_csb0                 ,
+    output                                          bb_web0                 ,
+    output          [3:0]                           bb_wmask0               ,
+    output          [31:0]                          bb_addr0                ,
+    output          [31:0]                          bb_din0                 ,
+    input           [31:0]                          bb_dout0                ,
+
+    output                                          bb_csb1                 ,
+    output          [31:0]                          bb_addr1                ,
+    input           [31:0]                          bb_dout1                         
 );
     wire clk;
     wire rst;
@@ -104,11 +126,9 @@
     assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
     assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
 
-    counter #(
-        .BITS(BITS)
-    ) counter(
-        .clk(clk),
-        .reset(rst),
+    c0_system c0_system(
+        .clk_g(clk),
+        .rst_g(rst),
         .ready(wbs_ack_o),
         .valid(valid),
         .rdata(rdata),
@@ -116,50 +136,34 @@
         .wstrb(wstrb),
         .la_write(la_write),
         .la_input(la_data_in[63:32]),
-        .count(count)
+        .count(count),
+        .tx(tx),
+        .rx(rx),
+        .io_gecerli(io_gecerli),
+        .io_ps(io_ps),
+        
+        .bb_csb0                                           (bb_csb0)                                                       ,
+        .bb_web0                                           (bb_web0)                                                       ,
+        .bb_wmask0                                         (bb_wmask0)                                                     ,
+        .bb_addr0                                          (bb_addr0)                                                      ,
+        .bb_din0                                           (bb_din0)                                                       ,
+        .bb_dout0                                          (bb_dout0)                                                      ,
+
+        .bb_csb1                                           (bb_csb1)                                                       ,
+        .bb_addr1                                          (bb_addr1)                                                      ,
+        .bb_dout1                                          (bb_dout1)                                                      ,
+
+        .vb_csb0                                           (vb_csb0)                                                       ,
+        .vb_web0                                           (vb_web0)                                                       ,
+        .vb_wmask0                                         (vb_wmask0)                                                     ,
+        .vb_addr0                                          (vb_addr0)                                                      ,
+        .vb_din0                                           (vb_din0)                                                       ,
+        .vb_dout0                                          (vb_dout0)                                                      ,
+
+        .vb_csb1                                           (vb_csb1)                                                       ,
+        .vb_addr1                                          (vb_addr1)                                                      ,
+        .vb_dout1                                          (vb_dout1) 
     );
 
 endmodule
-
-module counter #(
-    parameter BITS = 32
-)(
-    input clk,
-    input reset,
-    input valid,
-    input [3:0] wstrb,
-    input [BITS-1:0] wdata,
-    input [BITS-1:0] la_write,
-    input [BITS-1:0] la_input,
-    output ready,
-    output [BITS-1:0] rdata,
-    output [BITS-1:0] count
-);
-    reg ready;
-    reg [BITS-1:0] count;
-    reg [BITS-1:0] rdata;
-
-    always @(posedge clk) begin
-        if (reset) begin
-            count <= 0;
-            ready <= 0;
-        end else begin
-            ready <= 1'b0;
-            if (~|la_write) begin
-                count <= count + 1;
-            end
-            if (valid && !ready) begin
-                ready <= 1'b1;
-                rdata <= count;
-                if (wstrb[0]) count[7:0]   <= wdata[7:0];
-                if (wstrb[1]) count[15:8]  <= wdata[15:8];
-                if (wstrb[2]) count[23:16] <= wdata[23:16];
-                if (wstrb[3]) count[31:24] <= wdata[31:24];
-            end else if (|la_write) begin
-                count <= la_write & la_input;
-            end
-        end
-    end
-
-endmodule
 `default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5ee1cee..e2aa7df 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -81,43 +81,108 @@
 /*--------------------------------------*/
 /* User project is instantiated  here   */
 /*--------------------------------------*/
+wire                                         vb_clk0                 ;
+wire                                         vb_csb0                 ;
+wire                                         vb_web0                 ;
+wire         [3:0]                           vb_wmask0               ;
+wire         [12:0]                          vb_addr0                ;
+wire         [31:0]                          vb_din0                 ;
+wire         [31:0]                          vb_dout0                ;
+wire                                         vb_clk1                 ;
+wire                                         vb_csb1                 ;
+wire         [12:0]                          vb_addr1                ;
+wire         [31:0]                          vb_dout1                ;
+wire                                         bb_clk0                 ;
+wire                                         bb_csb0                 ;
+wire                                         bb_web0                 ;
+wire         [3:0]                           bb_wmask0               ;
+wire         [`BB_ADRES_BIT-1:0]             bb_addr0                ;
+wire         [31:0]                          bb_din0                 ;
+wire         [31:0]                          bb_dout0                ;
+wire                                         bb_clk1                 ;
+wire                                         bb_csb1                 ;
+wire         [`BB_ADRES_BIT-1:0]             bb_addr1                ;
+wire         [31:0]                          bb_dout1                ;    
 
-user_proj_example mprj (
+c0_system mprj (
 `ifdef USE_POWER_PINS
 	.vccd1(vccd1),	// User area 1 1.8V power
 	.vssd1(vssd1),	// User area 1 digital ground
 `endif
 
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
-
-    // MGMT SoC Wishbone Slave
-
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o),
-
-    // Logic Analyzer
-
-    .la_data_in(la_data_in),
-    .la_data_out(la_data_out),
-    .la_oenb (la_oenb),
+    .clk_g(wb_clk_i),
+    .rst_g(wb_rst_i),
 
     // IO Pads
-
-    .io_in (io_in),
-    .io_out(io_out),
+    .tx(io_out[1]),
+    .rx(io_in[0]),
+    .io_gecerli(io_out[2]),
+    .io_ps(io_out[34:3]),
     .io_oeb(io_oeb),
 
-    // IRQ
-    .irq(user_irq)
+
+    .bb_csb0                                           (bb_csb0)                                                       ,
+    .bb_web0                                           (bb_web0)                                                       ,
+    .bb_wmask0                                         (bb_wmask0)                                                     ,
+    .bb_addr0                                          (bb_addr0)                                                      ,
+    .bb_din0                                           (bb_din0)                                                       ,
+    .bb_dout0                                          (bb_dout0)                                                      ,
+
+    .bb_csb1                                           (bb_csb1)                                                       ,
+    .bb_addr1                                          (bb_addr1)                                                      ,
+    .bb_dout1                                          (bb_dout1)                                                      ,
+
+    .vb_csb0                                           (vb_csb0)                                                       ,
+    .vb_web0                                           (vb_web0)                                                       ,
+    .vb_wmask0                                         (vb_wmask0)                                                     ,
+    .vb_addr0                                          (vb_addr0)                                                      ,
+    .vb_din0                                           (vb_din0)                                                       ,
+    .vb_dout0                                          (vb_dout0)                                                      ,
+
+    .vb_csb1                                           (vb_csb1)                                                       ,
+    .vb_addr1                                          (vb_addr1)                                                      ,
+    .vb_dout1                                          (vb_dout1) 
 );
 
+sky130_sram_2kbyte_1rw1r_32x512_8 VB_SRAM
+(
+    `ifdef USE_POWER_PINS
+        .vccd1(vccd1),
+        .vssd1(vssd1),
+    `endif        
+
+    .clk0               (wb_clk_i)        ,
+    .csb0               (vb_csb0)        ,
+    .web0               (vb_web0)        ,
+    .wmask0             (vb_wmask0)      ,
+    .addr0              (vb_addr0)       ,
+    .din0               (vb_din0)        ,
+    .dout0              (vb_dout0)       ,
+    .clk1               (wb_clk_i)        ,
+    .csb1               (vb_csb1)        ,
+    .addr1              (vb_addr1)       ,
+    .dout1              (vb_dout1)     
+);
+
+sky130_sram_2kbyte_1rw1r_32x512_8 BB_SRAM
+(
+    `ifdef USE_POWER_PINS
+        .vccd1(vccd1),
+        .vssd1(vssd1),
+    `endif        
+
+    .clk0               (wb_clk_i)      ,
+    .csb0               (bb_csb0)      ,
+    .web0               (bb_web0)      ,
+    .wmask0             (bb_wmask0)    ,
+    .addr0              (bb_addr0)     ,
+    .din0               (bb_din0)      ,
+    .dout0              (bb_dout0)     ,
+    .clk1               (wb_clk_i)      ,
+    .csb1               (bb_csb1)      ,
+    .addr1              (bb_addr1)     ,
+    .dout1              (bb_dout1)   
+);
 endmodule	// user_project_wrapper
 
 `default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper_org.v b/verilog/rtl/user_project_wrapper_org.v
new file mode 100644
index 0000000..5ee1cee
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper_org.v
@@ -0,0 +1,123 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper.  The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+    parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated  here   */
+/*--------------------------------------*/
+
+user_proj_example mprj (
+`ifdef USE_POWER_PINS
+	.vccd1(vccd1),	// User area 1 1.8V power
+	.vssd1(vssd1),	// User area 1 digital ground
+`endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+
+    .io_in (io_in),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+
+    // IRQ
+    .irq(user_irq)
+);
+
+endmodule	// user_project_wrapper
+
+`default_nettype wire
diff --git a/verilog/rtl/veri_bellegi_sram.v b/verilog/rtl/veri_bellegi_sram.v
new file mode 100644
index 0000000..221d821
--- /dev/null
+++ b/verilog/rtl/veri_bellegi_sram.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+
+// Tek RW portlu SRAM bellegi modeller
+
+module veri_bellegi_sram
+(
+    input           [12:0]                          addra                   ,
+    input                                           clka                    ,
+    input           [31:0]                          dina                    ,
+    input                                           ena                     ,
+    input           [3:0]                           wea                     ,
+
+    output          [31:0]                          douta                   ,
+
+   // To SRAM outside c0's macro
+    output                                          csb0                    ,
+    output                                          web0                    ,
+    output          [3:0]                           wmask0                  ,
+    output          [12:0]                          addr0                   ,
+    output          [31:0]                          din0                    ,
+    input           [31:0]                          dout0                   ,
+
+    output                                          csb1                    ,
+    output          [12:0]                          addr1                   ,
+    input           [31:0]                          dout1                         
+
+);
+
+    assign      csb0        =           ~(ena&(|wea))       ;
+    assign      web0        =           ~(|wea)             ;
+    assign      wmask0      =           wea                 ;
+    
+    assign      addr0       =           addra               ;
+    assign      din0        =           dina                ;
+    //assign      dout0       =           32'b0           ;
+
+    assign      csb1        =           ~(ena&(~(|wea)))    ;
+    assign      addr1       =           addra               ;
+    assign      douta       =           dout1               ;
+
+endmodule
diff --git a/verilog/rtl/yazmac_obegi.v b/verilog/rtl/yazmac_obegi.v
new file mode 100644
index 0000000..3f0c6b9
--- /dev/null
+++ b/verilog/rtl/yazmac_obegi.v
@@ -0,0 +1,54 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+module yazmac_obegi(
+    `ifdef BASYS3
+    output        [15:0]            fpga_demo_signal            ,
+    `endif
+
+    input                           clk_g                       ,
+    input                           rst_g                       ,
+    input         [`HY_BIT-1:0]     ky1_adres_g                 ,
+    input         [`HY_BIT-1:0]     ky2_adres_g                 ,
+    input         [`HY_BIT-1:0]     hy_adres_g                  ,
+    input         [31:0]            hy_deger_g                  ,
+    input                           yaz_g                       ,
+    output reg    [31:0]            ky1_deger_c                 ,
+    output reg    [31:0]            ky2_deger_c
+    );
+    
+    reg           [31:0]    y_obek[31:0]                        ;
+    
+    `ifdef BASYS3
+    // FPGA DEMO for RISCV tests
+    assign fpga_demo_signal = {y_obek[10][7:0], y_obek[17][7:0]};
+    `endif
+
+    always@* begin
+        ky1_deger_c            = y_obek[ky1_adres_g]            ;
+        ky2_deger_c            = y_obek[ky2_adres_g]            ;
+    end
+    integer i = 0;
+    always@(posedge clk_g) begin
+        if (rst_g) begin
+            for(i = 0; i < 32; i = i + 1)
+                y_obek[i]           <=  0                           ;
+        end
+        else if(yaz_g) begin
+            y_obek[hy_adres_g]  <=  hy_deger_g                  ;
+        end
+    end
+endmodule
diff --git a/verilog/rtl/yazmac_oku_yurut.v b/verilog/rtl/yazmac_oku_yurut.v
new file mode 100644
index 0000000..3f9da65
--- /dev/null
+++ b/verilog/rtl/yazmac_oku_yurut.v
@@ -0,0 +1,487 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+////////////////////////////////////////////////////////////////////////////////////////
+//**************TODO:**********************
+//+Testbench yazimi
+//+MRET???
+////////////////////////////////////////////////////////////////////////////////////////
+
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`include "mikroislem.vh"
+`endif
+
+module yazmac_oku_yurut
+    (
+    input                               clk_g                                                            ,
+    input                               rst_g                                                            ,
+    input        [`UIS_BIT - 1:0]       gc_uis_g                                                         ,  
+    input        [31:0]                 oku_veri_g                                                       ,
+    input                               oku_veri_gecerli_g                                               ,
+    
+    input        [31:0]                 yo_ky1_veri_g                                                    ,
+    input        [31:0]                 yo_ky2_veri_g                                                    ,
+    input        [31:0]                 ddy_oku_veri_g                                                   ,
+    input                               bellek_hazir_g                                                   ,
+
+
+    output       [`UIS_BIT - 1:0]       yoy_uis_c                                                        , 
+    output                              oku_gecerli_c                                                    ,
+    output reg                          gc_duraklat_c                                                    ,
+    output reg   [31:0]                 siradaki_ps_c                                                    ,
+    output reg   [`ODD_BIT-1:0]         yoy_odd_kod_c                                                    , 
+    output reg                          yoy_odd_c                                                        ,
+    output reg   [31:0]                 yoy_odd_ps_c                                                     ,
+    output reg   [31:0]                 yoy_odd_adres_c                                                  ,
+    output reg                          gc_bosalt_c                                                      ,
+    output       [31:0]                 yaz_veri_c                                                       ,
+    output       [3:0]                  yaz_veri_maske_c                                                 ,
+    output                              yaz_gecerli_c                                                    ,
+    output       [31:0]                 adres_c                                                          , 
+    output reg   [4:0]                  yo_ky1_adres_c                                                   ,
+    output reg   [4:0]                  yo_ky2_adres_c                                                   ,                                  
+    output                              ddy_oku_gecerli_c                                                ,
+    output       [11:0]                 ddy_oku_adres_c                                              
+
+    );
+
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    ////*************************************uis ayirma***********************************************////
+    wire                                     gecerli_w         = gc_uis_g[`GECERLI]                      ;
+    wire         [`YURUT_KODU_BIT - 1: 0]    yurut_kodu_w      = gc_uis_g[`YURUT_KODU+:`YURUT_KODU_BIT]  ;
+    wire         [`ISLEV_KODU_BIT - 1: 0]    islev_kodu_w      = gc_uis_g[`ISLEV_KODU+:`ISLEV_KODU_BIT]  ;
+    wire         [`IS1_SEC_BIT - 1: 0]       is1_sec           = gc_uis_g[`IS1_SEC+:`IS1_SEC_BIT]        ;
+    wire         [`IS2_SEC_BIT - 1: 0]       is2_sec           = gc_uis_g[`IS2_SEC+:`IS2_SEC_BIT]        ;
+    wire         [`ANLIK_DEGER_BIT - 1: 0]   anlik_deger_w     = gc_uis_g[`ANLIK_DEGER+:`ANLIK_DEGER_BIT];
+    wire         [`KY1_BIT - 1: 0]           ky1_w             = gc_uis_g[`KY1+:`KY1_BIT]                ;
+    wire         [`KY2_BIT - 1: 0]           ky2_w             = gc_uis_g[`KY2+:`KY2_BIT]                ;
+    wire         [`BELLEK_BUYRUGU_BIT - 1: 0] bellek_buyrugu   = {gc_uis_g[`YUKLE_BUYRUGU],
+                                                                  gc_uis_g[`KAYDET_BUYRUGU],
+                                                                  gc_uis_g[`FENCE_BUYRUGU]};
+    wire         [`BELLEK_TURU_BIT - 1: 0]   bellek_turu       = {gc_uis_g[`BELLEK_TURU_W],
+                                                                  gc_uis_g[`BELLEK_TURU_HW],
+                                                                  gc_uis_g[`BELLEK_TURU_B]};
+    wire                                     bellek_isaretli_w = gc_uis_g[`BELLEK_ISARETLI]              ;
+    wire         [`HY_BIT - 1: 0]            hy_w              = gc_uis_g[`HY+:`HY_BIT]                  ;
+    wire         [`PS_BIT - 1: 0]            ps_w              = gc_uis_g[`PS+:`PS_BIT]                  ;
+    wire         [`DDY_ADRES_BIT - 1: 0]     ddy_adres_w       = gc_uis_g[`DDY_ADRES+:`DDY_ADRES_BIT]    ;
+    wire         [`DDY_ANLIK_BIT - 1: 0]     ddy_anlik_w       = gc_uis_g[`DDY_ANLIK+:`DDY_ANLIK_BIT]    ;
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    ////***********************************uis birlestirme********************************************////
+
+    reg          [`UIS_BIT - 1: 0]           yoy_uis_r                                                   ;
+    reg          [`UIS_BIT - 1: 0]           yoy_uis_sonraki_r                                           ;
+    
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    ////********************************Degisken tanimlamalari****************************************////
+    //Islec1 ve Islec2 icin yazmac tanimlamalari
+    reg          [31:0]                      is1_sec_r      =0                                             ; 
+    reg          [31:0]                      is2_sec_r      =0                                             ;
+ 
+    //YOY asamasinda guncellenecek uop bitleri icin yazmac tanimlamalari
+    //Hedef yazmacina yazma yapilacagi durumda -> 1, d.d. -> 0
+    reg                                      yazmac_yaz_r    =0                                             ;     
+    //Islem sonucunun yazilacagi yazmac
+    reg          [31:0]                      hy_deger_r      =0                                            ; 
+    // DDBye yazma yapilacagi durumda 1 
+    reg                                      ddy_yaz_r       =0                                            ;
+    reg                                      ddy_oku_r       =0                                            ;
+    reg          [31:0]                      ddy_yaz_veri_r  =0                                            ;
+
+                                   
+                                                     
+    //Cagirilan moduller icin degisken tanimlamalari
+    //AMB'de yapilan islemin sonucu
+    wire         [31:0]                      amb_sonuc_w                                                 ; 
+    // JAL ve JALR buyruklari icin hedef yazmaci degeri
+    wire         [31:0]                      jal_sonuc_w                                                 ;
+    //Dallanma buyruklari icin atliyorsa 1'b1, atlamiyorsa 1'b0 veren cikis
+    wire                                     db_sonuc_w                                                  ;
+    //DB'de guncellenmis program sayaci cikisi
+    wire         [31:0]                      siradaki_ps_db_w                                            ;
+    //TCB icin durum sinyalleri
+    
+    reg                                      tcb_hazir_r      =0                                           ;
+    wire                                     tcb_bitti_w                                                 ;
+    wire         [31:0]                      tcb_sonuc_w                                                 ;
+    reg                                      tcb_mesgul_r         = 0                                ;
+    reg                                      tcb_mesgul_sonraki_r = 0  ;
+    //TBB icin durum ve sonuc sinyalleri
+    reg                                      tbb_hazir_r      =0                                         ;
+    wire                                     tbb_bitti_w                                                 ;
+    wire         [31:0]                      tbb_sonuc_w                                                 ;
+    reg                                      tbb_mesgul_r         = 0                                ;
+    reg                                      tbb_mesgul_sonraki_r = 0  ;
+    //BIB icin durum sinyalleri
+    wire         [31:0]                      oku_veri_bib_w                                              ;
+    wire                                     bib_bitti_w                                                 ;
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+
+    
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    ////*************************************Modul Cagirma********************************************////
+    aritmetik_mantik_birimi amb_unit (
+                 //Girisler
+                 .islev_kodu_g             (islev_kodu_w)      ,
+                 .islec1_g                 (is1_sec_r)         ,
+                 .islec2_g                 (is2_sec_r)         ,
+                 //Cikislar
+                 .sonuc_c                  (amb_sonuc_w)
+                 );
+                 
+    dallanma_birimi db(
+                 //Girisler                 
+                 .islev_kodu_g             (islev_kodu_w[7:0]) ,
+                 .ps_g                     (ps_w)              ,
+                 .islec1_g                 (is1_sec_r)         ,
+                 .islec2_g                 (is2_sec_r)         ,
+                 .anlik_g                  (anlik_deger_w)     ,
+                 //Cikislar
+                 .jal_sonuc_c              (jal_sonuc_w)       ,
+                 .dallanma_sonuc_c         (db_sonuc_w)        ,
+                 .ps_c                     (siradaki_ps_db_w)
+                 );
+
+   tamsayi_carpma_birimi tcb_unit (
+                //Girisler                
+                .clk_g                    (clk_g)             ,
+                .rst_g                    (rst_g)             ,
+                .islev_kodu_g             (islev_kodu_w[3:0]) ,
+                .islec1_g                 (is1_sec_r)         ,
+                .islec2_g                 (is2_sec_r)         ,
+                .hazir_g                  (tcb_hazir_r)       ,
+                //Cikislar
+                .bitti_c                  (tcb_bitti_w)       ,
+                .sonuc_c                  (tcb_sonuc_w)
+                );
+
+   tamsayi_bolme_birimi tbb_unit (
+                //Girisler                
+                .clk_g                    (clk_g)             ,
+                .rst_g                    (rst_g)             ,
+                .islev_kodu_g             (islev_kodu_w[3:0]) ,
+                .islec1_g                 (is1_sec_r)         ,
+                .islec2_g                 (is2_sec_r)         ,
+                .hazir_g                  (tbb_hazir_r)       ,
+                //Cikislar
+                .bitti_c                  (tbb_bitti_w)       ,
+                .sonuc_c                  (tbb_sonuc_w)
+                );
+
+    bellek_islem_birimi bib_unit (
+                 //Girisler
+                 .clk_g                     (clk_g)            ,  
+                 .rst_g                     (rst_g)            ,  
+                 .bellek_buyrugu            (bellek_buyrugu)   , 
+                 .islec1_g                  (is1_sec_r)        ,
+                 .islec2_g                  (is2_sec_r)        ,
+                 .anlik_g                   (anlik_deger_w)    ,
+                 .bellek_isaretli           (bellek_isaretli_w),
+                 .bellek_turu               (bellek_turu)      ,
+                 .bellek_hazir_g            (bellek_hazir_g)   ,
+                 .oku_veri_g                (oku_veri_g)       ,
+                 .oku_veri_gecerli_g        (oku_veri_gecerli_g)  ,
+                 //Cikislar
+                 .bitti_c                   (bib_bitti_w)      ,
+                 .oku_veri_c                (oku_veri_bib_w)   ,
+                 .adres_bib_c               (adres_c)          ,
+                 .oku_gecerli_bib_c         (oku_gecerli_c)    ,
+                 .yaz_gecerli_bib_c         (yaz_gecerli_c)    ,
+                 .yaz_veri_bib_c            (yaz_veri_c)       ,
+                 .yaz_veri_bib_maske_c      (yaz_veri_maske_c)
+                 );
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+
+    assign                                   yoy_uis_c         = yoy_uis_r                               ;
+    // Atb: DDB'ye giden cikis sinyalleri
+    assign       ddy_oku_adres_c        =    ddy_adres_w                                                 ;                                                 
+    assign       ddy_oku_gecerli_c      =    ddy_oku_r                                                   ;                                                 
+        
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    ////*************************************Birlesik Devre*******************************************////
+    always@* begin
+        yoy_odd_adres_c         = 0             ; // TODO duzelt
+        tcb_mesgul_sonraki_r = tcb_mesgul_r;
+        tbb_mesgul_sonraki_r = tbb_mesgul_r;
+        siradaki_ps_c           = ps_w          ;
+        ddy_yaz_r               = `LOW          ;
+        yazmac_yaz_r            = `LOW          ;
+        yoy_odd_c               = `LOW          ;
+        //Yazmac obegine gonderilec ek kaynak yazmaclarinin adresleri
+        // 1.kaynak-yazmac adresinin yazmac obegine gonderilmesi
+        yo_ky1_adres_c          = ky1_w         ;
+        // 2.kaynak-yazmac adresinin yazmac obegine gonderilmesi
+        yo_ky2_adres_c          = ky2_w         ; 
+        
+        ddy_oku_r               = `LOW          ;
+        //yoy_uis_sonraki_r       = yoy_uis_r   ;
+        yoy_uis_sonraki_r       = gc_uis_g      ;
+
+        yoy_odd_ps_c            = ps_w          ;  
+
+        gc_duraklat_c           = `LOW          ;
+        gc_bosalt_c             = `LOW          ;
+        
+        // Inferred latchleri onlemek icin
+        // is2_sec_r               = 0             ;
+        // is1_sec_r               = 0             ;
+        yoy_odd_kod_c           = 0             ;
+        ddy_yaz_veri_r          = 0             ;
+        hy_deger_r              = 0             ;
+        tcb_hazir_r             = `LOW          ;
+        tbb_hazir_r             = `LOW          ;
+
+        if(gecerli_w) begin
+
+            //Islec1 Secimi
+            case(is1_sec) 
+                //Islec1 -> Kaynak Yazmaci 
+                `IS1_SEC_KY1: begin
+                //(bir onceki buyruktaki hedef yazmaci mi okunacak?)
+                    if((ky1_w == yoy_uis_c[`HY+:`HY_BIT]) 
+                            && yoy_uis_c[`GECERLI] && yoy_uis_c[`HY_YAZ] 
+                            && yoy_uis_c[`HY+:`HY_BIT] != 5'b0)
+                        is1_sec_r = yoy_uis_c[`HY_DEGER+:`HY_DEGER_BIT]       ;
+                    else 
+                        is1_sec_r = yo_ky1_veri_g                             ;
+                end
+                //Islec1 -> Program sayac
+                `IS1_SEC_PS : is1_sec_r    = ps_w                             ;
+                //Islec1 -> 
+                `IS1_SEC_0  : is1_sec_r    = 0                                ;
+                default     : is1_sec_r               = 0             ;
+            endcase
+            
+            // Islec2 Secimi
+            case(is2_sec) 
+                //Islec2 -> Kaynak Yazmaci 
+                `IS2_SEC_KY2: begin 
+                //(bir onceki buyruktaki hedef yazmaci mi okunacak?)
+                    if((ky2_w == yoy_uis_c[`HY+:`HY_BIT])
+                            && yoy_uis_c[`GECERLI] && yoy_uis_c[`HY_YAZ]
+                            && yoy_uis_c[`HY+:`HY_BIT] != 5'b0)
+                        is2_sec_r = yoy_uis_c[`HY_DEGER+:`HY_DEGER_BIT]       ;
+                    else 
+                        is2_sec_r = yo_ky2_veri_g                             ;      
+                 end
+                //Islec2 -> Anlik Deger
+                `IS2_SEC_AD    : is2_sec_r   = anlik_deger_w                  ;
+                //Islec2 ->
+                `IS2_SEC_4     : is2_sec_r   = 4                              ; 
+                //Islec2 ->
+                `IS2_SEC_0     : is2_sec_r   = 0                              ; 
+                //Islec2 -> CSR anlik dege
+                `IS2_SEC_CSR_AD: is2_sec_r   = 0                              ;
+                default: is2_sec_r               = 0             ;
+            endcase
+            // Yurutme asamasinda yapilacak islem secimi
+            case(yurut_kodu_w) 
+                // AMB islemi
+                `YURUT_KODU_AMB: begin 
+                    // Hedef yazmacina amb sonucu yazilacak deger
+                    hy_deger_r   = amb_sonuc_w;
+                    // Hedef yazmacina deger yazilacagini belirtmek icin 1'b1
+                    yazmac_yaz_r = 1'b1       ;
+                 end
+                 //DB islem
+                `YURUT_KODU_DB : begin 
+                    //Atlama buyruklari geldiyse
+                    if(islev_kodu_w == `JAL || islev_kodu_w == `JALR ) begin
+                        //Hedef yazmacina yazilacak deger
+                        hy_deger_r     = jal_sonuc_w     ;
+                        //Hedef yazmacina deger yazilacagini belirtmek icin 1'b1
+                        yazmac_yaz_r   = 1'b1            ;
+                        // Program sayaci guncelleme
+                        gc_bosalt_c    = 1'b1            ;
+                        if (siradaki_ps_db_w[1:0] != 2'b00)
+                        begin
+                            yoy_odd_ps_c        =   siradaki_ps_db_w;
+                            yoy_odd_c           =   `HIGH;
+                            yoy_odd_kod_c       =   `KDD_HBA; 
+                        end 
+                        else begin
+                            siradaki_ps_c  = siradaki_ps_db_w;
+                        end
+                    end
+                    //Dallanma buyruklari geldiyse
+                    else begin
+                        //Eger dallanma yanlis cozulduyse
+                        if(db_sonuc_w) begin
+                            //Boruhatiini bosaltma
+                            gc_bosalt_c                 =   1'b1            ;
+                            if (siradaki_ps_db_w[1:0] != 2'b00)
+                            begin
+                                yoy_odd_ps_c        =   siradaki_ps_db_w;
+                                yoy_odd_c           =   `HIGH;
+                                yoy_odd_kod_c       =   `KDD_HBA; 
+                            end 
+                            else begin
+                            // Program sayaci guncelleme
+                                siradaki_ps_c         = siradaki_ps_db_w;
+                            end
+                        end
+                    end
+                        
+                end    
+                // Bellek islemleri
+                `YURUT_KODU_BIB: begin 
+                    // Bellek islemleri bitene kadar boru hattini durdur
+                    gc_duraklat_c = ~bib_bitti_w; 
+                    case(bellek_buyrugu)
+                        `FENCE_b: begin
+                            //gc_bosalt_c = 1'b1;
+                        end
+                        `YUKLE_b: begin
+                            if(oku_veri_gecerli_g) begin
+                                hy_deger_r   = oku_veri_bib_w    ; 
+                                yazmac_yaz_r = 1'b1              ;
+                            end
+                            else gc_duraklat_c = `HIGH;
+   
+                        end
+                        `KAYDET_b: begin
+                            yazmac_yaz_r = 1'b0;
+                        end
+                    endcase
+                end
+                `YURUT_KODU_TCB: begin
+                    // Islem bitene kadar boruhattini durdur
+                    gc_duraklat_c = ~tcb_bitti_w;
+                     
+                     // Islem yapilmaya baslandiysa
+                    if(tcb_mesgul_r) begin 
+                        //Sadece tek cevrim 1'b1 degerini almali(bkz.tcb_unit)
+                        tcb_hazir_r = 1'b0;
+                    end
+                    else begin
+                        //Islem yapmaya baslamadiysa basla
+                        tcb_hazir_r              = 1'b1;
+                        //Yeni islem gonderilmesini engelle
+                        tcb_mesgul_sonraki_r = 1'b1;
+                    end
+                    // Islem tamamlandiysa
+                    if(tcb_bitti_w) begin
+                        //Hedef yazmacina islem sonucunu yaz
+                        hy_deger_r   = tcb_sonuc_w;
+                        yazmac_yaz_r = 1'b1       ;
+                        //Yeni islem almaya hazir hale getir
+                        tcb_mesgul_sonraki_r = 1'b0;
+                    end            
+                end
+                //TCB'nin aynisi
+                `YURUT_KODU_TBB: begin 
+                    gc_duraklat_c = ~tbb_bitti_w;
+                    if(tbb_mesgul_r) begin
+                        tbb_hazir_r = 1'b0;
+                    end
+                    else begin
+                        tbb_hazir_r               = 1'b1;
+                        tbb_mesgul_sonraki_r  = 1'b1;
+                    end
+                    if(tbb_bitti_w) begin
+                        hy_deger_r                = tbb_sonuc_w;
+                        yazmac_yaz_r              = 1'b1       ;
+                        tbb_mesgul_sonraki_r  = 1'b0       ;
+                    end            
+                end
+                `YURUT_KODU_CSR: begin
+                    gc_bosalt_c = 1'b1;
+                    siradaki_ps_c = ps_w + 32'd4;
+                    if (islev_kodu_w == `CSRRW || islev_kodu_w == `CSRRWI) begin
+                        ddy_yaz_r = 1'b1;
+                        ddy_yaz_veri_r = is1_sec_r;
+                        if(hy_w == 0) begin
+                            ddy_oku_r = 1'b0;
+                        end
+                        else begin
+                            ddy_oku_r = 1'b1;
+                            yazmac_yaz_r = 1'b1;
+                            hy_deger_r =  (islev_kodu_w == `CSRRW)  ?
+                                           ddy_oku_veri_g : ddy_anlik_w;              
+                        end
+                    end
+                    else if (islev_kodu_w == `CSRRS || islev_kodu_w == `CSRRSI) begin
+                        ddy_oku_r = 1'b1;
+                        yazmac_yaz_r = 1'b0;
+                        if(ky1_w != 'd0) begin
+                            ddy_yaz_r = 1'b1;
+                            ddy_yaz_veri_r =  (islev_kodu_w == `CSRRS) ?
+                                              (ddy_oku_veri_g == 32'b0 ? 32'b0 : is1_sec_r) :
+                                              (ddy_oku_veri_g == 32'b0 ? 32'b0 : ky1_w);
+                        end 
+                    end
+                    else if (islev_kodu_w == `CSRRC || islev_kodu_w == `CSRRCI) begin
+                         ddy_oku_r = 1'b1;
+                        yazmac_yaz_r = 1'b0;
+                        if (ddy_anlik_w != 'd0) begin
+                            ddy_yaz_r = 1'b1;
+                            ddy_yaz_veri_r = (islev_kodu_w == `CSRRC) ?
+                                               (ddy_oku_veri_g == 32'b0 ? 32'b0 : ~is1_sec_r) :
+                                               (ddy_oku_veri_g == 32'b0 ? 32'b0 : ~ky1_w);
+                        end
+                    end
+    
+                end // YURUT_KODU_CSR
+                `YURUT_KODU_SISTEM: begin
+                    gc_bosalt_c     =       `HIGH               ;
+                    if (islev_kodu_w == `MRET) begin
+                        yoy_odd_c               = `HIGH         ;
+                        yoy_odd_kod_c           = `KDD_MRET     ;
+                    end
+                    yazmac_yaz_r    =       `LOW                ;
+                    ddy_yaz_r       =       `LOW                ;
+                end
+            endcase
+            
+        yoy_uis_sonraki_r[`HY_YAZ]                      = yazmac_yaz_r;
+        yoy_uis_sonraki_r[`GECERLI]                     = ~gc_duraklat_c;
+        yoy_uis_sonraki_r[`DDY_YAZ]                     = ddy_yaz_r;
+        yoy_uis_sonraki_r[`HY_DEGER+:`HY_DEGER_BIT]     = hy_deger_r;  
+        yoy_uis_sonraki_r[`DDY_VERI+:`DDY_VERI_BIT]     = ddy_yaz_veri_r;
+        end // if gecerli  
+        else begin
+            is1_sec_r               = 0             ;
+            is2_sec_r               = 0             ;
+
+
+        end 
+    end
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    ////*************************************Sirali Devre*********************************************////
+
+    always@(posedge clk_g) begin
+        if (rst_g) begin
+            tbb_mesgul_r        <= `LOW;
+            tcb_mesgul_r        <= `LOW;
+            yoy_uis_r           <= 0;
+        end
+        else begin
+            tcb_mesgul_r <= tcb_mesgul_sonraki_r ;
+            tbb_mesgul_r <= tbb_mesgul_sonraki_r ;
+            yoy_uis_r    <= yoy_uis_sonraki_r    ;
+        end
+        
+    end
+    //////////////////////////////////////////////////////////////////////////////////////////////////////
+    
+endmodule
diff --git a/verilog/rtl/yazmac_yaz.v b/verilog/rtl/yazmac_yaz.v
new file mode 100644
index 0000000..11160dc
--- /dev/null
+++ b/verilog/rtl/yazmac_yaz.v
@@ -0,0 +1,69 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+`timescale 1ns / 1ps
+
+// mikroislem denetim 53. bit yazmaca_yaz
+// mikroislem denetim 21:52 hedef yazmacina yazilacak deger
+// mikroislem denetim 16:20 hedef yazmac tanimlayicisi
+
+//`define DEBUG_YAZMAC_YAZ
+`ifndef GL_RTL_SIM
+`include "sabitler.vh"
+`include "mikroislem.vh"
+`endif
+
+module yazmac_yaz(
+    `ifdef GL_RTL_SIM
+    output                  io_gecerli,
+    output [`PS_BIT-1:0]    io_ps,
+    `endif
+
+    input                                   clk_g                                                   ,
+    input         [`UIS_BIT - 1: 0]         yoy_uis_g                                               ,
+
+    output   reg                            yo_yaz_c                                                ,
+    output   reg  [`BUY_HY_BIT - 1: 0]      yo_yaz_hedef_c                                          ,
+    output   reg  [31: 0]                   yo_yaz_veri_c                                           ,
+    
+    output   reg                            ddy_yaz_c                                               ,
+    output   reg  [11: 0]                   ddy_yaz_hedef_c                                         ,
+    output   reg  [31: 0]                   ddy_yaz_veri_c      
+    );
+
+`ifdef DEBUG_YAZMAC_YAZ
+
+    wire                            gecerli        =    yoy_uis_g[`GECERLI]                                                         ;
+    wire        [`PS_BIT-1:0]       ps             =    yoy_uis_g[`PS +: `PS_BIT]                                                   ;
+    wire        [`HY_DEGER_BIT-1:0] hy_deger       =    yoy_uis_g[`HY_DEGER +: `HY_DEGER_BIT]                                       ;
+    wire        [`HY_BIT-1:0]       hy_adres       =    yoy_uis_g[`HY+:`HY_BIT];
+    wire                            hy_yaz         =    yoy_uis_g[`HY_YAZ];
+
+`endif
+
+`ifdef GL_RTL_SIM
+    assign io_gecerli        =    yoy_uis_g[`GECERLI]                                                         ;
+    assign io_ps             =    yoy_uis_g[`PS +: `PS_BIT]                                                   ;
+`endif
+
+    always @* begin
+        yo_yaz_c        =    yoy_uis_g[`GECERLI] && yoy_uis_g[`HY_YAZ] && (!yoy_uis_g[`HY+:`HY_BIT] == {`HY_BIT{1'b0}})   ;
+        yo_yaz_hedef_c  =    yoy_uis_g[`HY+:`HY_BIT]                                               ;
+        yo_yaz_veri_c   =    yoy_uis_g[`HY_DEGER+:`HY_DEGER_BIT]                                   ;
+
+        ddy_yaz_c       =    yoy_uis_g[`GECERLI] &&  yoy_uis_g[`DDY_YAZ]                                                   ;
+        ddy_yaz_hedef_c =    yoy_uis_g[`DDY_ADRES+:`DDY_ADRES_BIT]                                 ;
+        ddy_yaz_veri_c  =    yoy_uis_g[`DDY_VERI+:`DDY_VERI_BIT]                                    ;
+    end
+endmodule
\ No newline at end of file