diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index 4ed435a..2744da3 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -4207,9 +4207,7 @@
 END BLOCKAGES
 SPECIALNETS 8 ;
     - vccd1 ( PIN vccd1 ) + USE POWER
-      + ROUTED met4 0 + SHAPE STRIPE ( 1270520 2535880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 1270520 2355880 ) via4_3100x3100
-      NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
+      + ROUTED met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2890520 3522800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2710520 3522800 ) via4_3100x3100
       NEW met4 0 + SHAPE STRIPE ( 2530520 3522800 ) via4_3100x3100
diff --git a/gds/flash_array_8x8.gds b/gds/flash_array_8x8.gds
index ab14352..ebff002 100644
--- a/gds/flash_array_8x8.gds
+++ b/gds/flash_array_8x8.gds
Binary files differ
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index a261c85..812c7d2 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/lef/flash_array_8x8.lef b/lef/flash_array_8x8.lef
index 29c4ef3..aad48ec 100644
--- a/lef/flash_array_8x8.lef
+++ b/lef/flash_array_8x8.lef
@@ -6,7 +6,7 @@
   CLASS BLOCK ;
   FOREIGN flash_array_8x8 ;
   ORIGIN 0.000 0.000 ;
-  SIZE 93.100 BY 500.000 ;
+  SIZE 93.100 BY 25.555 ;
   PIN sen2
     ANTENNAGATEAREA 0.504000 ;
     PORT
@@ -688,7 +688,7 @@
         RECT 41.040 -18.350 41.360 -18.030 ;
         RECT 41.440 -18.350 41.760 -18.030 ;
       LAYER met4 ;
-        RECT 38.685 -100.000 41.785 400.000 ;
+        RECT 38.685 -25.490 41.785 0.000 ;
     END
   END vccd1
   PIN vssd1
@@ -802,7 +802,7 @@
         RECT 130.690 -15.375 131.010 -15.055 ;
         RECT 131.090 -15.375 131.410 -15.055 ;
       LAYER met4 ;
-        RECT 128.685 -100.000 131.785 400.000 ;
+        RECT 128.685 -25.515 131.785 0.000 ;
     END
   END vssd1
   OBS
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 83fbd97..422d70c 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1645042645
+timestamp 1646066240
 << locali >>
 rect 260849 439875 260883 440113
 rect 260757 439841 260883 439875
@@ -53227,9 +53227,9 @@
 rect 592618 -7622 592650 -7386
 rect -8726 -7654 592650 -7622
 use flash_array_8x8  u_flash_array_8x8
-timestamp 1645042645
+timestamp 1646066240
 transform 1 0 246057 0 1 440000
-box 7737 -20000 26357 80000
+box 7737 -5103 26357 0
 << labels >>
 rlabel metal3 s 583520 285276 584960 285516 6 analog_io[0]
 port 0 nsew signal bidirectional
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index a88125e..eda4eff 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1645042647
+timestamp 1646066242
 << obsli1 >>
 rect 260481 431953 262723 440215
 << obsm1 >>
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 1d62efd..6c2b326 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h1m48s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,452.46,1,0,0,0,0,0,0,2,21,0,-1,-1,89869,162,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.16,0.18,0.0,0.0,-1,29,647,29,647,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11.0,10.0,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h1m47s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,452.61,1,0,0,0,0,0,0,2,21,0,-1,-1,89869,162,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,0.16,0.18,0.0,0.0,-1,29,647,29,647,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11.0,10.0,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0