diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index 43a4149..28cd438 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile
@@ -20,7 +20,7 @@
 .SILENT: clean all
 
 
-PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus
+PATTERNS = io_ports la_test1 la_test2 wb_port mprj_stimulus qf105_smoke
 
 all:  ${PATTERNS}
 
diff --git a/verilog/dv/qf105_smoke/Makefile b/verilog/dv/qf105_smoke/Makefile
new file mode 100644
index 0000000..3fd0b56
--- /dev/null
+++ b/verilog/dv/qf105_smoke/Makefile
@@ -0,0 +1,32 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
+
diff --git a/verilog/dv/qf105_smoke/qf105_smoke.c b/verilog/dv/qf105_smoke/qf105_smoke.c
new file mode 100644
index 0000000..1adec94
--- /dev/null
+++ b/verilog/dv/qf105_smoke/qf105_smoke.c
@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+
+// --------------------------------------------------------
+
+void main()
+{
+    reg_mprj_io_8 =  GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_9 =  GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_10 =  GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_11 =  GPIO_MODE_USER_STD_INPUT_NOPULL;
+
+    reg_mprj_io_12 =  GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_13 =  GPIO_MODE_USER_STD_OUTPUT;
+    reg_mprj_io_14 =  GPIO_MODE_USER_STD_OUTPUT;
+
+    reg_mprj_xfer = 1;
+    while (reg_mprj_xfer == 1);
+
+    reg_la1_data = 0x00000001;
+    reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+    reg_la1_data = 0x00000001;
+    reg_la1_data = 0x00000001;
+    reg_la1_data = 0x00000001;
+    reg_la1_data = 0x00000000;
+
+    //reg_mprj_io_15 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_16 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_17 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_18 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_19 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_20 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_21 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_22 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_23 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_24 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_25 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_26 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_27 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_28 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_29 =  GPIO_MODE_USER_STD_OUTPUT;
+    //reg_mprj_io_30 =  GPIO_MODE_USER_STD_OUTPUT;
+}
diff --git a/verilog/dv/qf105_smoke/qf105_smoke_tb.v b/verilog/dv/qf105_smoke/qf105_smoke_tb.v
new file mode 100644
index 0000000..3bfcdf2
--- /dev/null
+++ b/verilog/dv/qf105_smoke/qf105_smoke_tb.v
@@ -0,0 +1,161 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module qf105_smoke_tb;
+	reg clock;
+	reg RSTB;
+	reg CSB;
+	reg power1, power2;
+	reg power3, power4;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+
+	assign mprj_io_0 = mprj_io[7:0];
+	// assign mprj_io_0 = {mprj_io[8:4],mprj_io[2:0]};
+	assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+	end
+
+	initial begin
+		$dumpfile("qf105_smoke.vcd");
+		$dumpvars(0, qf105_smoke_tb);
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (100) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Mega-Project IO Ports (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+		`endif
+		$display("%c[0m",27);
+		$finish;
+	end
+
+	initial begin
+		RSTB <= 1'b0;
+		CSB  <= 1'b1;
+		#2000;
+		RSTB <= 1'b1;	    	// Release reset
+		#300000;
+		CSB = 1'b0;
+	end
+
+	initial begin		// Power-up sequence
+		power1 <= 1'b0;
+		power2 <= 1'b0;
+		power3 <= 1'b0;
+		power4 <= 1'b0;
+		#100;
+		power1 <= 1'b1;
+		#100;
+		power2 <= 1'b1;
+		#100;
+		power3 <= 1'b1;
+		#100;
+		power4 <= 1'b1;
+	end
+
+	//always @(mprj_io) begin
+	//	#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
+	//end
+
+	wire flash_csb;
+	wire flash_clk;
+	wire flash_io0;
+	wire flash_io1;
+
+	wire mspi_mosi = mprj_io[10];
+	wire mspi_miso;
+	assign mprj_io[11] = mspi_miso;
+	wire mspi_sclk = mprj_io[9];
+	wire mspi_csb  = mprj_io[8];
+
+	wire VDD3V3;
+	wire VDD1V8;
+	wire VSS;
+	
+	assign VDD3V3 = power1;
+	assign VDD1V8 = power2;
+	assign VSS = 1'b0;
+
+	caravel uut (
+		.vddio	  (VDD3V3),
+		.vddio_2  (VDD3V3),
+		.vssio	  (VSS),
+		.vssio_2  (VSS),
+		.vdda	  (VDD3V3),
+		.vssa	  (VSS),
+		.vccd	  (VDD1V8),
+		.vssd	  (VSS),
+		.vdda1    (VDD3V3),
+		.vdda1_2  (VDD3V3),
+		.vdda2    (VDD3V3),
+		.vssa1	  (VSS),
+		.vssa1_2  (VSS),
+		.vssa2	  (VSS),
+		.vccd1	  (VDD1V8),
+		.vccd2	  (VDD1V8),
+		.vssd1	  (VSS),
+		.vssd2	  (VSS),
+		.clock    (clock),
+		.gpio     (gpio),
+		.mprj_io  (mprj_io),
+		.flash_csb(flash_csb),
+		.flash_clk(flash_clk),
+		.flash_io0(flash_io0),
+		.flash_io1(flash_io1),
+		.resetb	  (RSTB)
+	);
+
+	spiflash #(
+		.FILENAME("qf105_smoke.hex")
+	) spiflash (
+		.csb(flash_csb),
+		.clk(flash_clk),
+		.io0(flash_io0),
+		.io1(flash_io1),
+		.io2(),			// not used
+		.io3()			// not used
+	);
+
+	mkQF100SPIFlashEmulator mspi (
+		.CLK(clock),
+		.RST_N(!mspi_csb),
+		.mosi_value(mspi_mosi),
+		.miso(mspi_miso),
+		.sclk_value(mspi_sclk),
+		.csb_value(mspi_csb)
+	);
+
+endmodule
+`default_nettype wire
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index f5047d5..f3169fc 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,3 +1,7 @@
 # Caravel user project includes	     
 -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v     
+-v $(USER_PROJECT_VERILOG)/gl/mkLanaiCPU.v
+-v $(USER_PROJECT_VERILOG)/gl/mkQF100Fabric.v
+-v $(USER_PROJECT_VERILOG)/gl/mkQF100Memory.v
+-v $(USER_PROJECT_VERILOG)/gl/mkQF100SPI.v
+-v $(USER_PROJECT_VERILOG)/gl/mkQF100GPIO.v
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 31ab09b..6c8cd91 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,5 +1,13 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/user_proj_example.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkQF105.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkQF100Fabric.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkQF100FlashController.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkQF100SPI.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkQF100GPIO.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkLanaiCPU.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkLanaiFrontend.v
+-v $(USER_PROJECT_VERILOG)/rtl/mkQF100SPIFlashEmulator.v
 
- 
\ No newline at end of file
+