)]}'
{
  "commit": "f9c75b385e3ba9e2ba4a2de3eecfc50229a9f457",
  "tree": "0b4666e859e990f5ea2283084a8ca9f978e04578",
  "parents": [
    "3e8bb57f771fd05fa9c3a73cfc17d7a549d37cfd"
  ],
  "author": {
    "name": "GokulKuppuswamy",
    "email": "gokulkg2701@gmail.com",
    "time": "Fri Mar 18 17:18:16 2022 +0530"
  },
  "committer": {
    "name": "GokulKuppuswamy",
    "email": "gokulkg2701@gmail.com",
    "time": "Fri Mar 18 17:18:16 2022 +0530"
  },
  "message": "New LVDT empty verilog file\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ea4046bcecf8dc1247476a0b7ab6c69a2fa36cd1",
      "old_mode": 33188,
      "old_path": "verilog/rtl/LVDT.v",
      "new_id": "c6821e65617b279a3c8bb0d49ce22b68c426ab51",
      "new_mode": 33188,
      "new_path": "verilog/rtl/LVDT.v"
    }
  ]
}