)]}'
{
  "commit": "896a02de356273bccbaa4a484e06ed686aa170f7",
  "tree": "e86093549891b2f29736150a92ffb692d45b37b4",
  "parents": [
    "cd40776de3fff8b59d046b2ec8e0455c119bc2f5"
  ],
  "author": {
    "name": "GokulKuppuswamy",
    "email": "gokulkg2701@gmail.com",
    "time": "Mon Mar 28 16:01:07 2022 +0530"
  },
  "committer": {
    "name": "GokulKuppuswamy",
    "email": "gokulkg2701@gmail.com",
    "time": "Mon Mar 28 16:01:07 2022 +0530"
  },
  "message": "Updated Gate level netlist\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "682e43d7724c4891a6b7a2fd95dd26f722865617",
      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
      "new_id": "3d908332382b40a9307e5309cdae6fc3f2ca65b9",
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}