diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl
index 4ea25c6..4f420af 100755
--- a/openlane/user_proj_example/config.tcl
+++ b/openlane/user_proj_example/config.tcl
@@ -19,23 +19,46 @@
 
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../caravel/verilog/rtl/defines.v \
+        $script_dir/../../verilog/rtl/gps_engine/accumulator.v \
+        $script_dir/../../verilog/rtl/gps_engine/adc2to3bit.v \
+        $script_dir/../../verilog/rtl/gps_engine/clk_gen_gps_new.v \
+        $script_dir/../../verilog/rtl/gps_engine/codectrllogic.v \
+        $script_dir/../../verilog/rtl/gps_engine/codegen.v \
+        $script_dir/../../verilog/rtl/gps_engine/goldcode.v \
+        $script_dir/../../verilog/rtl/gps_engine/signmag_twocomp_vv.v \
+        $script_dir/../../verilog/rtl/gps_engine/signmul.v \
+        $script_dir/../../verilog/rtl/gps_engine/thresh_control.v \
+        $script_dir/../../verilog/rtl/gps_engine/threshold.v \
+        $script_dir/../../verilog/rtl/gps_engine/track_intganddump.v \
+        $script_dir/../../verilog/rtl/gps_engine/wb_interface.v \
+        $script_dir/../../verilog/rtl/gps_engine/gps_single_channel.v \
+        $script_dir/../../verilog/rtl/gps_engine/gps_multichannel.v \
 	$script_dir/../../verilog/rtl/user_proj_example.v"
-
-set ::env(CLOCK_PORT) ""
-set ::env(CLOCK_NET) "counter.clk"
+	
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
 set ::env(CLOCK_PERIOD) "10"
 
-set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 900 600"
 set ::env(DESIGN_IS_CORE) 0
+set ::env(FP_PDN_CORE_RING) 0
+set ::env(GLB_RT_MAXLAYER) 5
+set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 
 set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
 
-set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
+set ::env(SYNTH_MAX_FANOUT) 6
+set ::env(FP_CORE_UTIL) 20
+set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)+4) / 100.0 ]
+set ::env(CELL_PAD) 4
 
-set ::env(PL_BASIC_PLACEMENT) 1
-set ::env(PL_TARGET_DENSITY) 0.05
+set ::env(DIODE_INSERTION_STRATEGY) 0
+#set ::env(SYNTH_STRATEGY) 2
+#set ::env(SYNTH_STRATEGY) "DELAY 1"
+set ::env(SYNTH_NO_FLAT) 0
 
-# If you're going to use multiple power domains, then keep this disabled.
-set ::env(RUN_CVC) 0
+set ::env(ROUTING_CORES) 16
+
+set ::env(MAGIC_DRC_USE_GDS) 1
+set ::env(LVS_INSERT_POWER_PINS) 1
+
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 330cf57..1d86acf 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -30,8 +30,8 @@
 	$script_dir/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
 
 set ::env(CLOCK_PERIOD) "10"