)]}'
{
  "commit": "2880a6f722a2e61946b9a4d7b780bbd3e05beff8",
  "tree": "eb7fd3df7be7052271fe763cbd9650c607285ca6",
  "parents": [
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  "author": {
    "name": "GokulKuppuswamy",
    "email": "gokulkg2701@gmail.com",
    "time": "Tue Mar 29 12:25:34 2022 +0530"
  },
  "committer": {
    "name": "GokulKuppuswamy",
    "email": "gokulkg2701@gmail.com",
    "time": "Tue Mar 29 12:25:34 2022 +0530"
  },
  "message": "Final Gate level Netlist of Integrated Wrapper\n",
  "tree_diff": [
    {
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      "old_mode": 33188,
      "old_path": "verilog/gl/user_project_wrapper.v",
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