pins
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index 38a468b..5a14337 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ
diff --git a/mag/ashish.mag b/mag/ashish.mag
index 0d58b0a..1396763 100644
--- a/mag/ashish.mag
+++ b/mag/ashish.mag
@@ -1,10 +1,12 @@
magic
tech sky130A
magscale 1 2
-timestamp 1647888148
+timestamp 1647919040
<< nwell >>
rect 560 910 7640 2090
-rect 1790 -2020 7640 -810
+rect 1790 -960 7640 -810
+rect 1104 -1704 7640 -960
+rect 1790 -2020 7640 -1704
<< nmos >>
rect 90 160 120 660
rect 320 160 350 660
@@ -1037,13 +1039,13 @@
rect 6820 -1230 6920 -1130
rect 6820 -1570 6920 -1470
<< psubdiff >>
-rect -690 2484 -430 2514
-rect -1990 2324 -1730 2354
-rect -1990 2124 -1960 2324
-rect -1760 2124 -1730 2324
-rect -690 2284 -660 2484
-rect -460 2284 -430 2484
-rect -690 2254 -430 2284
+rect -812 2484 -552 2514
+rect -2112 2324 -1852 2354
+rect -2112 2124 -2082 2324
+rect -1882 2124 -1852 2324
+rect -812 2284 -782 2484
+rect -582 2284 -552 2484
+rect -812 2254 -552 2284
rect 310 2484 570 2514
rect 310 2284 340 2484
rect 540 2284 570 2484
@@ -1077,23 +1079,23 @@
rect 7580 2284 7880 2484
rect 7350 2254 7880 2284
rect 7990 2254 8250 2284
-rect -1990 2070 -1730 2124
+rect -2112 2070 -1852 2124
rect 7990 2030 8020 2254
rect 8220 2030 8250 2254
rect 7990 1940 8250 2030
-rect -1990 1280 -1730 1310
-rect -1990 1080 -1960 1280
-rect -1760 1080 -1730 1280
+rect -2112 1280 -1852 1310
+rect -2112 1080 -2082 1280
+rect -1882 1080 -1852 1280
rect 7990 1520 8250 1550
rect 7990 1320 8020 1520
rect 8220 1320 8250 1520
rect 7990 1290 8250 1320
-rect -1990 990 -1730 1080
+rect -2112 990 -1852 1080
rect 8010 830 8270 860
-rect -1990 570 -1730 600
-rect -1990 370 -1960 570
-rect -1760 370 -1730 570
-rect -1990 340 -1730 370
+rect -2112 570 -1852 600
+rect -2112 370 -2082 570
+rect -1882 370 -1852 570
+rect -2112 340 -1852 370
rect 8010 630 8040 830
rect 8240 630 8270 830
rect 8010 600 8270 630
@@ -1101,30 +1103,34 @@
rect 1320 30 1370 80
rect 1450 30 1490 80
rect 1320 10 1490 30
-rect -1990 -450 -1730 -420
-rect -1990 -650 -1960 -450
-rect -1760 -650 -1730 -450
+rect 5186 80 5356 100
+rect 5186 30 5236 80
+rect 5316 30 5356 80
+rect 5186 10 5356 30
+rect -2112 -450 -1852 -420
+rect -2112 -650 -2082 -450
+rect -1882 -650 -1852 -450
rect 8010 -190 8270 -160
rect 8010 -390 8040 -190
rect 8240 -390 8270 -190
rect 8010 -420 8270 -390
-rect -1990 -680 -1730 -650
-rect -1990 -1450 -1730 -1420
-rect -1990 -1650 -1960 -1450
-rect -1760 -1650 -1730 -1450
-rect -1990 -1680 -1730 -1650
+rect -2112 -680 -1852 -650
+rect -2112 -1450 -1852 -1420
+rect -2112 -1650 -2082 -1450
+rect -1882 -1650 -1852 -1450
+rect -2112 -1680 -1852 -1650
rect 8010 -1920 8270 -1890
rect 8010 -2120 8040 -1920
rect 8240 -2120 8270 -1920
rect 8010 -2150 8270 -2120
-rect -1800 -2200 -1540 -2170
-rect -1800 -2400 -1770 -2200
-rect -1570 -2400 -1540 -2200
-rect -1800 -2430 -1540 -2400
-rect -580 -2200 -320 -2170
-rect -580 -2400 -550 -2200
-rect -350 -2400 -320 -2200
-rect -580 -2430 -320 -2400
+rect -1922 -2200 -1662 -2170
+rect -1922 -2400 -1892 -2200
+rect -1692 -2400 -1662 -2200
+rect -1922 -2430 -1662 -2400
+rect -702 -2200 -442 -2170
+rect -702 -2400 -672 -2200
+rect -472 -2400 -442 -2200
+rect -702 -2430 -442 -2400
rect 280 -2200 540 -2170
rect 280 -2400 310 -2200
rect 510 -2400 540 -2200
@@ -1158,17 +1164,25 @@
rect 7550 -2400 7580 -2200
rect 7320 -2430 7580 -2400
<< nsubdiff >>
+rect 1020 1696 1240 1744
+rect 1020 1564 1058 1696
+rect 1198 1564 1240 1696
+rect 1020 1518 1240 1564
rect 7090 1720 7320 1760
rect 7090 1540 7130 1720
rect 7290 1540 7320 1720
rect 7090 1510 7320 1540
+rect 1412 -1358 1632 -1310
+rect 1412 -1490 1450 -1358
+rect 1590 -1490 1632 -1358
+rect 1412 -1536 1632 -1490
rect 7050 -1100 7280 -1060
rect 7050 -1280 7090 -1100
rect 7250 -1280 7280 -1100
rect 7050 -1310 7280 -1280
<< psubdiffcont >>
-rect -1960 2124 -1760 2324
-rect -660 2284 -460 2484
+rect -2082 2124 -1882 2324
+rect -782 2284 -582 2484
rect 340 2284 540 2484
rect 1340 2284 1540 2484
rect 2360 2284 2560 2484
@@ -1178,17 +1192,18 @@
rect 6380 2284 6580 2484
rect 7380 2284 7580 2484
rect 8020 2030 8220 2254
-rect -1960 1080 -1760 1280
+rect -2082 1080 -1882 1280
rect 8020 1320 8220 1520
-rect -1960 370 -1760 570
+rect -2082 370 -1882 570
rect 8040 630 8240 830
rect 1370 30 1450 80
-rect -1960 -650 -1760 -450
+rect 5236 30 5316 80
+rect -2082 -650 -1882 -450
rect 8040 -390 8240 -190
-rect -1960 -1650 -1760 -1450
+rect -2082 -1650 -1882 -1450
rect 8040 -2120 8240 -1920
-rect -1770 -2400 -1570 -2200
-rect -550 -2400 -350 -2200
+rect -1892 -2400 -1692 -2200
+rect -672 -2400 -472 -2200
rect 310 -2400 510 -2200
rect 1310 -2400 1510 -2200
rect 2330 -2400 2530 -2200
@@ -1198,7 +1213,9 @@
rect 6350 -2400 6550 -2200
rect 7350 -2400 7550 -2200
<< nsubdiffcont >>
+rect 1058 1564 1198 1696
rect 7130 1540 7290 1720
+rect 1450 -1490 1590 -1358
rect 7090 -1280 7250 -1100
<< poly >>
rect 1520 1880 1640 1900
@@ -1889,11 +1906,11 @@
rect 6440 -1770 6520 -1700
rect 6700 -1770 6780 -1700
<< locali >>
-rect -2100 2484 8350 2594
-rect -2100 2324 -660 2484
-rect -2100 2124 -1960 2324
-rect -1760 2284 -660 2324
-rect -460 2284 340 2484
+rect -2222 2484 8350 2594
+rect -2222 2324 -782 2484
+rect -2222 2124 -2082 2324
+rect -1882 2284 -782 2324
+rect -582 2284 340 2484
rect 540 2284 1340 2484
rect 1540 2284 2360 2484
rect 2560 2284 3360 2484
@@ -1902,10 +1919,10 @@
rect 5580 2284 6380 2484
rect 6580 2284 7380 2484
rect 7580 2284 8350 2484
-rect -1760 2254 8350 2284
-rect -1760 2144 8020 2254
-rect -1760 2124 -1650 2144
-rect -2100 1280 -1650 2124
+rect -1882 2254 8350 2284
+rect -1882 2144 8020 2254
+rect -1882 2124 -1772 2144
+rect -2222 1280 -1772 2124
rect 7900 2030 8020 2144
rect 8220 2030 8350 2254
rect 1520 1880 1640 1900
@@ -1988,7 +2005,12 @@
rect 6730 1810 6750 1880
rect 6830 1810 6850 1880
rect 6730 1790 6850 1810
+rect 1036 1698 1224 1728
rect 7090 1720 7320 1760
+rect 1036 1696 1060 1698
+rect 1036 1564 1058 1696
+rect 1198 1564 1224 1698
+rect 1036 1540 1224 1564
rect 1380 1680 1520 1700
rect 1380 1580 1400 1680
rect 1500 1580 1520 1680
@@ -2094,8 +2116,8 @@
rect 2020 1300 2040 1400
rect 1900 1280 2040 1300
rect 2170 1340 2310 1360
-rect -2100 1080 -1960 1280
-rect -1760 1080 -1650 1280
+rect -2222 1080 -2082 1280
+rect -1882 1080 -1772 1280
rect 2170 1240 2190 1340
rect 2290 1240 2310 1340
rect 2170 1220 2310 1240
@@ -2173,7 +2195,7 @@
rect 6850 1220 6990 1240
rect 7900 1320 8020 1520
rect 8220 1320 8350 1520
-rect -2100 570 -1650 1080
+rect -2222 570 -1772 1080
rect 7900 830 8350 1320
rect 50 770 160 790
rect 50 700 70 770
@@ -2297,8 +2319,8 @@
rect 6720 680 6830 700
rect 7900 630 8040 830
rect 8240 630 8350 830
-rect -2100 370 -1960 570
-rect -1760 370 -1650 570
+rect -2222 370 -2082 570
+rect -1882 370 -1772 570
rect -80 610 60 630
rect -80 510 -60 610
rect 40 510 60 610
@@ -2423,7 +2445,7 @@
rect 6820 510 6840 610
rect 6940 510 6960 610
rect 6820 490 6960 510
-rect -2100 -450 -1650 370
+rect -2222 -450 -1772 370
rect -80 310 60 330
rect -80 210 -60 310
rect 40 210 60 310
@@ -2552,6 +2574,10 @@
rect 1320 20 1340 90
rect 1470 20 1490 90
rect 1320 10 1490 20
+rect 5186 90 5356 100
+rect 5186 20 5206 90
+rect 5336 20 5356 90
+rect 5186 10 5356 20
rect -80 -100 60 -80
rect -80 -200 -60 -100
rect 40 -200 60 -100
@@ -2677,8 +2703,8 @@
rect 6940 -200 6960 -100
rect 6820 -220 6960 -200
rect 7900 -190 8350 630
-rect -2100 -650 -1960 -450
-rect -1760 -650 -1650 -450
+rect -2222 -650 -2082 -450
+rect -1882 -650 -1772 -450
rect -80 -400 60 -380
rect -80 -500 -60 -400
rect 40 -500 60 -400
@@ -2805,7 +2831,7 @@
rect 6820 -520 6960 -500
rect 7900 -390 8040 -190
rect 8240 -390 8350 -190
-rect -2100 -1450 -1650 -650
+rect -2222 -1450 -1772 -650
rect 50 -590 160 -570
rect 50 -660 70 -590
rect 140 -660 160 -590
@@ -3006,8 +3032,13 @@
rect 7050 -1280 7090 -1100
rect 7250 -1280 7280 -1100
rect 7050 -1310 7280 -1280
-rect -2100 -1650 -1960 -1450
-rect -1760 -1650 -1650 -1450
+rect -2222 -1650 -2082 -1450
+rect -1882 -1650 -1772 -1450
+rect 1428 -1356 1616 -1326
+rect 1428 -1358 1452 -1356
+rect 1428 -1490 1450 -1358
+rect 1590 -1490 1616 -1356
+rect 1428 -1514 1616 -1490
rect 2120 -1470 2260 -1450
rect 2120 -1570 2140 -1470
rect 2240 -1570 2260 -1470
@@ -3084,7 +3115,7 @@
rect 6800 -1570 6820 -1470
rect 6920 -1570 6940 -1470
rect 6800 -1590 6940 -1570
-rect -2100 -2090 -1650 -1650
+rect -2222 -2090 -1772 -1650
rect 2260 -1700 2380 -1680
rect 2260 -1770 2280 -1700
rect 2360 -1770 2380 -1700
@@ -3159,14 +3190,14 @@
rect 6680 -1790 6800 -1770
rect 7900 -1920 8350 -390
rect 7900 -2090 8040 -1920
-rect -2100 -2120 8040 -2090
+rect -2222 -2120 8040 -2090
rect 8240 -2120 8350 -1920
-rect -2100 -2198 8350 -2120
-rect -2100 -2200 -554 -2198
-rect -352 -2200 8350 -2198
-rect -2100 -2400 -1770 -2200
-rect -1570 -2400 -554 -2200
-rect -350 -2400 310 -2200
+rect -2222 -2198 8350 -2120
+rect -2222 -2200 -676 -2198
+rect -474 -2200 8350 -2198
+rect -2222 -2400 -1892 -2200
+rect -1692 -2400 -676 -2200
+rect -472 -2400 310 -2200
rect 510 -2400 1310 -2200
rect 1510 -2400 2330 -2200
rect 2530 -2400 3330 -2200
@@ -3175,7 +3206,7 @@
rect 5550 -2400 6350 -2200
rect 6550 -2400 7350 -2200
rect 7550 -2400 8350 -2200
-rect -2100 -2540 8350 -2400
+rect -2222 -2540 8350 -2400
<< viali >>
rect 1540 1810 1620 1880
rect 1800 1810 1880 1880
@@ -3197,6 +3228,8 @@
rect 6230 1810 6310 1880
rect 6490 1810 6570 1880
rect 6750 1810 6830 1880
+rect 1060 1696 1198 1698
+rect 1060 1568 1198 1696
rect 1400 1580 1500 1680
rect 1920 1580 2020 1680
rect 2190 1580 2290 1680
@@ -3286,6 +3319,11 @@
rect 1370 30 1450 80
rect 1450 30 1470 80
rect 1340 20 1470 30
+rect 5206 80 5336 90
+rect 5206 30 5236 80
+rect 5236 30 5316 80
+rect 5316 30 5336 80
+rect 5206 20 5336 30
rect 170 -200 270 -100
rect 630 -200 730 -100
rect 1090 -200 1190 -100
@@ -3358,6 +3396,8 @@
rect 6300 -1230 6400 -1130
rect 6820 -1230 6920 -1130
rect 7090 -1280 7250 -1100
+rect 1452 -1358 1590 -1356
+rect 1452 -1486 1590 -1358
rect 2400 -1570 2500 -1470
rect 2920 -1570 3020 -1470
rect 3440 -1570 3540 -1470
@@ -3385,9 +3425,9 @@
rect 6180 -1770 6260 -1700
rect 6440 -1770 6520 -1700
rect 6700 -1770 6780 -1700
-rect -554 -2200 -352 -2198
-rect -554 -2400 -550 -2200
-rect -550 -2400 -352 -2200
+rect -676 -2200 -474 -2198
+rect -676 -2400 -672 -2200
+rect -672 -2400 -474 -2200
<< metal1 >>
rect 1520 1880 1640 1900
rect 1520 1810 1540 1880
@@ -3469,7 +3509,11 @@
rect 6730 1810 6750 1880
rect 6830 1810 6850 1880
rect 6730 1790 6850 1810
+rect 1036 1698 1224 1728
rect 7090 1720 7320 1760
+rect 1036 1568 1060 1698
+rect 1198 1568 1224 1698
+rect 1036 1540 1224 1568
rect 1380 1680 1520 1700
rect 1380 1580 1400 1680
rect 1500 1580 1520 1680
@@ -3809,6 +3853,10 @@
rect 1320 20 1340 90
rect 1470 20 1490 90
rect 1320 10 1490 20
+rect 5186 90 5356 100
+rect 5186 20 5206 90
+rect 5336 20 5356 90
+rect 5186 10 5356 20
rect 150 -100 290 -80
rect 150 -200 170 -100
rect 270 -200 290 -100
@@ -4097,6 +4145,10 @@
rect 7050 -1280 7090 -1100
rect 7250 -1280 7280 -1100
rect 7050 -1310 7280 -1280
+rect 1428 -1356 1616 -1326
+rect 1428 -1486 1452 -1356
+rect 1590 -1486 1616 -1356
+rect 1428 -1514 1616 -1486
rect 2380 -1470 2520 -1450
rect 2380 -1570 2400 -1470
rect 2500 -1570 2520 -1470
@@ -4205,10 +4257,10 @@
rect 6680 -1770 6700 -1700
rect 6780 -1770 6800 -1700
rect 6680 -1790 6800 -1770
-rect -584 -2198 -312 -2172
-rect -584 -2400 -554 -2198
-rect -352 -2400 -312 -2198
-rect -584 -2430 -312 -2400
+rect -706 -2198 -434 -2172
+rect -706 -2400 -676 -2198
+rect -474 -2400 -434 -2198
+rect -706 -2430 -434 -2400
<< via1 >>
rect 1540 1810 1620 1880
rect 1800 1810 1880 1880
@@ -4230,6 +4282,7 @@
rect 6230 1810 6310 1880
rect 6490 1810 6570 1880
rect 6750 1810 6830 1880
+rect 1060 1568 1198 1698
rect 1400 1580 1500 1680
rect 1920 1580 2020 1680
rect 2190 1580 2290 1680
@@ -4315,6 +4368,7 @@
rect 6150 210 6250 310
rect 6610 210 6710 310
rect 1340 20 1470 90
+rect 5206 20 5336 90
rect 170 -200 270 -100
rect 630 -200 730 -100
rect 1090 -200 1190 -100
@@ -4387,6 +4441,7 @@
rect 6300 -1230 6400 -1130
rect 6820 -1230 6920 -1130
rect 7090 -1280 7250 -1100
+rect 1452 -1486 1590 -1356
rect 2400 -1570 2500 -1470
rect 2920 -1570 3020 -1470
rect 3440 -1570 3540 -1470
@@ -4414,7 +4469,7 @@
rect 6180 -1770 6260 -1700
rect 6440 -1770 6520 -1700
rect 6700 -1770 6780 -1700
-rect -554 -2400 -352 -2198
+rect -676 -2400 -474 -2198
<< metal2 >>
rect 2010 1920 2200 1950
rect 1520 1880 1900 1900
@@ -4483,7 +4538,10 @@
rect 6210 1790 6330 1810
rect 6470 1790 6590 1810
rect 6730 1790 6850 1810
+rect 1036 1698 1224 1728
rect 7090 1720 7320 1760
+rect 1036 1568 1060 1698
+rect 1198 1678 1224 1698
rect 1380 1680 1520 1700
rect 1900 1680 2040 1700
rect 2170 1680 2310 1700
@@ -4497,7 +4555,8 @@
rect 6330 1680 6470 1700
rect 6850 1680 6990 1700
rect 7090 1680 7130 1720
-rect 1350 1580 1400 1680
+rect 1350 1678 1400 1680
+rect 1198 1580 1400 1678
rect 1500 1580 1920 1680
rect 2020 1580 2190 1680
rect 2290 1580 2710 1680
@@ -4510,8 +4569,11 @@
rect 5930 1580 6350 1680
rect 6450 1580 6870 1680
rect 6970 1580 7130 1680
-rect 1380 1560 1520 1580
-rect 1900 1560 2040 1580
+rect 1198 1576 2040 1580
+rect 1198 1568 1224 1576
+rect 1036 1540 1224 1568
+rect 1380 1560 1520 1576
+rect 1900 1560 2040 1576
rect 2170 1560 2310 1580
rect 2690 1560 2830 1580
rect 3210 1560 3350 1580
@@ -4882,6 +4944,10 @@
rect 1320 20 1340 90
rect 1470 20 1490 90
rect 1320 10 1490 20
+rect 5186 90 5356 100
+rect 5186 20 5206 90
+rect 5336 20 5356 90
+rect 5186 10 5356 20
rect 150 -100 290 -80
rect 150 -200 170 -100
rect 270 -120 290 -100
@@ -5205,7 +5271,7 @@
rect 6280 -1130 6420 -1110
rect 6800 -1130 6940 -1110
rect 7050 -1130 7090 -1100
-rect 2120 -1230 2140 -1130
+rect 1888 -1230 2140 -1130
rect 2240 -1230 2660 -1130
rect 2760 -1230 3180 -1130
rect 3280 -1230 3700 -1130
@@ -5216,7 +5282,12 @@
rect 5880 -1230 6300 -1130
rect 6400 -1230 6820 -1130
rect 6920 -1230 7090 -1130
-rect 2120 -1250 2260 -1230
+rect 1888 -1236 2292 -1230
+rect 1428 -1356 1616 -1326
+rect 1428 -1486 1452 -1356
+rect 1590 -1370 1616 -1356
+rect 1892 -1370 1966 -1236
+rect 2120 -1250 2260 -1236
rect 2640 -1250 2780 -1230
rect 3160 -1250 3300 -1230
rect 3680 -1250 3820 -1230
@@ -5236,6 +5307,9 @@
rect 7250 -1280 7280 -1230
rect 7370 -1260 7590 -1230
rect 7050 -1310 7280 -1280
+rect 1590 -1478 1966 -1370
+rect 1590 -1486 1616 -1478
+rect 1892 -1480 1966 -1478
rect 2380 -1470 2520 -1450
rect 2900 -1470 3040 -1450
rect 3420 -1470 3560 -1450
@@ -5246,6 +5320,7 @@
rect 6020 -1470 6160 -1450
rect 6540 -1470 6680 -1450
rect 7100 -1470 7240 -1450
+rect 1428 -1514 1616 -1486
rect 2380 -1570 2400 -1470
rect 2500 -1570 2920 -1470
rect 3020 -1570 3440 -1470
@@ -5328,10 +5403,10 @@
rect 6680 -1790 6800 -1770
rect 2180 -1800 2210 -1790
rect 2000 -1830 2210 -1800
-rect -584 -2198 -312 -2172
-rect -584 -2400 -554 -2198
-rect -352 -2400 -312 -2198
-rect -584 -2430 -312 -2400
+rect -706 -2198 -434 -2172
+rect -706 -2400 -676 -2198
+rect -474 -2400 -434 -2198
+rect -706 -2430 -434 -2400
<< via2 >>
rect 1660 1810 1760 1880
rect 2040 1800 2170 1920
@@ -5351,6 +5426,7 @@
rect 4770 210 4870 310
rect 6610 210 6710 310
rect 1340 20 1470 90
+rect 5206 20 5336 90
rect 170 -200 270 -100
rect 630 -200 730 -100
rect 1090 -200 1190 -100
@@ -5366,7 +5442,7 @@
rect 7420 -1220 7550 -1100
rect 7120 -1560 7220 -1470
rect 2040 -1800 2180 -1690
-rect -554 -2400 -352 -2198
+rect -676 -2400 -474 -2198
<< metal3 >>
rect 2000 1920 2210 1960
rect 1640 1880 1780 1900
@@ -5389,7 +5465,7 @@
rect 1680 880 1710 960
rect 1470 850 1710 880
rect 650 780 710 840
-rect -1540 -400 -300 780
+rect -1662 -400 -422 780
rect 640 770 720 780
rect 640 700 650 770
rect 710 700 720 770
@@ -5454,9 +5530,9 @@
rect 1650 -200 1670 -100
rect 1530 -220 1670 -200
rect -80 -400 60 -380
-rect -1540 -500 -60 -400
+rect -1662 -500 -60 -400
rect 40 -500 60 -400
-rect -1540 -1820 -300 -500
+rect -1662 -1820 -422 -500
rect -80 -520 60 -500
rect 640 -590 720 -580
rect 640 -660 650 -590
@@ -5542,6 +5618,10 @@
rect 3390 -680 3490 -670
rect 3860 -740 3940 -220
rect 4770 -580 4870 190
+rect 5186 90 5356 100
+rect 5186 20 5206 90
+rect 5336 20 5356 90
+rect 5186 10 5356 20
rect 6590 -100 6730 -80
rect 6590 -200 6610 -100
rect 6710 -200 6730 -100
@@ -5577,10 +5657,10 @@
rect 2000 -1800 2040 -1690
rect 2180 -1800 2210 -1690
rect 2000 -1830 2210 -1800
-rect -584 -2198 -312 -2172
-rect -584 -2400 -554 -2198
-rect -352 -2400 -312 -2198
-rect -584 -2430 -312 -2400
+rect -706 -2198 -434 -2172
+rect -706 -2400 -676 -2198
+rect -474 -2400 -434 -2198
+rect -706 -2430 -434 -2400
<< via3 >>
rect 590 870 670 950
rect 690 870 770 950
@@ -5601,20 +5681,21 @@
rect 6660 880 6740 960
rect 6610 210 6710 310
rect 7120 230 7220 320
+rect 5206 20 5336 90
rect 6610 -200 6710 -100
rect 7120 -210 7220 -120
rect 3810 -850 3890 -770
rect 3910 -850 3990 -770
rect 6570 -850 6650 -770
rect 6670 -850 6750 -770
-rect -554 -2400 -352 -2198
+rect -676 -2400 -474 -2198
<< mimcap >>
-rect -1440 640 -398 680
-rect -1440 -1680 -1400 640
-rect -438 -1680 -398 640
-rect -1440 -1720 -398 -1680
+rect -1562 640 -520 680
+rect -1562 -1680 -1522 640
+rect -560 -1680 -520 640
+rect -1562 -1720 -520 -1680
<< mimcapcontact >>
-rect -1400 -1680 -438 640
+rect -1522 -1680 -560 640
<< metal4 >>
rect 560 950 800 980
rect 1470 960 1710 990
@@ -5639,13 +5720,13 @@
rect 1470 850 1710 880
rect 3770 850 4010 880
rect 6530 850 6770 880
-rect -1401 640 -437 641
-rect -1401 -1680 -1400 640
-rect -438 610 -437 640
+rect -1523 640 -559 641
+rect -1523 -1680 -1522 640
+rect -560 610 -559 640
rect -80 610 60 630
-rect -438 510 -60 610
+rect -560 510 -60 610
rect 40 510 60 610
-rect -438 -1680 -437 510
+rect -560 -1680 -559 510
rect -80 490 60 510
rect 6590 310 6730 330
rect 6590 210 6610 310
@@ -5657,24 +5738,31 @@
rect 6710 210 6730 230
rect 7100 210 7240 230
rect 6590 190 6730 210
-rect -1401 -1681 -437 -1680
+rect -1523 -1681 -559 -1680
rect -240 100 -50 102
rect 170 100 270 110
rect 630 100 730 110
rect 1090 100 1190 110
rect 1310 100 1500 120
+rect 5176 100 5366 120
rect -240 10 180 100
rect 260 10 640 100
rect 720 10 1100 100
-rect 1180 90 1500 100
+rect 1180 96 1500 100
+rect 5170 96 5366 100
+rect 1180 90 5366 96
rect 1180 20 1340 90
-rect 1470 20 1500 90
-rect 1180 10 1500 20
+rect 1470 20 5206 90
+rect 5336 20 5366 90
+rect 1180 12 5366 20
+rect 1180 10 1500 12
+rect 5170 10 5366 12
rect -240 -600 -152 10
rect 170 0 270 10
rect 630 0 730 10
rect 1090 0 1190 10
rect 1310 -10 1500 10
+rect 5176 -10 5366 10
rect 6590 -100 6730 -80
rect 6590 -200 6610 -100
rect 6710 -120 6730 -100
@@ -5709,17 +5797,17 @@
rect 6650 -850 6670 -770
rect 6750 -850 6780 -770
rect 6540 -880 6780 -850
-rect -584 -2198 -148 -2172
-rect -584 -2400 -554 -2198
-rect -352 -2254 -148 -2198
-rect -352 -2400 -150 -2254
-rect -584 -2430 -150 -2400
+rect -706 -2198 -148 -2172
+rect -706 -2400 -676 -2198
+rect -474 -2254 -148 -2198
+rect -474 -2400 -150 -2254
+rect -706 -2430 -150 -2400
<< labels >>
rlabel via3 7170 260 7170 260 1 von
rlabel via3 7170 -160 7170 -160 1 vop
-rlabel metal4 -330 560 -330 560 1 a
-rlabel metal3 -340 -450 -340 -450 1 b
rlabel metal2 1460 1840 1460 1840 1 cm
rlabel via3 210 50 210 50 1 gnd!
rlabel metal3 7240 1630 7240 1630 1 vdd!
+rlabel metal4 -452 560 -452 560 1 a
+rlabel metal3 -462 -450 -462 -450 1 b
<< end >>
diff --git a/mag/ro_divider_buffered.mag b/mag/ro_divider_buffered.mag
index 6cfb627..b154e19 100644
--- a/mag/ro_divider_buffered.mag
+++ b/mag/ro_divider_buffered.mag
@@ -1,6 +1,6 @@
magic
tech sky130A
-timestamp 1647865536
+timestamp 1647916358
<< locali >>
rect -665 8178 -464 8216
rect -665 8047 -635 8178
@@ -178,11 +178,11 @@
rect -1301 -8842 -1183 -8735
rect -1433 -10493 -1263 -10323
<< metal2 >>
-rect -1834 11459 -1332 11501
-rect -1834 11357 -1476 11459
-rect -1371 11357 -1332 11459
-rect -1834 11318 -1332 11357
-rect -1834 7371 -1632 11318
+rect -1835 11871 -337 11955
+rect -1833 11501 -1632 11871
+rect -1834 11421 -1632 11501
+rect -1834 11272 -1640 11421
+rect -1834 7371 -1632 11272
rect -980 9793 -515 9830
rect -980 9683 -664 9793
rect -551 9683 -515 9793
@@ -251,7 +251,6 @@
rect -1263 -10493 -1236 -10323
rect -1455 -10515 -1236 -10493
<< via2 >>
-rect -1476 11357 -1371 11459
rect -664 9683 -551 9793
rect -635 8047 -504 8178
rect -149 6764 -11 6902
@@ -264,10 +263,6 @@
rect -1301 -8842 -1183 -8735
rect -1433 -10493 -1263 -10323
<< metal3 >>
-rect -1504 11459 -1346 11479
-rect -1504 11357 -1476 11459
-rect -1371 11357 -1346 11459
-rect -1504 11335 -1346 11357
rect -676 9793 -542 9805
rect -676 9683 -664 9793
rect -551 9683 -542 9793
@@ -313,7 +308,6 @@
rect -1263 -10493 -1236 -10323
rect -1455 -10515 -1236 -10493
<< via3 >>
-rect -1476 11357 -1371 11459
rect -664 9683 -551 9793
rect -635 8047 -504 8178
rect -149 6764 -11 6902
@@ -329,11 +323,6 @@
rect -2967 11789 -2640 11800
rect -2967 11637 25 11789
rect -2967 11315 -2640 11637
-rect -1428 11479 -293 11487
-rect -1504 11459 -293 11479
-rect -1504 11357 -1476 11459
-rect -1371 11357 -293 11459
-rect -1504 11335 -293 11357
rect -2957 10935 -2647 11315
rect -2972 10826 -2647 10935
rect -2972 10118 -2652 10826
@@ -449,47 +438,47 @@
rect -711 -9559 -449 -9424
rect -711 -9700 -601 -9559
use tapered_buf tapered_buf_7
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 -374 0 1 -9948
box -470 -910 43675 401
use tapered_buf tapered_buf_6
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 -414 0 1 -8329
box -470 -910 43675 401
use tapered_buf tapered_buf_5
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 -335 0 1 -6548
box -470 -910 43675 401
use tapered_buf tapered_buf_4
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 -375 0 1 -4929
box -470 -910 43675 401
use tapered_buf tapered_buf_3
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 -256 0 1 -3271
box -470 -910 43675 401
-use tapered_buf tapered_buf_2
-timestamp 1647818295
-transform 1 0 -296 0 1 -1652
-box -470 -910 43675 401
use ro_complete ro_complete_0
-timestamp 1647865156
+timestamp 1647916358
transform 1 0 348 0 1 5690
box -348 -5690 4661 1440
-use tapered_buf tapered_buf_0
-timestamp 1647818295
-transform 1 0 100 0 1 8579
+use tapered_buf tapered_buf_2
+timestamp 1647889165
+transform 1 0 -296 0 1 -1652
box -470 -910 43675 401
use divider divider_0
-timestamp 1647865156
+timestamp 1647769399
transform 1 0 6289 0 1 4964
box -490 -235 4690 2150
+use tapered_buf tapered_buf_0
+timestamp 1647889165
+transform 1 0 100 0 1 8579
+box -470 -910 43675 401
use tapered_buf tapered_buf_1
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 60 0 1 10198
box -470 -910 43675 401
use tapered_buf tapered_buf_8
-timestamp 1647818295
+timestamp 1647889165
transform 1 0 65 0 1 11875
box -470 -910 43675 401
<< labels >>
@@ -505,5 +494,5 @@
rlabel space -324 8611 -324 8611 1 vcont
rlabel space -338 9736 -338 9736 1 out
rlabel space -395 10231 -395 10231 1 mc2
-rlabel space -390 11890 -390 11890 1 out
+rlabel space -356 11404 -356 11404 1 out
<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index 1f252a7..a5079c5 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,7 +1,7 @@
magic
tech sky130A
magscale 1 2
-timestamp 1647914498
+timestamp 1647918604
<< psubdiff >>
rect 193788 665794 196518 666014
rect 193788 663430 194026 665794
@@ -4229,6 +4229,11 @@
rect 331886 496068 332050 498418
rect 329208 495886 332050 496068
rect 87136 485928 88752 490636
+rect 425266 488978 426318 489018
+rect 425266 488662 436754 488978
+rect 425266 488522 436500 488662
+rect 436648 488522 436754 488662
+rect 425266 488484 436754 488522
rect 87136 460628 88744 485928
rect 329170 484246 332012 484412
rect 329170 481896 329316 484246
@@ -4255,11 +4260,7 @@
rect 80298 419168 80352 419486
rect 80662 419168 80690 419486
rect 80298 419096 80690 419168
-rect 80134 355930 80644 356006
-rect 80134 355582 80188 355930
-rect 80590 355582 80644 355930
-rect 80134 355516 80644 355582
-rect 87136 353226 88744 459416
+rect 87136 412812 88744 459416
rect 329456 457886 332298 458052
rect 329456 455536 329602 457886
rect 332134 455536 332298 457886
@@ -4276,10 +4277,25 @@
rect 329496 419686 329642 422036
rect 332174 419686 332338 422036
rect 329496 419504 332338 419686
+rect 425266 421074 426318 488484
+rect 425266 420958 437532 421074
+rect 425266 420828 437368 420958
+rect 437494 420828 437532 420958
+rect 425266 420802 437532 420828
rect 90912 419422 91228 419440
rect 90912 419194 90982 419422
rect 91176 419194 91228 419422
rect 90912 419142 91228 419194
+rect 425266 414218 426318 420802
+rect 425266 413132 426270 414218
+rect 407844 412812 426270 413132
+rect 87136 410254 426270 412812
+rect 87136 409946 409122 410254
+rect 80134 355930 80644 356006
+rect 80134 355582 80188 355930
+rect 80590 355582 80644 355930
+rect 80134 355516 80644 355582
+rect 87136 353226 88744 409946
rect 329458 407864 332300 408030
rect 329458 405514 329604 407864
rect 332136 405514 332300 407864
@@ -4457,18 +4473,20 @@
rect 329254 530404 331786 532754
rect 329180 517600 331712 519950
rect 329354 496068 331886 498418
+rect 436500 488522 436648 488662
rect 329316 481896 331848 484246
rect 329242 469092 331774 471442
rect 90886 459752 91154 459996
rect 96844 459752 97108 460040
rect 81864 421250 82064 421440
rect 80352 419168 80662 419486
-rect 80188 355582 80590 355930
rect 329602 455536 332134 457886
rect 329562 443812 332094 446162
rect 90320 421260 90554 421486
rect 329642 419686 332174 422036
+rect 437368 420828 437494 420958
rect 90982 419194 91176 419422
+rect 80188 355582 80590 355930
rect 329604 405514 332136 407864
rect 329530 392710 332062 395060
rect 329616 383900 332148 386250
@@ -4544,6 +4562,20 @@
rect 415130 698768 415200 699050
rect 415504 698768 415606 699050
rect 415130 682442 415606 698768
+rect 559094 693594 559532 693750
+rect 559094 693348 559184 693594
+rect 559420 693348 559532 693594
+rect 559094 691980 559532 693348
+rect 559094 691882 570096 691980
+rect 559094 691706 570108 691882
+rect 560042 690798 560264 690806
+rect 560042 690660 564314 690798
+rect 560042 689932 560264 690660
+rect 569940 690458 570108 691706
+rect 560022 686082 560264 689932
+rect 560022 685530 560244 686082
+rect 568790 685530 569324 685688
+rect 560022 685208 569324 685530
rect 415130 681972 431438 682442
rect 330362 680954 414596 680982
rect 330362 680484 430624 680954
@@ -4583,6 +4615,19 @@
rect 328816 663376 328962 665726
rect 331494 663376 331658 665726
rect 328816 663194 331658 663376
+rect 36470 660722 72504 661146
+rect 36470 660682 84928 660722
+rect 36470 660668 90350 660682
+rect 36470 660600 93666 660668
+rect 36470 660564 93668 660600
+rect 36470 660342 93400 660564
+rect 93628 660342 93668 660564
+rect 36470 660306 93668 660342
+rect 36470 660276 93666 660306
+rect 36470 660230 84928 660276
+rect 86204 660262 93666 660276
+rect 36470 659968 72504 660230
+rect 36522 653970 38022 659968
rect 87552 655878 91224 656038
rect 87552 655814 91232 655878
rect 87552 655802 93892 655814
@@ -4591,6 +4636,7 @@
rect 87552 655608 93892 655614
rect 87552 655548 91232 655608
rect 87552 655484 91224 655548
+rect 36590 246866 37924 653970
rect 87552 653022 88048 655484
rect 87168 652084 88368 653022
rect 86242 651744 88368 652084
@@ -4614,6 +4660,12 @@
rect 429422 621938 429758 678816
rect 430280 625178 430616 680484
rect 431064 628408 431400 681972
+rect 438282 648154 439522 648182
+rect 438282 648004 438326 648154
+rect 438484 648004 439522 648154
+rect 438282 647978 439522 648004
+rect 568790 637136 569324 685208
+rect 568790 636670 569396 637136
rect 431062 628176 438690 628408
rect 431062 628158 431792 628176
rect 431064 627724 431404 628158
@@ -4765,6 +4817,21 @@
rect 431654 611556 431708 611764
rect 431942 611556 438588 611764
rect 431654 611514 438588 611556
+rect 568862 589206 569396 636670
+rect 568862 588118 569472 589206
+rect 568938 541230 569472 588118
+rect 568938 540188 569550 541230
+rect 569016 493294 569550 540188
+rect 569016 492212 569616 493294
+rect 436448 488662 437010 488742
+rect 436448 488522 436500 488662
+rect 436648 488522 437010 488662
+rect 436448 488488 437010 488522
+rect 436382 485466 436660 485508
+rect 436382 485272 436420 485466
+rect 436608 485406 436660 485466
+rect 436608 485272 437222 485406
+rect 436382 485220 436660 485272
rect 431092 464726 436300 465002
rect 430226 461512 436300 461790
rect 430264 461498 430692 461512
@@ -4784,6 +4851,7 @@
rect 90250 421486 90614 438018
rect 90968 435054 91230 446278
rect 329416 446162 332258 446328
+rect 569082 446266 569616 492212
rect 329416 443812 329562 446162
rect 332094 443812 332258 446162
rect 329416 443630 332258 443812
@@ -4793,6 +4861,12 @@
rect 90554 421260 90614 421486
rect 90250 421092 90614 421260
rect 90950 423478 91218 424466
+rect 436888 424384 437680 424404
+rect 436228 424198 437680 424384
+rect 436228 423900 436302 424198
+rect 436646 423900 437680 424198
+rect 436228 423732 437680 423900
+rect 436888 423630 437680 423732
rect 80298 419486 80690 419550
rect 80298 419168 80352 419486
rect 80662 419168 80690 419486
@@ -4826,14 +4900,26 @@
rect 329496 422036 332338 422202
rect 329496 419686 329642 422036
rect 332174 419686 332338 422036
+rect 437328 420958 437634 420998
+rect 437328 420828 437368 420958
+rect 437494 420828 437634 420958
+rect 437328 420804 437634 420828
rect 329496 419504 332338 419686
rect 90950 419194 90982 419422
rect 91176 419194 91214 419422
rect 90950 419148 91214 419194
+rect 569010 413360 569652 446266
rect 329458 407864 332300 408030
rect 329458 405514 329604 407864
rect 332136 405514 332300 407864
+rect 569048 406966 569650 413360
+rect 569048 406646 569652 406966
+rect 569060 405840 569652 406646
rect 329458 405332 332300 405514
+rect 569002 405538 569804 405840
+rect 569002 404992 569152 405538
+rect 569652 404992 569804 405538
+rect 569002 404726 569804 404992
rect 329384 395060 332226 395226
rect 329384 392710 329530 395060
rect 332062 392710 332226 395060
@@ -4883,6 +4969,9 @@
rect 81342 291646 81402 292026
rect 81770 291646 81806 292026
rect 81342 291598 81806 291646
+rect 36590 246224 36888 246866
+rect 37684 246224 37924 246866
+rect 36590 245784 37924 246224
rect 85810 200510 87738 349636
rect 88090 349558 88776 349678
rect 88090 348956 88146 349558
@@ -4924,7 +5013,6 @@
rect 329424 274044 329570 276394
rect 332102 274044 332266 276394
rect 329424 273862 332266 274044
-rect 407356 259014 410032 259304
rect 329440 238186 332282 238352
rect 329440 235836 329586 238186
rect 332118 235836 332282 238186
@@ -5504,11 +5592,14 @@
rect 228208 698440 228956 699186
rect 330570 698704 331356 699404
rect 415200 698768 415504 699050
+rect 559184 693348 559420 693594
rect 328962 663376 331494 665726
+rect 93400 660342 93628 660564
rect 90648 655614 90854 655802
rect 329000 650632 331532 652982
rect 328962 636460 331494 638810
rect 329012 622110 331544 624460
+rect 438326 648004 438484 648154
rect 328974 607938 331506 610288
rect 329190 589392 331722 591742
rect 329152 575220 331684 577570
@@ -5526,19 +5617,23 @@
rect 329602 455536 332134 457886
rect 96568 451818 96762 452016
rect 96580 448878 96794 449076
+rect 436420 485272 436608 485466
rect 329562 443812 332094 446162
+rect 436302 423900 436646 424198
rect 80352 419168 80662 419486
rect 80314 382226 80706 382680
rect 78782 381750 79084 382048
rect 81446 378160 81838 378614
rect 329642 419686 332174 422036
rect 329604 405514 332136 407864
+rect 569152 404992 569652 405538
rect 329530 392710 332062 395060
rect 329616 383900 332148 386250
rect 329578 369728 332110 372078
rect 329504 356924 332036 359274
rect 81736 334106 82006 334358
rect 81402 291646 81770 292026
+rect 36888 246224 37684 246866
rect 329224 345074 331756 347424
rect 90310 334106 90598 334392
rect 329150 332270 331682 334620
@@ -5613,11 +5708,20 @@
rect 413780 698768 415200 699050
rect 415504 698768 417852 699050
rect 465732 698778 469804 702300
-rect 413780 698622 417852 698768
-rect 510880 698640 514952 702340
-rect 520902 698606 524974 702340
+rect 510880 700726 514952 702340
+rect 520902 700726 524974 702340
rect 566594 702300 571594 704800
-rect 567176 698412 571248 702300
+rect 413780 698622 417852 698768
+rect 467422 692178 469094 698778
+rect 567176 698574 571248 702300
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+rect 571080 698430 571248 698574
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+rect 559110 693594 559484 693668
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+rect 559420 693348 559484 693594
+rect 559110 693284 559484 693348
+rect 438280 691210 469094 692178
rect 16442 689368 20688 690532
rect 16442 688204 17538 689368
rect 18770 688342 20688 689368
@@ -5633,15 +5737,12 @@
rect 10036 683482 20294 684744
rect 10036 682240 10560 683482
rect 11608 682240 20294 683482
-rect 582300 682418 584800 682984
rect -800 680242 1700 680942
rect 10036 680936 20294 682240
rect 11666 680900 20294 680936
rect 16750 680872 20294 680900
rect 16768 678024 20294 680872
-rect 574234 678344 584800 682418
rect 16860 670474 20166 678024
-rect 582300 677984 584800 678344
rect 31538 670552 84670 670818
rect 87172 670552 89064 670640
rect 23060 670474 89064 670552
@@ -5655,6 +5756,10 @@
rect 328816 663376 328962 665726
rect 331494 663376 331658 665726
rect 328816 663194 331658 663376
+rect 93362 660564 93668 660600
+rect 93362 660342 93400 660564
+rect 93628 660342 93668 660564
+rect 93362 660306 93668 660342
rect 87394 655802 90980 656140
rect 87394 655614 90648 655802
rect 90854 655614 90980 655802
@@ -5663,12 +5768,32 @@
rect 328854 650632 329000 652982
rect 331532 650632 331696 652982
rect 328854 650450 331696 650632
+rect 438314 650478 439252 691210
+rect 467422 691170 469094 691210
+rect 582300 682418 584800 682984
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+rect 574234 682200 574506 682336
+rect 574636 682200 584800 682336
+rect 574234 678344 584800 682200
+rect 582300 677984 584800 678344
+rect 438314 650412 439382 650478
+rect 438314 650212 438986 650412
+rect 439194 650212 439382 650412
+rect 438314 650166 439382 650212
+rect 438314 650100 439252 650166
rect -800 648098 1660 648642
+rect 432466 648196 432750 648266
+rect 436670 648196 438504 648208
+rect 432466 648154 438504 648196
rect -800 644312 20156 648098
+rect 432466 648004 438326 648154
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+rect 432466 647952 438504 648004
+rect 432466 647948 436914 647952
+rect 432466 646744 432750 647948
rect -800 643842 1660 644312
+rect 432328 642524 432750 646744
rect 582340 644184 584800 644584
-rect 574030 640110 584800 644184
-rect 582340 639784 584800 640110
rect 328816 638810 331658 638976
rect -800 638250 1660 638642
rect -800 634464 20016 638250
@@ -5676,31 +5801,47 @@
rect 331494 636460 331658 638810
rect 328816 636278 331658 636460
rect -800 633842 1660 634464
-rect 582340 634254 584800 634584
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rect 328866 624460 331708 624626
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rect 331544 622110 331708 624460
rect 328866 621928 331708 622110
rect 328828 610288 331670 610454
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rect 328828 607938 328974 610288
rect 331506 607938 331670 610288
rect 328828 607756 331670 607938
+rect 432258 606336 432756 610394
+rect 432214 605746 444662 606336
rect 329044 591742 331886 591908
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rect 331722 589392 331886 591742
-rect 583520 589472 584800 589584
rect 329044 589210 331886 589392
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-rect 575062 584856 583716 585090
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-rect 575046 583398 583700 583562
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rect 329180 517600 331712 519950
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rect 96568 451818 96762 452016
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rect 329530 392710 332062 395060
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rect 331356 698704 333820 699404
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rect 327798 650632 329000 652982
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rect 88606 602608 107508 602698
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rect 328730 258182 334628 262902
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@@ -6768,7 +7041,8 @@
rect 177430 698572 178044 699236
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rect 330570 698704 331356 699404
-rect 513626 551694 516246 553978
+rect 559184 693348 559420 693594
+rect 573626 551694 576246 553978
<< metal5 >>
rect 165594 702300 170594 704800
rect 175894 702300 180894 704800
@@ -6791,6 +7065,13 @@
rect 329748 698704 330570 699404
rect 331356 698704 333820 699404
rect 329748 698310 333820 698704
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rect 128554 667272 189802 667342
rect 312956 667272 318892 667938
@@ -6799,11 +7080,13 @@
rect 97670 667262 318892 667264
rect 90404 666950 318892 667262
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rect 312838 661298 318892 663560
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@@ -6811,6 +7094,8 @@
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@@ -6834,14 +7119,17 @@
rect 313244 560458 318778 562112
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@@ -6885,13 +7173,19 @@
rect 313774 460186 318786 461276
rect 313774 459358 318788 460186
rect 313716 454000 318890 459358
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rect 313734 447634 318786 449552
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rect 313814 424336 318786 426590
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rect 313756 410076 318930 423508
rect 313598 406210 318930 410076
rect 313480 405686 318930 406210
@@ -6929,17 +7223,14 @@
rect 314104 278294 318786 285006
rect 314104 272782 320504 278294
rect 314104 270000 318786 272782
-rect 396756 270000 419348 270076
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+rect 106530 266000 346900 270000
rect 112040 264924 114408 266000
rect 111810 262996 114408 264924
rect 111810 256572 114380 262996
rect 314104 262902 318786 266000
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rect 111810 255126 114408 256572
rect 112040 241032 114408 255126
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rect 314104 256376 320080 256418
rect 111818 235962 114548 241032
rect 101184 233482 114548 235962
@@ -7000,45 +7291,45 @@
rect 584000 0 584100 704000
rect -100 -100 584100 0
use filter_buffered filter_buffered_0
-timestamp 1647914062
+timestamp 1647918604
transform 1 0 115808 0 1 59356
box -2 0 89610 28900
use pll_full_buffered2 pll_full_buffered2_0
-timestamp 1647910864
+timestamp 1647918604
transform 1 0 100982 0 1 174612
box -3258 0 88322 40874
-use ashish ashish_0
-timestamp 1647888148
-transform 1 0 406076 0 1 64768
-box -2100 -2540 8350 2594
use div_pd_buffered div_pd_buffered_0
-timestamp 1647914062
+timestamp 1647918604
transform 1 0 102890 0 1 341826
box -1894 -6452 88296 14680
-use divider_buffered divider_buffered_0
-timestamp 1647903160
-transform 1 0 409804 0 1 252392
-box -1492 -3136 88296 10326
use pd_buffered pd_buffered_0
-timestamp 1647913243
+timestamp 1647918604
transform 1 0 96910 0 1 454596
box -1894 -6512 88296 8906
use cp_buffered cp_buffered_0
-timestamp 1647912062
+timestamp 1647918604
transform 1 0 96826 0 1 525962
box -2796 -7196 88288 10904
+use divider_buffered divider_buffered_2
+timestamp 1647918604
+transform 1 0 437574 0 1 414122
+box -1492 -3136 88296 10326
use ro_divider_buffered ro_divider_buffered_0
-timestamp 1647903160
+timestamp 1647918604
transform 1 0 437678 0 1 468106
box -5944 -21716 87550 24552
use pll_full_buffered1 pll_full_buffered1_1
-timestamp 1647909110
+timestamp 1647918604
transform 1 0 93658 0 1 630304
box -2122 0 88316 32243
use ro_complete_buffered ro_complete_buffered_0
-timestamp 1647903160
+timestamp 1647918604
transform 1 0 440094 0 1 631512
box -5924 -21716 87550 20899
+use ashish ashish_0
+timestamp 1647888148
+transform 1 0 562822 0 1 688874
+box -2100 -2540 8350 2594
<< labels >>
flabel metal3 s 583520 269230 584800 269342 0 FreeSans 1120 0 0 0 gpio_analog[0]
port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 5634606..8b61b31 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -88,7 +88,7 @@
+ la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
+ la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
+ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 user_irq[0] user_irq[1] user_irq[2]
-+ vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
++ vccd1 vccd2 vssa1 vdda2 vssa2 vssd1 vssd2 wb_clk_i wb_rst_i wbs_ack_o wbs_adr_i[0]
+ wbs_adr_i[10] wbs_adr_i[11] wbs_adr_i[12] wbs_adr_i[13] wbs_adr_i[14] wbs_adr_i[15]
+ wbs_adr_i[16] wbs_adr_i[17] wbs_adr_i[18] wbs_adr_i[19] wbs_adr_i[1] wbs_adr_i[20]
+ wbs_adr_i[21] wbs_adr_i[22] wbs_adr_i[23] wbs_adr_i[24] wbs_adr_i[25] wbs_adr_i[26]
@@ -106,2150 +106,2200 @@
+ wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
+ wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
+ wbs_stb_i wbs_we_i
-C0 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
-C1 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF
-C3 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF
-C4 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF
-C5 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/z5 0.03fF
-C6 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z2 0.14fF
-C7 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in5 29.21fF
-C8 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C9 ashish_0/b ashish_0/a 7.46fF
-C10 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
-C11 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C12 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
-C13 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
-C14 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF
-C15 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF
-C16 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF
-C17 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
-C18 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF
-C19 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C20 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C21 div_pd_buffered_0/tapered_buf_0/in5 gpio_noesd[12] 26.29fF
-C22 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C23 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C24 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C25 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF
-C26 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C27 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C28 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C29 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C30 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in3 2.89fF
-C31 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
-C32 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C33 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
-C34 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_2/in3 4.78fF
-C35 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in2 0.84fF
-C36 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C37 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C38 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF
-C39 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C40 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C41 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF
-C42 io_analog[3] io_analog[8] 1.02fF
-C43 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF
-C44 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF
-C45 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in5 29.21fF
-C46 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
-C47 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C48 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF
-C49 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C50 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C51 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C52 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C53 gpio_analog[10] gpio_noesd[10] 1.36fF
-C54 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C55 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
-C56 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C57 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF
-C58 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C59 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF
-C60 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C61 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
-C62 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C63 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C64 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C65 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C66 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
-C67 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C68 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C69 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C70 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C71 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
-C72 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/A 0.15fF
-C73 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/Out 0.12fF
-C74 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF
-C75 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF
-C76 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF
-C77 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C78 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C79 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C80 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
-C81 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF
-C82 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF
-C83 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C84 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF
-C85 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C86 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in5 0.84fF
-C87 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C88 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C89 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C90 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C91 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C92 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C93 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
-C94 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C95 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C96 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF
-C97 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C98 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C99 io_analog[9] gpio_noesd[10] 3.45fF
-C100 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C101 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF
-C102 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF
-C103 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C104 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C105 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C106 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C107 ro_complete_buffered_0/ro_complete_0/a0 io_analog[5] 0.23fF
-C108 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF
-C109 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C110 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C111 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF
-C112 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C113 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF
-C114 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C115 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C116 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C117 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C118 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
-C119 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF
-C120 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF
-C121 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C122 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C123 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C124 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C125 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C126 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C127 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF
-C128 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C129 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C130 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C131 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C132 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF
-C133 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C134 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF
-C135 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF
-C136 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C137 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF
-C138 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF
-C139 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C140 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C141 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF
-C142 ashish_0/von ashish_0/a 8.93fF
-C143 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF
-C144 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF
-C145 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in1 0.22fF
-C146 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.05fF
-C147 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF
-C148 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF
-C149 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C150 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C151 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C152 gpio_noesd[7] gpio_analog[8] 1.68fF
-C153 io_analog[9] gpio_noesd[9] 1.19fF
-C154 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C155 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF
-C156 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C157 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C158 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C159 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF
-C160 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in3 1.27fF
-C161 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF
-C162 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C163 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C164 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C165 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C166 ro_complete_buffered_0/ro_complete_0/a4 io_analog[4] 0.20fF
-C167 gpio_noesd[10] gpio_noesd[11] 6.19fF
-C168 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C169 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF
-C170 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C171 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C172 io_analog[10] pd_buffered_0/pd_0/DIV 0.52fF
-C173 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C174 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF
-C175 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF
-C176 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in5 0.84fF
-C177 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C178 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C179 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C180 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF
-C181 gpio_noesd[8] gpio_analog[9] 1.10fF
-C182 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF
-C183 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
-C184 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C185 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C186 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
-C187 io_analog[10] gpio_analog[9] 1.15fF
-C188 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF
-C189 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C190 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C191 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C192 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
-C193 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF
-C194 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C195 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C196 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C197 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C198 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C199 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C200 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF
-C201 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF
-C202 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
-C203 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
-C204 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C205 pll_full_buffered2_0/tapered_buf_4/in1 pll_full_buffered2_0/tapered_buf_4/in5 0.22fF
-C206 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C207 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF
-C208 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C209 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF
-C210 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C211 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C212 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C213 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C214 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
-C215 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF
-C216 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/B 0.21fF
-C217 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/REF 0.02fF
-C218 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF
-C219 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C220 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C221 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C222 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C223 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF
-C224 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF
-C225 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C226 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C227 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C228 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C229 io_analog[9] gpio_noesd[12] 1.79fF
-C230 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF
-C231 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C232 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF
-C233 ashish_0/cm ashish_0/b 0.27fF
-C234 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C235 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C236 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C237 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF
-C238 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C239 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C240 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF
-C241 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
-C242 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.05fF
-C243 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C244 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C245 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C246 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF
-C247 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF
-C248 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF
-C249 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF
-C250 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF
-C251 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C252 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C253 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C254 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C255 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C256 gpio_noesd[8] io_analog[10] 3.39fF
-C257 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF
-C258 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C259 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C260 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF
-C261 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF
-C262 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF
-C263 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C264 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C265 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
-C266 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF
-C267 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C268 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C269 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C270 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C271 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C272 ro_complete_buffered_0/ro_complete_0/a1 io_analog[4] 0.32fF
-C273 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C274 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C275 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C276 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
-C277 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C278 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C279 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF
-C280 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C281 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF
-C282 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in5 2.89fF
-C283 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF
-C284 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C285 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_1/Z1 0.06fF
-C286 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C287 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C288 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C289 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C290 ro_complete_buffered_0/tapered_buf_5/in1 io_analog[5] 0.19fF
-C291 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C292 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C293 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/Out 0.15fF
-C294 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C295 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C296 io_analog[5] io_analog[4] 20.14fF
-C297 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
-C298 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF
-C299 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF
-C300 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C301 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/nor_1/Z1 0.80fF
-C302 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF
-C303 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C304 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C305 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C306 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in1 0.22fF
-C307 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DIV 0.12fF
-C308 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C309 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C310 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF
-C311 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/nor_1/A 0.21fF
-C312 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF
-C313 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF
-C314 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/divider_0/clk 0.19fF
-C315 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C316 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in5 0.22fF
-C317 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C318 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C319 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF
-C320 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF
-C321 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF
-C322 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C323 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C324 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF
-C325 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF
-C326 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF
-C327 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF
-C328 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C329 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
-C330 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
-C331 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C332 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
-C333 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C334 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C335 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C336 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF
-C337 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF
-C338 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C339 ro_complete_buffered_0/ro_complete_0/a0 io_analog[6] 0.23fF
-C340 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C341 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF
-C342 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
-C343 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C344 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C345 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C346 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C347 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C348 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C349 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C350 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in3 2.89fF
-C351 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C352 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C353 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C354 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF
-C355 ashish_0/cm ashish_0/von 1.96fF
-C356 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C357 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C358 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 1.07fF
-C359 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C360 ro_complete_buffered_0/tapered_buf_1/in1 io_analog[3] 0.19fF
-C361 io_analog[10] pll_full_buffered1_0/tapered_buf_1/in1 0.19fF
-C362 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C363 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in2 0.84fF
-C364 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C365 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C366 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF
-C367 filter_buffered_0/tapered_buf_0/in5 gpio_analog[17] 26.29fF
-C368 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C369 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C370 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF
-C371 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
-C372 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF
-C373 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z3 0.05fF
-C374 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z1 0.03fF
-C375 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C376 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C377 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF
-C378 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF
-C379 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF
-C380 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF
-C381 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C382 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF
-C383 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C384 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C385 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C386 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C387 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C388 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C389 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF
-C390 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF
-C391 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C392 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C393 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF
-C394 gpio_noesd[7] gpio_noesd[13] 0.80fF
-C395 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
-C396 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C397 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF
-C398 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C399 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C400 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF
-C401 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF
-C402 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C403 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF
-C404 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C405 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C406 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C407 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C408 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C409 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C410 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF
-C411 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
-C412 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
-C413 filter_buffered_0/filter_0/v gpio_analog[17] 0.54fF
-C414 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF
-C415 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C416 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF
-C417 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF
-C418 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/tspc_r_0/Qbar 0.21fF
-C419 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in4 29.21fF
-C420 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C421 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C422 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C423 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C424 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C425 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF
-C426 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF
-C427 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C428 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C429 io_analog[9] gpio_analog[9] 0.93fF
-C430 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.65fF
-C431 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C432 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C433 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C434 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF
-C435 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C436 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/tapered_buf_1/in5 0.22fF
-C437 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C438 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C439 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF
-C440 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C441 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF
-C442 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C443 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF
-C444 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF
-C445 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C446 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
-C447 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C448 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C449 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
-C450 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF
-C451 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/REF 0.65fF
-C452 gpio_noesd[8] gpio_analog[10] 0.48fF
-C453 divider_buffered_0/divider_0/mc2 divider_buffered_0/tapered_buf_0/in5 26.29fF
-C454 io_analog[10] gpio_analog[10] 1.17fF
-C455 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF
-C456 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
-C457 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C458 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C459 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C460 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF
-C461 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF
-C462 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF
-C463 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF
-C464 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C465 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF
-C466 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C467 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF
-C468 pll_full_buffered2_0/tapered_buf_5/in1 pll_full_buffered2_0/tapered_buf_5/in2 0.37fF
-C469 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C470 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/A 0.55fF
-C471 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF
-C472 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in4 4.78fF
-C473 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF
-C474 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF
-C475 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF
-C476 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in5 2.89fF
-C477 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF
-C478 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C479 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
-C480 gpio_noesd[8] io_analog[9] 0.91fF
-C481 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF
-C482 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF
-C483 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF
-C484 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C485 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C486 io_analog[9] io_analog[10] 1065.54fF
-C487 pll_full_buffered2_0/tapered_buf_1/in4 pll_full_buffered2_0/tapered_buf_1/in5 29.21fF
-C488 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C489 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
-C490 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C491 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C492 ro_complete_buffered_0/ro_complete_0/a1 io_analog[5] 0.22fF
-C493 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF
-C494 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/Out 0.08fF
-C495 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF
-C496 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C497 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF
-C498 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C499 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C500 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
-C501 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF
-C502 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF
-C503 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C504 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C505 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C506 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF
-C507 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C508 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
-C509 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
-C510 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C511 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C512 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C513 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
-C514 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF
-C515 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/and_0/OUT 0.03fF
-C516 ro_complete_buffered_0/ro_complete_0/a2 io_analog[3] 0.22fF
-C517 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in3 4.78fF
-C518 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C519 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C520 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C521 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
-C522 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF
-C523 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
-C524 gpio_noesd[10] pd_buffered_0/tapered_buf_2/in5 26.29fF
-C525 io_analog[6] io_analog[4] 1.25fF
-C526 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
-C527 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF
-C528 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF
-C529 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
-C530 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C531 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z3 0.38fF
-C532 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF
-C533 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF
-C534 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C535 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C536 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF
-C537 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/OUT 0.31fF
-C538 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C539 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
-C540 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF
-C541 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF
-C542 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/mc2 0.33fF
-C543 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C544 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
-C545 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C546 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
-C547 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF
-C548 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF
-C549 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C550 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C551 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF
-C552 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C553 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C554 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C555 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C556 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF
-C557 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C558 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C559 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C560 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF
-C561 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C562 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C563 gpio_noesd[8] gpio_noesd[11] 0.55fF
-C564 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C565 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF
-C566 io_analog[10] gpio_noesd[11] 1.30fF
-C567 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF
-C568 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C569 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF
-C570 ro_complete_buffered_0/ro_complete_0/a0 io_analog[7] 0.23fF
-C571 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF
-C572 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF
-C573 io_analog[7] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF
-C574 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C575 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C576 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF
-C577 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF
-C578 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF
-C579 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF
-C580 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C581 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C582 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C583 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF
-C584 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C585 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF
-C586 cp_buffered_0/tapered_buf_2/in1 cp_buffered_0/tapered_buf_2/in2 0.37fF
-C587 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF
-C588 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C589 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF
-C590 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF
-C591 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF
-C592 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF
-C593 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
-C594 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C595 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z1 0.01fF
-C596 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C597 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
-C598 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C599 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF
-C600 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C601 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C602 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF
-C603 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C604 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.04fF
-C605 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in1 0.22fF
-C606 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C607 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C608 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF
-C609 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF
-C610 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C611 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
-C612 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF
-C613 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
-C614 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF
-C615 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF
-C616 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF
-C617 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C618 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C619 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF
-C620 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C621 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF
-C622 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C623 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C624 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF
-C625 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C626 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C627 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C628 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF
-C629 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF
-C630 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF
-C631 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF
-C632 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF
-C633 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_1/Z1 0.06fF
-C634 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF
-C635 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C636 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C637 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C638 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.16fF
-C639 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C640 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF
-C641 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/pll_full_0/ref 26.29fF
-C642 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C643 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
-C644 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF
-C645 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C646 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C647 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C648 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF
-C649 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C650 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C651 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C652 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C653 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C654 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C655 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF
-C656 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF
-C657 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C658 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C659 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C660 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C661 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C662 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C663 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C664 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z4 0.36fF
-C665 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF
-C666 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C667 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF
-C668 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF
-C669 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/mc2 0.06fF
-C670 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.05fF
-C671 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C672 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C673 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
-C674 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/and_0/OUT 0.01fF
-C675 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.09fF
-C676 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
-C677 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF
-C678 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C679 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF
-C680 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C681 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out 26.29fF
-C682 io_analog[9] gpio_analog[10] 3.28fF
-C683 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF
-C684 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C685 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF
-C686 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C687 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C688 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C689 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF
-C690 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C691 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF
-C692 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
-C693 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
-C694 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF
-C695 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C696 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C697 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
-C698 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C699 ro_complete_buffered_0/tapered_buf_2/in1 io_analog[8] 0.19fF
-C700 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C701 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C702 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in1 0.22fF
-C703 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF
-C704 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C705 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF
-C706 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C707 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C708 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF
-C709 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C710 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF
-C711 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF
-C712 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
-C713 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF
-C714 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C715 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C716 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C717 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF
-C718 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C719 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C720 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF
-C721 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
-C722 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF
-C723 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C724 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C725 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C726 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C727 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C728 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C729 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C730 ro_complete_buffered_0/ro_complete_0/a1 io_analog[6] 0.22fF
-C731 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF
-C732 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
-C733 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C734 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF
-C735 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C736 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C737 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C738 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF
-C739 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF
-C740 io_clamp_high[0] io_analog[4] 0.53fF
-C741 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Z1 0.06fF
-C742 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF
-C743 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF
-C744 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF
-C745 ro_divider_buffered_0/tapered_buf_0/in2 ro_divider_buffered_0/tapered_buf_0/in3 1.27fF
-C746 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF
-C747 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C748 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C749 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C750 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in5 0.22fF
-C751 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C752 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF
-C753 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C754 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF
-C755 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C756 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
-C757 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C758 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C759 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C760 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C761 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF
-C762 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C763 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C764 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C765 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
-C766 io_analog[7] io_analog[4] 1.11fF
-C767 io_analog[6] io_analog[5] 21.00fF
-C768 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z3 0.45fF
-C769 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF
-C770 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C771 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF
-C772 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/Z1 0.18fF
-C773 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C774 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF
-C775 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C776 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF
-C777 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
-C778 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C779 gpio_analog[10] gpio_noesd[11] 0.49fF
-C780 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C781 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF
-C782 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C783 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C784 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C785 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF
-C786 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C787 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C788 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.21fF
-C789 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/REF 0.17fF
-C790 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in4 4.78fF
-C791 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF
-C792 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C793 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C794 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C795 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF
-C796 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C797 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF
-C798 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C799 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C800 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C801 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
-C802 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C803 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z4 0.15fF
-C804 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF
-C805 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF
-C806 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
-C807 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF
-C808 gpio_analog[7] cp_buffered_0/tapered_buf_2/in1 0.19fF
-C809 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF
-C810 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C811 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF
-C812 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF
-C813 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C814 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF
-C815 io_analog[9] gpio_noesd[11] 3.74fF
-C816 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C817 gpio_noesd[9] gpio_analog[8] 2.46fF
-C818 ro_complete_buffered_0/ro_complete_0/a0 io_analog[8] 0.23fF
-C819 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF
-C820 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C821 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.07fF
-C822 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF
-C823 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C824 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C825 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C826 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF
-C827 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C828 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C829 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C830 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C831 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Z3 0.03fF
-C832 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C833 io_clamp_high[1] io_analog[5] 0.53fF
-C834 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C835 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF
-C836 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C837 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF
-C838 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/mc2 0.06fF
-C839 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C840 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF
-C841 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C842 gpio_noesd[7] gpio_noesd[10] 0.73fF
-C843 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C844 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C845 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF
-C846 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C847 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
-C848 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF
-C849 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C850 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF
-C851 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C852 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF
-C853 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF
-C854 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C855 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF
-C856 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF
-C857 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF
-C858 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C859 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/mc2 0.16fF
-C860 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/pll_full_0/ref 26.29fF
-C861 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
-C862 ashish_0/cm ashish_0/a 0.27fF
-C863 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C864 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
-C865 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF
-C866 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C0 io_analog[7] io_analog[9] 1.28fF
+C1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C2 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF
+C3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C5 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C6 pd_buffered_0/tapered_buf_1/in1 pd_buffered_0/tapered_buf_1/in2 0.37fF
+C7 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C8 io_analog[4] ro_complete_buffered_0/ro_complete_0/a0 0.33fF
+C9 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C10 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in5 0.84fF
+C11 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in4 4.78fF
+C12 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.03fF
+C13 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C14 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF
+C15 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C16 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C17 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C18 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF
+C19 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/div 0.01fF
+C20 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C21 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF
+C22 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF
+C23 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C24 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C25 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF
+C26 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_divider_buffered_0/divider_0/clk 0.26fF
+C27 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in5 0.84fF
+C28 div_pd_buffered_0/tapered_buf_1/in3 div_pd_buffered_0/tapered_buf_1/in4 4.78fF
+C29 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/clk 0.14fF
+C30 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF
+C31 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C32 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C33 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C34 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C35 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C36 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C37 pll_full_buffered2_0/tapered_buf_1/in1 io_analog[9] 0.19fF
+C38 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C39 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C40 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C41 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in5 2.89fF
+C42 ashish_0/b ashish_0/a 7.45fF
+C43 gpio_noesd[9] gpio_noesd[8] 1.97fF
+C44 io_analog[3] ro_divider_buffered_0/ro_complete_0/a1 0.19fF
+C45 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.78fF
+C46 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C47 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C48 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C49 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C50 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF
+C51 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF
+C52 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C53 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C54 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/divider_0/clk 0.05fF
+C55 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF
+C56 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C57 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C58 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
+C59 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/A 0.01fF
+C60 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/in1 0.19fF
+C61 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C62 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C63 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C64 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in5 2.89fF
+C65 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/tapered_buf_2/in2 0.37fF
+C66 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C67 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.00fF
+C68 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C69 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF
+C70 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C71 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
+C72 gpio_noesd[7] io_analog[9] 1.42fF
+C73 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C74 io_analog[3] ro_complete_buffered_0/ro_complete_0/a0 0.20fF
+C75 filter_buffered_0/tapered_buf_1/in4 filter_buffered_0/tapered_buf_1/in5 29.21fF
+C76 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C77 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C78 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C79 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C80 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C81 io_analog[8] ro_complete_buffered_0/tapered_buf_2/in1 0.19fF
+C82 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in3 2.89fF
+C83 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C84 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C85 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C86 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C87 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF
+C88 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C89 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C90 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C91 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
+C92 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF
+C93 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C94 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C95 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C96 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C97 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C98 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C99 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF
+C100 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 gpio_noesd[14] 26.29fF
+C101 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C102 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF
+C103 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF
+C104 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a4 0.13fF
+C105 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C106 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.03fF
+C107 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C108 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C109 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C110 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a3 2.04fF
+C111 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C112 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 0.06fF
+C113 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C114 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C115 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C116 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C117 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C118 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C119 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C120 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C121 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
+C122 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
+C123 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF
+C124 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C125 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF
+C126 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.45fF
+C127 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C128 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C129 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C130 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C131 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/UP 0.45fF
+C132 gpio_noesd[14] gpio_noesd[10] 2.89fF
+C133 cp_buffered_0/tapered_buf_2/in4 cp_buffered_0/tapered_buf_2/in5 29.21fF
+C134 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
+C135 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C136 divider_buffered_0/tapered_buf_2/in3 divider_buffered_0/tapered_buf_2/in4 4.78fF
+C137 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C138 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C139 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C140 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C141 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in5 2.89fF
+C142 ro_divider_buffered_0/tapered_buf_6/in5 ro_divider_buffered_0/ro_complete_0/a2 26.29fF
+C143 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C144 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C145 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C146 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF
+C147 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in1 0.37fF
+C148 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in5 2.89fF
+C149 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/a0 3.46fF
+C150 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C151 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C152 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
+C153 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
+C154 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C155 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C156 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C157 gpio_noesd[14] gpio_noesd[8] 2.61fF
+C158 gpio_analog[3] gpio_analog[5] 1.06fF
+C159 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C160 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF
+C161 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF
+C162 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.29fF
+C163 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C164 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in5 2.89fF
+C165 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C166 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.00fF
+C167 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C168 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in5 0.84fF
+C169 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in2 0.37fF
+C170 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C171 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C172 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C173 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/div 0.51fF
+C174 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C175 io_analog[9] gpio_analog[10] 3.28fF
+C176 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C177 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
+C178 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/REF 0.17fF
+C179 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C180 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF
+C181 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C182 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C183 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C184 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C185 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF
+C186 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C187 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C188 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
+C189 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF
+C190 gpio_noesd[7] gpio_analog[10] 0.77fF
+C191 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.01fF
+C192 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C193 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C194 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in5 2.89fF
+C195 io_analog[4] gpio_analog[6] 0.64fF
+C196 io_analog[5] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
+C197 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C198 io_analog[6] io_analog[7] 1.12fF
+C199 io_analog[5] io_analog[8] 1.24fF
+C200 ro_divider_buffered_0/tapered_buf_6/in4 ro_divider_buffered_0/tapered_buf_6/in5 29.21fF
+C201 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C202 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/nor_1/B 0.38fF
+C203 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C204 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C205 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C206 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
+C207 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C208 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in5 0.22fF
+C209 div_pd_buffered_0/tapered_buf_0/in1 div_pd_buffered_0/tapered_buf_0/in5 0.22fF
+C210 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in5 29.21fF
+C211 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C212 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C213 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C214 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C215 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C216 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C217 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z1 1.07fF
+C218 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C219 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF
+C220 gpio_analog[3] gpio_noesd[4] 1.38fF
+C221 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a1 1.84fF
+C222 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C223 io_clamp_low[0] io_analog[4] 0.53fF
+C224 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Q 0.04fF
+C225 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C226 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
+C227 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
+C228 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C229 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C230 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C231 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 io_analog[2] 26.29fF
+C232 gpio_noesd[9] gpio_analog[8] 2.46fF
+C233 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C234 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_0/Q 0.22fF
+C235 cp_buffered_0/cp_0/out cp_buffered_0/cp_0/down 0.79fF
+C236 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF
+C237 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF
+C238 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C239 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C240 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C241 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C242 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF
+C243 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C244 io_analog[6] io_analog[9] 1.28fF
+C245 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C246 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF
+C247 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C248 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C249 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C250 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C251 io_analog[3] gpio_analog[6] 0.53fF
+C252 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C253 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF
+C254 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C255 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
+C256 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
+C257 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C258 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C259 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a4 0.12fF
+C260 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C261 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C262 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C263 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C264 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF
+C265 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
+C266 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C267 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C268 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C269 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C270 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C271 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/UP 0.11fF
+C272 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/clk 0.45fF
+C273 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/clk 0.64fF
+C274 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF
+C275 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C276 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
+C277 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in3 2.89fF
+C278 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C279 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C280 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C281 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF
+C282 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF
+C283 io_analog[10] pll_full_buffered2_0/pll_full_0/div 0.47fF
+C284 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C285 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.38fF
+C286 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
+C287 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C288 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C289 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C290 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C291 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C292 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
+C293 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C294 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C295 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in5 0.22fF
+C296 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C297 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF
+C298 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C299 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/clk 0.11fF
+C300 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C301 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF
+C302 div_pd_buffered_0/tapered_buf_0/in1 div_pd_buffered_0/pd_0/UP 0.19fF
+C303 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C304 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF
+C305 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C306 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C307 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C308 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C309 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C310 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in 0.19fF
+C311 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C312 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C313 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered2_0/pll_full_0/vco 1.58fF
+C314 gpio_analog[9] io_analog[9] 0.93fF
+C315 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/nor_1/A 0.15fF
+C316 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF
+C317 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in2 0.84fF
+C318 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF
+C319 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C320 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF
+C321 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
+C322 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/divider_0/mc2 26.29fF
+C323 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
+C324 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C325 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C326 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C327 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C328 pll_full_buffered2_0/tapered_buf_3/in5 pll_full_buffered2_0/tapered_buf_3/out 26.29fF
+C329 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/Z1 0.07fF
+C330 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C331 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF
+C332 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF
+C333 gpio_analog[9] gpio_noesd[7] 1.96fF
+C334 io_analog[4] ro_complete_buffered_0/ro_complete_0/a4 0.20fF
+C335 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in1 0.37fF
+C336 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C337 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C338 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/div 0.02fF
+C339 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF
+C340 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF
+C341 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in3 4.78fF
+C342 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
+C343 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C344 gpio_noesd[14] gpio_analog[8] 2.77fF
+C345 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in5 0.84fF
+C346 div_pd_buffered_0/tapered_buf_2/in3 div_pd_buffered_0/tapered_buf_2/in4 4.78fF
+C347 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF
+C348 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
+C349 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF
+C350 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z3 0.25fF
+C351 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C352 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C353 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C354 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/DOWN 0.03fF
+C355 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/A 0.16fF
+C356 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C357 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C358 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C359 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C360 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C361 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C362 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
+C363 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C364 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF
+C365 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
+C366 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF
+C367 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C368 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C369 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in3 2.89fF
+C370 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C371 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C372 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C373 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C374 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C375 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C376 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C377 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF
+C378 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C379 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C380 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF
+C381 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in5 2.89fF
+C382 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF
+C383 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF
+C384 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF
+C385 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C386 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C387 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C388 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.04fF
+C389 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF
+C390 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C391 io_analog[10] io_analog[9] 1065.06fF
+C392 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C393 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C394 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF
+C395 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF
+C396 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C397 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C398 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C399 gpio_noesd[12] io_analog[9] 1.79fF
+C400 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in1 0.37fF
+C401 divider_buffered_0/tapered_buf_1/in5 divider_buffered_0/tapered_buf_1/in2 0.84fF
+C402 pll_full_buffered2_0/pll_full_0/div pll_full_buffered2_0/pll_full_0/vco 2.26fF
+C403 gpio_noesd[7] io_analog[10] 5.73fF
+C404 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C405 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF
+C406 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
+C407 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C408 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in2 0.84fF
+C409 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in3 4.78fF
+C410 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF
+C411 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C412 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C413 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF
+C414 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in2 0.84fF
+C415 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in3 4.78fF
+C416 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF
+C417 gpio_noesd[12] gpio_noesd[7] 0.68fF
+C418 io_analog[3] ro_complete_buffered_0/ro_complete_0/a4 0.17fF
+C419 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C420 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF
+C421 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C422 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C423 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/pd_0/DIV 26.29fF
+C424 pll_full_buffered2_0/tapered_buf_1/in2 pll_full_buffered2_0/tapered_buf_1/in5 0.84fF
+C425 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.55fF
+C426 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C427 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C428 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C429 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/R 0.61fF
+C430 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.45fF
+C431 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF
+C432 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C433 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
+C434 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C435 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
+C436 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C437 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in3 1.27fF
+C438 io_analog[4] ro_complete_buffered_0/ro_complete_0/a1 0.32fF
+C439 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C440 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C441 io_analog[5] io_analog[7] 1.11fF
+C442 io_analog[4] io_analog[8] 1.24fF
+C443 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.19fF
+C444 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/tapered_buf_1/in5 26.29fF
+C445 io_analog[9] gpio_noesd[13] 2.15fF
+C446 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C447 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.22fF
+C448 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C449 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C450 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C451 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.80fF
+C452 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C453 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C454 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C455 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Z3 0.38fF
+C456 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C457 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C458 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C459 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF
+C460 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF
+C461 gpio_noesd[7] gpio_noesd[13] 0.80fF
+C462 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF
+C463 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C464 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C465 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF
+C466 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.14fF
+C467 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a5 0.13fF
+C468 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C469 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.80fF
+C470 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C471 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF
+C472 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C473 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/Out 0.11fF
+C474 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/A 0.01fF
+C475 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C476 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C477 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C478 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C479 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in5 2.89fF
+C480 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C481 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/UP 0.21fF
+C482 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C483 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C484 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C485 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/A 0.26fF
+C486 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C487 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.36fF
+C488 filter_buffered_0/filter_0/v gpio_analog[17] 0.54fF
+C489 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF
+C490 io_analog[4] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF
+C491 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.20fF
+C492 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C493 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C494 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C495 io_clamp_high[2] io_analog[6] 0.53fF
+C496 io_analog[10] gpio_analog[10] 1.17fF
+C497 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.45fF
+C498 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/clk 0.01fF
+C499 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.21fF
+C500 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C501 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C502 gpio_noesd[14] gpio_noesd[11] 2.58fF
+C503 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in3 1.27fF
+C504 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C505 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.36fF
+C506 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C507 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C508 io_analog[5] io_analog[9] 1.28fF
+C509 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
+C510 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C511 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF
+C512 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C513 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C514 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C515 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C516 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF
+C517 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/div 0.25fF
+C518 io_analog[3] ro_complete_buffered_0/ro_complete_0/a1 0.17fF
+C519 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C520 io_analog[3] io_analog[8] 1.02fF
+C521 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF
+C522 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF
+C523 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF
+C524 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C525 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.11fF
+C526 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C527 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF
+C528 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C529 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C530 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C531 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C532 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C533 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF
+C534 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
+C535 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C536 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C537 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C538 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/ref 0.17fF
+C539 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
+C540 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C541 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
+C542 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
+C543 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C544 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/div 0.03fF
+C545 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/vco 0.06fF
+C546 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C547 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/tapered_buf_3/in 0.11fF
+C548 pd_buffered_0/tapered_buf_0/in4 pd_buffered_0/tapered_buf_0/in5 29.21fF
+C549 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C550 gpio_analog[3] gpio_noesd[5] 0.96fF
+C551 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF
+C552 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF
+C553 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C554 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C555 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C556 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C557 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/div 0.03fF
+C558 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/vco 0.06fF
+C559 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF
+C560 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
+C561 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/vco 0.64fF
+C562 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF
+C563 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in5 2.89fF
+C564 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/nor_1/B 0.30fF
+C565 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/Z1 0.04fF
+C566 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C567 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF
+C568 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/pd_0/DOWN 0.19fF
+C569 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C570 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C571 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in2 1.27fF
+C572 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
+C573 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF
+C574 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C575 io_analog[8] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF
+C576 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in4 4.78fF
+C577 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/vco 0.64fF
+C578 io_analog[0] gpio_analog[3] 3.87fF
+C579 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C580 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C581 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/div 0.65fF
+C582 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
+C583 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C584 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
+C585 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF
+C586 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C587 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C588 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF
+C589 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF
+C590 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF
+C591 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C592 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.29fF
+C593 gpio_noesd[10] io_analog[9] 3.45fF
+C594 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/Out 0.11fF
+C595 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C596 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C597 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/div 0.65fF
+C598 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z4 0.00fF
+C599 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C600 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.01fF
+C601 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C602 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C603 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in2 1.27fF
+C604 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C605 gpio_noesd[10] gpio_noesd[7] 0.73fF
+C606 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/DOWN 0.02fF
+C607 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/R 0.30fF
+C608 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C609 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
+C610 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.26fF
+C611 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF
+C612 ro_divider_buffered_0/tapered_buf_0/in3 ro_divider_buffered_0/tapered_buf_0/in2 1.27fF
+C613 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF
+C614 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C615 gpio_noesd[8] io_analog[9] 0.91fF
+C616 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/A 0.15fF
+C617 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF
+C618 ro_divider_buffered_0/tapered_buf_2/in2 ro_divider_buffered_0/tapered_buf_2/in1 0.37fF
+C619 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C620 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C621 io_analog[8] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C622 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C623 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF
+C624 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF
+C625 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C626 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C627 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.04fF
+C628 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/A 0.26fF
+C629 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C630 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C631 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z1 0.03fF
+C632 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C633 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C634 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C635 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C636 gpio_noesd[12] div_pd_buffered_0/pd_0/DOWN 0.33fF
+C637 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF
+C638 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C639 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C640 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C641 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C642 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/pll_full_0/div 0.19fF
+C643 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF
+C644 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C645 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C646 gpio_analog[9] io_analog[10] 1.15fF
+C647 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C648 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C649 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C650 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/pd_0/REF 26.29fF
+C651 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C652 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C653 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C654 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Z4 0.65fF
+C655 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C656 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C657 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C658 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF
+C659 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C660 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C661 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
+C662 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF
+C663 ro_divider_buffered_0/divider_0/Out io_analog[9] 1.19fF
+C664 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C665 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C666 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.20fF
+C667 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF
+C668 ashish_0/b gpio_analog[3] 0.27fF
+C669 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C670 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C671 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C672 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C673 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/and_0/OUT 0.14fF
+C674 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C675 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C676 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C677 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C678 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C679 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C680 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in2 0.84fF
+C681 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C682 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C683 io_analog[4] io_analog[7] 1.11fF
+C684 io_analog[5] io_analog[6] 21.00fF
+C685 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C686 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF
+C687 gpio_noesd[10] gpio_analog[10] 1.36fF
+C688 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF
+C689 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C690 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.25fF
+C691 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C692 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C693 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
+C694 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in3 2.89fF
+C695 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C696 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/R 0.51fF
+C697 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered1_0/pll_full_0/vco 0.26fF
+C698 pll_full_buffered2_0/tapered_buf_2/in2 pll_full_buffered2_0/tapered_buf_2/in1 0.37fF
+C699 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF
+C700 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C701 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C702 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF
+C703 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF
+C704 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF
+C705 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
+C706 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C707 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C708 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C709 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C710 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF
+C711 gpio_noesd[8] gpio_analog[10] 0.48fF
+C712 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C713 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/UP 0.61fF
+C714 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C715 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF
+C716 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C717 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C718 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C719 gpio_noesd[14] gpio_analog[7] 2.55fF
+C720 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C721 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C722 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF
+C723 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C724 gpio_noesd[12] io_analog[10] 1.57fF
+C725 io_analog[9] divider_buffered_0/divider_0/clk 0.40fF
+C726 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_buffered2_0/pll_full_0/vco 0.26fF
+C727 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C728 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C729 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C730 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C731 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C732 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_2/Z4 0.02fF
+C733 gpio_analog[3] gpio_analog[6] 1.30fF
+C734 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF
+C735 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C736 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF
+C737 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C738 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF
+C739 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF
+C740 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/nor_1/B 0.06fF
+C741 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/UP 0.61fF
+C742 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C743 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C744 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C745 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C746 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C747 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C748 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF
+C749 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF
+C750 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C751 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C752 io_analog[4] io_analog[9] 1.28fF
+C753 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C754 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF
+C755 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C756 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF
+C757 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C758 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C759 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C760 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/nor_1/A 0.03fF
+C761 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C762 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF
+C763 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
+C764 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF
+C765 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
+C766 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF
+C767 io_analog[3] ro_complete_buffered_0/ro_complete_0/a5 0.15fF
+C768 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.05fF
+C769 io_analog[3] io_analog[7] 0.92fF
+C770 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C771 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/div 4.07fF
+C772 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF
+C773 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C774 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C775 io_analog[10] gpio_noesd[13] 1.85fF
+C776 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C777 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C778 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/REF 0.02fF
+C779 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in2 1.27fF
+C780 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C781 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C782 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C783 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in2 0.84fF
+C784 divider_buffered_0/tapered_buf_1/in5 divider_buffered_0/tapered_buf_1/in1 0.22fF
+C785 gpio_noesd[12] gpio_noesd[13] 0.45fF
+C786 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF
+C787 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C788 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/nor_1/A 0.01fF
+C789 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C790 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C791 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
+C792 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C793 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C794 ashish_0/b io_analog[0] 8.93fF
+C795 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C796 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.21fF
+C797 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.11fF
+C798 pll_full_buffered2_0/tapered_buf_0/in4 pll_full_buffered2_0/tapered_buf_0/in3 4.78fF
+C799 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C800 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C801 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C802 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C803 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF
+C804 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C805 gpio_analog[8] io_analog[9] 1.10fF
+C806 div_pd_buffered_0/tapered_buf_3/in1 div_pd_buffered_0/tapered_buf_3/in5 0.22fF
+C807 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C808 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/clk 0.51fF
+C809 div_pd_buffered_0/pd_0/tspc_r_1/Z4 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C810 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C811 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/divider_0/Out 0.19fF
+C812 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/out1 0.31fF
+C813 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/tspc_0/Q 0.15fF
+C814 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C815 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/div 0.05fF
+C816 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C817 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C818 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.21fF
+C819 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C820 gpio_analog[8] gpio_noesd[7] 1.68fF
+C821 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF
+C822 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF
+C823 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C824 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C825 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in3 4.78fF
+C826 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C827 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C828 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in5 0.84fF
+C829 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C830 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/div 0.05fF
+C831 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C832 pd_buffered_0/tapered_buf_2/in1 pd_buffered_0/pd_0/UP 0.19fF
+C833 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C834 io_analog[3] io_analog[9] 1.00fF
+C835 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF
+C836 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in2 0.84fF
+C837 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF
+C838 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C839 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_0/Q 0.15fF
+C840 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C841 div_pd_buffered_0/pd_0/and_pd_0/Out1 div_pd_buffered_0/pd_0/UP 0.33fF
+C842 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF
+C843 pll_full_buffered2_0/tapered_buf_5/in pll_full_buffered2_0/tapered_buf_5/in1 0.19fF
+C844 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/and_0/B 0.29fF
+C845 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF
+C846 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C847 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C848 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C849 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C850 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C851 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF
+C852 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/tapered_buf_0/in4 29.21fF
+C853 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C854 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C855 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF
+C856 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C857 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF
+C858 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/REF 0.51fF
+C859 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.20fF
+C860 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C861 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C862 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
+C863 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/tapered_buf_1/in4 29.21fF
+C864 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C865 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C866 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
C867 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
-C868 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/nor_1/A 0.02fF
-C869 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C870 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in3 2.89fF
-C871 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C872 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C873 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C874 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C875 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Q 0.04fF
-C876 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C877 io_analog[3] ro_divider_buffered_0/ro_complete_0/a5 0.17fF
-C878 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C879 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF
-C880 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/nor_0/Z1 0.06fF
-C881 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in3 2.89fF
-C882 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C883 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF
-C884 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF
-C885 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C886 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C887 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in3 2.89fF
-C888 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C889 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/divider_0/clk 0.05fF
-C890 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C891 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C892 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C893 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C894 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF
-C895 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF
-C896 ro_complete_buffered_0/ro_complete_0/a0 io_analog[3] 0.20fF
-C897 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C898 pll_full_buffered1_0/tapered_buf_0/in pll_full_buffered1_0/tapered_buf_0/in1 0.19fF
-C899 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C900 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C901 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
-C902 gpio_noesd[7] gpio_noesd[9] 3.28fF
-C903 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/clk 0.04fF
-C904 io_clamp_high[2] io_analog[6] 0.53fF
-C905 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C906 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C907 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C908 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/a0 0.09fF
-C909 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C910 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C911 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C912 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
-C913 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF
-C914 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/pd_0/UP 0.05fF
-C915 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C916 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C917 pd_buffered_0/tapered_buf_2/in2 pd_buffered_0/tapered_buf_2/in1 0.37fF
-C918 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C919 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C920 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF
-C921 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C922 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
-C923 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/divider_0/clk 26.29fF
-C924 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C925 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C926 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C927 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in3 1.27fF
-C928 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_0/in1 0.19fF
-C929 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/A 0.35fF
-C930 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF
-C931 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF
-C932 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z1 0.01fF
-C933 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF
-C934 ro_divider_buffered_0/tapered_buf_8/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF
-C935 ro_divider_buffered_0/tapered_buf_7/in5 ro_divider_buffered_0/ro_complete_0/a3 26.29fF
-C936 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/mc2 0.15fF
-C937 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in3 2.89fF
-C938 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C939 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in5 2.89fF
-C940 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C941 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C942 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF
-C943 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.33fF
-C944 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF
-C945 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF
-C946 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in5 0.22fF
-C947 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_0/B 0.47fF
-C948 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF
-C949 divider_buffered_0/divider_0/tspc_1/Z4 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.12fF
-C950 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C951 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF
-C952 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C953 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z4 0.15fF
-C954 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.45fF
-C955 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF
-C956 pll_full_buffered2_0/tapered_buf_4/in1 pll_full_buffered2_0/tapered_buf_4/in2 0.37fF
-C957 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C958 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C959 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C960 io_analog[10] pll_full_buffered2_0/tapered_buf_3/in 0.42fF
-C961 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C962 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C963 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF
-C964 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C965 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C966 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
-C967 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
-C968 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF
-C969 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C970 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C971 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/clk 0.60fF
-C972 ro_divider_buffered_0/tapered_buf_2/in4 ro_divider_buffered_0/tapered_buf_2/in5 29.21fF
-C973 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF
-C974 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z2 1.07fF
-C975 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C976 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF
-C977 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in5 2.89fF
-C978 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in5 0.22fF
-C979 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C980 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C981 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C982 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C983 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/A 0.26fF
-C984 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF
-C985 gpio_noesd[7] gpio_noesd[12] 0.68fF
-C986 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in3 2.89fF
-C987 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C988 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
-C989 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C990 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF
-C991 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF
-C992 pll_full_buffered2_0/tapered_buf_5/in4 pll_full_buffered2_0/tapered_buf_5/in5 29.21fF
-C993 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C994 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C995 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C996 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/divider_0/clk 0.05fF
-C997 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C998 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C999 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/Z2 0.14fF
-C1000 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF
-C1001 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C1002 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF
-C1003 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/Out 0.11fF
-C1004 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF
-C1005 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C1006 ro_complete_buffered_0/ro_complete_0/a1 io_analog[7] 0.23fF
-C1007 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
-C1008 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
-C1009 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF
-C1010 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF
-C1011 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in5 0.22fF
-C1012 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C1013 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C1014 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1015 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF
-C1016 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_0/B 0.06fF
-C1017 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
-C1018 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF
-C1019 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF
-C1020 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z3 0.09fF
-C1021 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF
-C1022 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C1023 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF
-C1024 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1025 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF
-C1026 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z2 0.16fF
-C1027 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF
-C1028 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1029 ashish_0/b ashish_0/vop 8.93fF
-C1030 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
-C1031 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1032 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF
-C1033 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C1034 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C1035 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1036 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
-C1037 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in2 0.37fF
-C1038 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/out1 0.06fF
-C1039 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF
-C1040 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C1041 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C1042 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1043 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C1044 io_analog[8] io_analog[4] 1.24fF
-C1045 io_analog[7] io_analog[5] 1.11fF
-C1046 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.01fF
-C1047 io_analog[10] div_pd_buffered_0/tapered_buf_1/in1 0.19fF
-C1048 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C1049 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C1050 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
-C1051 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
-C1052 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF
-C1053 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF
-C1054 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C1055 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF
-C1056 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C1057 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C1058 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF
-C1059 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF
-C1060 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C1061 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1062 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1063 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF
-C1064 ro_divider_buffered_0/tapered_buf_0/in ro_divider_buffered_0/tapered_buf_0/in1 0.19fF
-C1065 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in5 0.22fF
-C1066 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF
-C1067 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1068 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF
-C1069 ro_divider_buffered_0/divider_0/and_0/Z1 ro_divider_buffered_0/divider_0/and_0/OUT 0.04fF
-C1070 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1071 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1072 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1073 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF
-C1074 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
-C1075 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.01fF
-C1076 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in5 0.22fF
-C1077 div_pd_buffered_0/pd_0/DOWN gpio_noesd[12] 0.33fF
-C1078 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in3 2.89fF
-C1079 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C1080 pll_full_buffered1_0/tapered_buf_0/in1 pll_full_buffered1_0/tapered_buf_0/in2 0.37fF
-C1081 io_analog[8] ro_divider_buffered_0/tapered_buf_4/in1 0.19fF
-C1082 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/clk 0.26fF
-C1083 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C1084 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C1085 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1086 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF
-C1087 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C1088 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/Out 0.05fF
-C1089 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF
-C1090 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1091 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1092 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1093 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF
-C1094 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1095 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/in1 0.19fF
-C1096 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1097 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C1098 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF
-C1099 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C1100 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C1101 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1102 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.14fF
-C1103 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF
-C1104 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1105 divider_buffered_0/tapered_buf_2/in4 divider_buffered_0/tapered_buf_2/in5 29.21fF
-C1106 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF
-C1107 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF
-C1108 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in2 1.27fF
-C1109 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
-C1110 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF
-C1111 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/clk 0.26fF
-C1112 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1113 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1114 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1115 io_analog[3] io_analog[4] 0.88fF
-C1116 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C1117 ro_divider_buffered_0/tapered_buf_5/in2 ro_divider_buffered_0/tapered_buf_5/in5 0.84fF
-C1118 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in4 4.78fF
-C1119 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
-C1120 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF
-C1121 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF
-C1122 gpio_noesd[8] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.21fF
-C1123 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1124 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1125 pd_buffered_0/pd_0/UP pd_buffered_0/tapered_buf_2/in1 0.19fF
-C1126 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF
-C1127 io_analog[10] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.36fF
-C1128 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF
-C1129 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in1 0.37fF
-C1130 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF
-C1131 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
-C1132 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1133 pd_buffered_0/tapered_buf_0/in3 pd_buffered_0/tapered_buf_0/in4 4.78fF
-C1134 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF
-C1135 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z3 0.65fF
-C1136 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF
-C1137 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in5 2.89fF
-C1138 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C1139 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C1140 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C1141 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C1142 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF
-C1143 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_1/B 0.35fF
-C1144 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.08fF
-C1145 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF
-C1146 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.12fF
-C1147 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in3 1.27fF
-C1148 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.15fF
-C1149 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in2 0.37fF
-C1150 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/down 0.32fF
-C1151 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1152 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C1153 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C1154 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
-C1155 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C1156 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/clk 0.05fF
-C1157 ashish_0/vop ashish_0/von 7.97fF
-C1158 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
-C1159 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C1160 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C1161 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1162 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1163 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF
-C1164 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1165 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF
-C1166 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1167 gpio_noesd[13] gpio_noesd[12] 0.45fF
-C1168 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF
-C1169 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in5 2.89fF
-C1170 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
-C1171 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C1172 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in1 0.37fF
-C1173 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
-C1174 io_analog[4] ro_divider_buffered_0/tapered_buf_8/in1 0.19fF
-C1175 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in3 1.27fF
-C1176 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1177 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1178 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
-C1179 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF
-C1180 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_6/in5 29.21fF
-C1181 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1182 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1183 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C1184 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1185 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF
-C1186 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C1187 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF
-C1188 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C1189 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF
-C1190 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C1191 gpio_analog[8] cp_buffered_0/tapered_buf_0/in1 0.19fF
-C1192 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C1193 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1194 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C1195 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.19fF
-C1196 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1197 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C1198 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C1199 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF
-C1200 io_analog[10] gpio_analog[8] 1.48fF
-C1201 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF
-C1202 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF
-C1203 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in3 4.78fF
-C1204 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF
-C1205 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C1206 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1207 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1208 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 3.73fF
-C1209 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1210 pd_buffered_0/tapered_buf_1/in4 pd_buffered_0/tapered_buf_1/in3 4.78fF
-C1211 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1212 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C1213 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1214 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1215 gpio_noesd[7] gpio_analog[9] 1.96fF
-C1216 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1217 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
-C1218 io_analog[10] gpio_analog[7] 2.78fF
-C1219 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C1220 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/A 0.04fF
-C1221 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1222 ro_divider_buffered_0/tapered_buf_2/in1 ro_divider_buffered_0/tapered_buf_2/in 0.19fF
-C1223 divider_buffered_0/tapered_buf_0/in4 divider_buffered_0/tapered_buf_0/in3 4.78fF
-C1224 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C1225 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C1226 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C1227 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF
-C1228 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF
-C1229 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in4 4.78fF
-C1230 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF
-C1231 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
-C1232 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1233 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/a4 0.09fF
-C1234 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/a5 0.09fF
-C1235 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1236 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1237 io_analog[9] pll_full_buffered2_0/tapered_buf_3/in 0.61fF
-C1238 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1239 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1240 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF
-C1241 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1242 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C1243 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF
-C1244 ro_complete_buffered_0/ro_complete_0/a4 io_analog[3] 0.17fF
-C1245 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1246 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1247 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF
-C1248 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1249 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF
-C1250 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.02fF
-C1251 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1252 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
-C1253 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in5 2.89fF
-C1254 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF
-C1255 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C1256 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.00fF
-C1257 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF
-C1258 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C1259 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in2 1.27fF
-C1260 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/R 0.02fF
-C1261 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DIV 0.65fF
-C1262 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1263 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF
-C1264 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C1265 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1266 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/divider_0/clk 0.10fF
-C1267 div_pd_buffered_0/tapered_buf_2/in2 div_pd_buffered_0/tapered_buf_2/in3 1.27fF
-C1268 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1269 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C1270 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1271 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in5 0.84fF
-C1272 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1273 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in5 2.89fF
-C1274 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C1275 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1276 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in2 0.37fF
-C1277 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in3 1.27fF
-C1278 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1279 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1280 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF
-C1281 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1282 gpio_noesd[7] io_analog[10] 5.73fF
-C1283 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF
-C1284 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1285 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out 26.29fF
-C1286 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
-C1287 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF
-C1288 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF
-C1289 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C1290 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.43fF
-C1291 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in1 0.22fF
-C1292 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
-C1293 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C1294 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF
-C1295 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_0/B 0.15fF
-C1296 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF
-C1297 io_analog[8] io_analog[5] 1.24fF
-C1298 io_analog[7] io_analog[6] 1.12fF
-C1299 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF
-C1300 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C1301 ro_divider_buffered_0/tapered_buf_5/in4 ro_divider_buffered_0/tapered_buf_5/in5 29.21fF
-C1302 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C1303 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_2/in1 0.37fF
-C1304 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C1305 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/and_0/B 0.78fF
-C1306 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF
-C1307 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C1308 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF
-C1309 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
-C1310 ro_divider_buffered_0/divider_0/Out ro_divider_buffered_0/divider_0/mc2 1.14fF
-C1311 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
-C1312 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1313 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF
-C1314 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1315 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF
-C1316 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF
-C1317 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1318 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1319 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
-C1320 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1321 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C1322 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1323 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1324 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
-C1325 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1326 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/tapered_buf_1/in4 29.21fF
-C1327 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C1328 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1329 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_0/Z1 0.18fF
-C1330 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1331 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C1332 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 0.22fF
-C1333 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C1334 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C1335 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF
-C1336 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in 0.19fF
-C1337 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z2 0.01fF
-C1338 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
-C1339 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF
-C1340 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1341 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/a5 2.39fF
-C1342 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1343 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in3 1.27fF
-C1344 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF
-C1345 pll_full_buffered2_0/tapered_buf_4/in3 pll_full_buffered2_0/tapered_buf_4/in4 4.78fF
-C1346 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in1 0.22fF
-C1347 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C1348 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1349 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1350 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1351 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1352 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF
-C1353 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1354 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1355 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1356 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/clk 0.29fF
-C1357 ro_complete_buffered_0/ro_complete_0/a1 io_analog[3] 0.17fF
-C1358 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/REF 0.04fF
-C1359 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF
-C1360 filter_buffered_0/tapered_buf_1/in1 filter_buffered_0/tapered_buf_1/in2 0.37fF
-C1361 divider_buffered_0/tapered_buf_0/in4 divider_buffered_0/tapered_buf_0/in5 29.21fF
-C1362 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1363 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1364 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/clk 0.45fF
-C1365 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF
-C1366 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1367 io_analog[6] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1368 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/nor_0/B 0.35fF
-C1369 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF
-C1370 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in2 0.37fF
-C1371 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_4/in5 0.84fF
-C1372 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1373 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C1374 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1375 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1376 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1377 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF
-C1378 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF
-C1379 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/cp_0/upbar 26.29fF
-C1380 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF
-C1381 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C1382 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/Out 0.04fF
-C1383 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1384 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/divider_0/clk 1.27fF
-C1385 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1386 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C1387 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1388 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF
-C1389 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF
-C1390 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
-C1391 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF
-C1392 gpio_noesd[9] cp_buffered_0/cp_0/down 0.38fF
-C1393 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in2 0.37fF
-C1394 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C1395 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1396 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C1397 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1398 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1399 io_analog[3] io_analog[5] 0.93fF
-C1400 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1401 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
-C1402 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF
-C1403 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1404 io_analog[9] pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.53fF
-C1405 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 29.21fF
-C1406 io_analog[10] pll_full_buffered2_0/tapered_buf_0/in1 0.19fF
-C1407 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF
-C1408 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1409 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1410 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1411 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
-C1412 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C1413 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1414 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1415 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1416 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C1417 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1418 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF
-C1419 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
-C1420 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF
-C1421 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z2 0.15fF
-C1422 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1423 div_pd_buffered_0/divider_0/and_0/B div_pd_buffered_0/divider_0/and_0/Z1 0.07fF
-C1424 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1425 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF
-C1426 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1427 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in3 4.78fF
-C1428 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
-C1429 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1430 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF
-C1431 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1432 gpio_noesd[10] pd_buffered_0/pd_0/DOWN 0.54fF
-C1433 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1434 io_analog[10] pd_buffered_0/tapered_buf_3/in1 0.19fF
-C1435 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C1436 io_analog[3] ro_divider_buffered_0/tapered_buf_3/in1 0.19fF
-C1437 io_analog[10] pll_full_buffered1_0/pll_full_0/vco 0.56fF
-C1438 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z3 0.38fF
-C1439 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C1440 pll_full_buffered2_0/tapered_buf_2/in1 pll_full_buffered2_0/tapered_buf_2/in2 0.37fF
-C1441 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/nor_0/B 0.47fF
-C1442 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/nor_1/Z1 0.18fF
-C1443 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1444 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF
-C1445 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C1446 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in2 0.84fF
-C1447 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1448 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1449 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1450 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF
-C1451 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.19fF
-C1452 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1453 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF
-C1454 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C1455 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
-C1456 gpio_noesd[8] gpio_noesd[13] 0.55fF
-C1457 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.33fF
-C1458 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1459 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1460 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF
-C1461 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
-C1462 pll_full_buffered1_0/tapered_buf_0/in2 pll_full_buffered1_0/tapered_buf_0/in5 0.84fF
-C1463 pll_full_buffered1_0/tapered_buf_0/in3 pll_full_buffered1_0/tapered_buf_0/in4 4.78fF
-C1464 io_analog[10] gpio_noesd[13] 1.85fF
-C1465 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z2 0.11fF
-C1466 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF
-C1467 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1468 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1469 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in3 1.27fF
-C1470 io_analog[9] gpio_analog[8] 1.10fF
-C1471 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.35fF
-C1472 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF
-C1473 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_1/Z3 0.45fF
-C1474 ro_divider_buffered_0/divider_0/Out ro_divider_buffered_0/tapered_buf_0/in5 26.29fF
-C1475 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in5 2.89fF
-C1476 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1477 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1478 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
-C1479 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
-C1480 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1481 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1482 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1483 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C1484 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C1485 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1486 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF
-C1487 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.04fF
-C1488 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF
-C1489 io_analog[9] gpio_analog[7] 1.40fF
-C1490 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C1491 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1492 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/A 0.16fF
-C1493 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C1494 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1495 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1496 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C1497 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1498 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1499 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C1500 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF
-C1501 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C1502 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF
-C1503 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in4 29.21fF
-C1504 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
-C1505 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF
-C1506 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF
-C1507 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in2 0.37fF
-C1508 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C1509 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1510 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1511 div_pd_buffered_0/tapered_buf_2/in5 div_pd_buffered_0/tapered_buf_2/in2 0.84fF
-C1512 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
-C1513 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1514 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1515 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1516 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1517 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
-C1518 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
-C1519 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1520 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF
-C1521 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1522 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1523 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C1524 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
-C1525 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF
-C1526 gpio_noesd[7] gpio_analog[10] 0.77fF
-C1527 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/B 0.01fF
-C1528 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C1529 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
-C1530 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1531 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF
-C1532 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Q 0.04fF
-C1533 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z2 0.30fF
-C1534 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
-C1535 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF
-C1536 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1537 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_5/in5 0.84fF
-C1538 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in4 4.78fF
-C1539 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in4 29.21fF
-C1540 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF
-C1541 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C1542 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1543 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C1544 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1545 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in5 2.89fF
-C1546 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1547 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C1548 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF
-C1549 div_pd_buffered_0/tapered_buf_4/in5 gpio_noesd[13] 26.29fF
-C1550 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1551 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF
-C1552 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
-C1553 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF
-C1554 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1555 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1556 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF
-C1557 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF
-C1558 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
-C1559 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF
-C1560 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C1561 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1562 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C1563 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF
-C1564 pd_buffered_0/tapered_buf_1/in2 pd_buffered_0/tapered_buf_1/in3 1.27fF
-C1565 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1566 gpio_noesd[7] io_analog[9] 1.42fF
-C1567 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Q 0.05fF
-C1568 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1569 div_pd_buffered_0/tapered_buf_3/in4 div_pd_buffered_0/tapered_buf_3/in5 29.21fF
-C1570 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF
-C1571 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1572 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1573 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C1574 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
-C1575 ro_complete_buffered_0/ro_complete_0/a2 io_analog[4] 0.37fF
-C1576 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF
-C1577 io_analog[8] io_analog[6] 1.24fF
-C1578 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C1579 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C1580 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF
-C1581 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
-C1582 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
-C1583 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF
-C1584 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF
-C1585 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
-C1586 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF
-C1587 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1588 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1589 pll_full_buffered2_0/tapered_buf_0/in1 pll_full_buffered2_0/tapered_buf_0/in2 0.37fF
-C1590 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1591 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1592 ashish_0/b ashish_0/von 4.11fF
-C1593 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1594 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C1595 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1596 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C1597 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF
-C1598 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF
-C1599 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1600 div_pd_buffered_0/tapered_buf_0/in5 div_pd_buffered_0/tapered_buf_0/in1 0.22fF
-C1601 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF
-C1602 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1603 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF
-C1604 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF
-C1605 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C1606 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF
-C1607 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C1608 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF
-C1609 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF
-C1610 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/nor_1/B 0.22fF
-C1611 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/Out 0.01fF
-C1612 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1613 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1614 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1615 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1616 ro_complete_buffered_0/ro_complete_0/a5 io_analog[3] 0.15fF
-C1617 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/REF 0.12fF
-C1618 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1619 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF
-C1620 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in2 0.37fF
-C1621 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1622 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/A 0.80fF
-C1623 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF
-C1624 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF
-C1625 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C1626 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C1627 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1628 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C1629 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1630 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1631 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C1632 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF
-C1633 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF
-C1634 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF
-C1635 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
-C1636 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF
-C1637 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF
-C1638 gpio_noesd[7] gpio_noesd[11] 0.79fF
-C1639 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
-C1640 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF
-C1641 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF
-C1642 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF
-C1643 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1644 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF
-C1645 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.08fF
-C1646 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in1 0.37fF
-C1647 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1648 pll_full_buffered1_0/tapered_buf_0/in4 pll_full_buffered1_0/tapered_buf_0/in5 29.21fF
-C1649 io_analog[3] io_analog[6] 1.03fF
-C1650 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF
-C1651 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF
-C1652 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF
-C1653 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z2 0.01fF
-C1654 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF
-C1655 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C1656 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C1657 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1658 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1659 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a0 26.29fF
-C1660 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF
-C1661 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1662 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF
-C1663 div_pd_buffered_0/tapered_buf_2/in4 div_pd_buffered_0/tapered_buf_2/in5 29.21fF
-C1664 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1665 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C1666 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1667 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1668 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
-C1669 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1670 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1671 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
-C1672 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF
-C1673 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C1674 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1675 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
-C1676 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1677 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
-C1678 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
-C1679 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/tspc_0/Z4 0.00fF
-C1680 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF
-C1681 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
-C1682 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1683 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C1684 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF
-C1685 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF
-C1686 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/A 0.01fF
-C1687 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in3 1.27fF
-C1688 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF
-C1689 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF
-C1690 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C1691 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C1692 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF
-C1693 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
-C1694 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1695 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1696 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1697 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
-C1698 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C1699 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF
-C1700 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1701 div_pd_buffered_0/tapered_buf_1/in4 div_pd_buffered_0/tapered_buf_1/in3 4.78fF
-C1702 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF
-C1703 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF
-C1704 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1705 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF
-C1706 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1707 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
-C1708 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C1709 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1710 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1711 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in2 0.37fF
-C1712 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
-C1713 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in1 0.22fF
-C1714 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
-C1715 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF
-C1716 io_analog[5] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF
-C1717 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1718 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1719 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF
-C1720 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_5/in5 29.21fF
-C1721 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF
-C1722 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1723 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C1724 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C1725 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1726 divider_buffered_0/divider_0/tspc_0/Z4 divider_buffered_0/divider_0/tspc_0/Z1 0.00fF
-C1727 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
-C1728 ashish_0/vop ashish_0/a 4.11fF
-C1729 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF
-C1730 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C1731 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF
-C1732 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1733 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1734 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF
-C1735 io_analog[9] gpio_noesd[13] 2.15fF
-C1736 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z2 0.23fF
-C1737 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C1738 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C1739 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/Out 0.04fF
-C1740 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C1741 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF
-C1742 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF
-C1743 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1744 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
-C1745 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1746 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1747 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1748 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1749 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1750 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
-C1751 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.78fF
-C1752 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C1753 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C1754 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C1755 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C1756 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
-C1757 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF
-C1758 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF
-C1759 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF
-C1760 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF
-C1761 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF
-C1762 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1763 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF
-C1764 div_pd_buffered_0/pd_0/UP div_pd_buffered_0/tapered_buf_0/in1 0.19fF
-C1765 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF
-C1766 io_clamp_low[0] io_analog[4] 0.53fF
-C1767 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF
-C1768 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.00fF
-C1769 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1770 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1771 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in3 1.27fF
-C1772 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF
-C1773 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1774 divider_buffered_0/tapered_buf_0/in1 divider_buffered_0/tapered_buf_0/in5 0.22fF
-C1775 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1776 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF
-C1777 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
-C1778 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF
-C1779 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF
-C1780 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
-C1781 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C1782 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in4 4.78fF
-C1783 ro_divider_buffered_0/divider_0/tspc_0/Q ro_divider_buffered_0/divider_0/tspc_1/Z2 0.14fF
-C1784 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF
-C1785 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/Out 0.15fF
-C1786 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
-C1787 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C1788 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1789 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1790 pd_buffered_0/pd_0/UP pd_buffered_0/pd_0/R 0.45fF
-C1791 div_pd_buffered_0/tapered_buf_3/in5 div_pd_buffered_0/tapered_buf_3/in1 0.22fF
-C1792 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
-C1793 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C1794 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1795 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.33fF
-C1796 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1797 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF
-C1798 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1799 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF
-C1800 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in3 1.27fF
-C1801 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF
-C1802 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1803 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1804 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
-C1805 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF
-C1806 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF
-C1807 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1808 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1809 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in5 0.84fF
-C1810 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1811 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C1812 ro_divider_buffered_0/tapered_buf_1/in ro_divider_buffered_0/tapered_buf_1/in1 0.19fF
-C1813 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/nor_0/B 0.22fF
-C1814 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1815 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF
-C1816 pll_full_buffered2_0/tapered_buf_5/in gpio_noesd[7] 0.54fF
-C1817 pll_full_buffered2_0/tapered_buf_5/in1 pll_full_buffered2_0/tapered_buf_5/in5 0.22fF
-C1818 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1819 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1820 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1821 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1822 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C1823 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1824 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.03fF
-C1825 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1826 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1827 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_1/in5 26.29fF
-C1828 ro_complete_buffered_0/tapered_buf_4/in1 io_analog[6] 0.19fF
-C1829 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
-C1830 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF
-C1831 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF
-C1832 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
-C1833 ro_complete_buffered_0/ro_complete_0/a2 io_analog[5] 0.25fF
-C1834 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C1835 io_analog[8] io_analog[7] 1.38fF
-C1836 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
-C1837 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF
-C1838 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C1839 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF
-C1840 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF
-C1841 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C1842 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C1843 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF
-C1844 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF
-C1845 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1846 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1847 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.40fF
-C1848 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF
-C1849 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/UP 0.45fF
-C1850 io_clamp_low[1] io_analog[5] 0.53fF
-C1851 ro_divider_buffered_0/tapered_buf_5/in5 ro_divider_buffered_0/ro_complete_0/a1 26.29fF
-C1852 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
-C1853 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
-C1854 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1855 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1856 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1857 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
-C1858 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1859 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1860 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
-C1861 gpio_analog[10] div_pd_buffered_0/tapered_buf_3/in1 0.19fF
-C1862 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in1 0.37fF
-C1863 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A 0.01fF
-C1864 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.05fF
-C1865 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF
-C1866 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
-C1867 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1868 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF
-C1869 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF
-C1870 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF
-C1871 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
-C1872 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1873 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C1874 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C1875 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
-C1876 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.25fF
-C1877 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C1878 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Z4 0.65fF
-C1879 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF
-C1880 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF
-C1881 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF
-C1882 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
-C1883 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1884 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C1885 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1886 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/div 0.51fF
-C1887 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1888 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
-C1889 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1890 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C1891 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
-C1892 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
-C1893 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1894 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF
-C1895 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1896 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C1897 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1898 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1899 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1900 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
-C1901 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF
-C1902 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF
-C1903 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C1904 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF
-C1905 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
-C1906 pd_buffered_0/pd_0/REF pd_buffered_0/tapered_buf_3/in5 26.29fF
-C1907 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
-C1908 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1909 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
-C1910 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
-C1911 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/and_0/OUT 0.01fF
-C1912 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1913 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C1914 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF
-C1915 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C1916 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF
-C1917 ro_complete_buffered_0/tapered_buf_6/in1 io_analog[4] 0.19fF
-C1918 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF
-C1919 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1920 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
-C1921 divider_buffered_0/tapered_buf_2/in2 divider_buffered_0/tapered_buf_2/in3 1.27fF
-C1922 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1923 io_analog[3] io_analog[7] 0.92fF
-C1924 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
-C1925 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF
-C1926 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF
-C1927 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF
-C1928 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF
-C1929 pd_buffered_0/tapered_buf_0/in5 gpio_noesd[11] 26.29fF
-C1930 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C1931 io_clamp_low[2] io_analog[6] 0.53fF
-C1932 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C1933 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF
-C1934 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in1 0.37fF
-C1935 divider_buffered_0/divider_0/tspc_0/Q divider_buffered_0/divider_0/nor_1/B 0.22fF
-C1936 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/pll_full_0/cp_0/upbar 0.05fF
-C1937 io_analog[9] pll_full_buffered2_0/tapered_buf_1/in1 0.19fF
-C1938 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
-C1939 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1940 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1941 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C1942 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.05fF
-C1943 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1944 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C1945 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1946 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF
-C1947 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
-C1948 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
-C1949 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
-C1950 filter_buffered_0/tapered_buf_1/in1 gpio_analog[17] 0.19fF
-C1951 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF
-C1952 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF
-C1953 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF
-C1954 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF
-C1955 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF
-C1956 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF
-C1957 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.14fF
-C1958 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C1959 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1960 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1961 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF
-C1962 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF
-C1963 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/and_0/B 0.29fF
-C1964 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in4 4.78fF
-C1965 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF
-C1966 gpio_analog[9] gpio_noesd[9] 1.46fF
-C1967 ashish_0/cm ashish_0/vop 3.87fF
-C1968 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C1969 gpio_noesd[8] gpio_noesd[10] 0.51fF
-C1970 pll_full_buffered2_0/tapered_buf_0/in2 pll_full_buffered2_0/tapered_buf_0/in5 0.84fF
-C1971 pll_full_buffered2_0/tapered_buf_0/in3 pll_full_buffered2_0/tapered_buf_0/in4 4.78fF
-C1972 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C1973 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1974 io_analog[10] gpio_noesd[10] 1.21fF
-C1975 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF
-C1976 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1977 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1978 ro_complete_buffered_0/ro_complete_0/a0 io_analog[4] 0.33fF
-C1979 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF
-C1980 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
-C1981 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF
-C1982 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1983 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1984 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C1985 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
-C1986 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
-C1987 gpio_analog[9] pd_buffered_0/tapered_buf_1/in1 0.19fF
-C1988 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF
-C1989 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/Out 0.11fF
-C1990 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/DIV 0.17fF
-C1991 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C1992 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C1993 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C1994 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C1995 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF
-C1996 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C1997 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
-C1998 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.05fF
-C1999 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/REF 0.19fF
-C2000 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_1/A 1.21fF
-C2001 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C2002 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in5 2.89fF
-C2003 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C2004 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C2005 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF
-C2006 pll_full_buffered1_0/tapered_buf_1/in3 pll_full_buffered1_0/tapered_buf_1/in4 4.78fF
-C2007 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF
-C2008 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C2009 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C2010 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
-C2011 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF
-C2012 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C2013 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C2014 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
-C2015 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
-C2016 ro_divider_buffered_0/tapered_buf_1/in1 ro_divider_buffered_0/tapered_buf_1/in2 0.37fF
-C2017 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
-C2018 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/nor_0/Z1 0.78fF
-C2019 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
-C2020 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C2021 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF
-C2022 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF
-C2023 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.38fF
-C2024 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.00fF
-C2025 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C2026 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
-C2027 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_1/B 0.51fF
-C2028 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C2029 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C2030 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF
-C2031 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C2032 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C2033 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C2034 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C2035 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/Out 0.19fF
-C2036 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF
-C2037 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C2038 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C2039 ro_divider_buffered_0/tapered_buf_2/in3 ro_divider_buffered_0/tapered_buf_2/in2 1.27fF
-C2040 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF
-C2041 gpio_noesd[8] gpio_noesd[9] 1.97fF
-C2042 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in1 0.37fF
-C2043 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/nor_1/B 0.38fF
-C2044 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C2045 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C2046 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C2047 io_analog[10] gpio_noesd[9] 1.63fF
-C2048 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z3 0.06fF
-C2049 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C2050 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
-C2051 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.11fF
-C2052 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF
-C2053 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF
-C2054 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
-C2055 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
-C2056 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
-C2057 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C2058 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C2059 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z1 0.06fF
-C2060 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C2061 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_buffered1_0/pll_full_0/vco 1.58fF
-C2062 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF
-C2063 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C2064 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF
-C2065 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# 0.19fF
-C2066 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
-C2067 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Q 0.51fF
-C2068 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C2069 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C2070 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C2071 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF
-C2072 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
-C2073 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C2074 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in1 0.37fF
-C2075 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 0.01fF
-C2076 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF
-C2077 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF
-C2078 ro_divider_buffered_0/divider_0/and_0/B ro_divider_buffered_0/divider_0/mc2 0.20fF
-C2079 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C2080 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.02fF
-C2081 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/div 0.02fF
-C2082 ro_complete_buffered_0/tapered_buf_3/in1 io_analog[7] 0.19fF
-C2083 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.65fF
-C2084 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C2085 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in2 0.84fF
-C2086 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.11fF
-C2087 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF
-C2088 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C2089 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C2090 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C2091 div_pd_buffered_0/pd_0/and_pd_0/Z1 div_pd_buffered_0/pd_0/UP 0.06fF
-C2092 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.35fF
-C2093 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C2094 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF
-C2095 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C2096 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
-C2097 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF
-C2098 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in5 29.21fF
-C2099 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C2100 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C2101 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C2102 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF
-C2103 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF
-C2104 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF
-C2105 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/R 0.33fF
-C2106 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C2107 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C2108 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C2109 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C2110 ro_complete_buffered_0/ro_complete_0/a2 io_analog[6] 0.25fF
-C2111 div_pd_buffered_0/tapered_buf_1/in5 div_pd_buffered_0/pd_0/REF 26.29fF
-C2112 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF
-C2113 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF
-C2114 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C2115 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C2116 gpio_noesd[8] gpio_noesd[12] 0.46fF
-C2117 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.04fF
-C2118 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
-C2119 io_analog[10] gpio_noesd[12] 1.57fF
-C2120 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C2121 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C2122 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_2/in4 29.21fF
-C2123 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in2 0.37fF
-C2124 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C2125 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C2126 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C2127 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C2128 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
-C2129 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C2130 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF
-C2131 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C2132 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF
-C2133 pll_full_buffered1_0/pll_full_0/div pll_full_buffered1_0/pll_full_0/vco 2.26fF
-C2134 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
-C2135 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/UP 0.03fF
-C2136 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF
-C2137 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF
-C2138 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF
-C2139 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C2140 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C868 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C869 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in5 2.89fF
+C870 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C871 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C872 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z2 1.07fF
+C873 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C874 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/pll_full_0/div 0.45fF
+C875 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in4 4.78fF
+C876 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C877 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C878 pll_full_buffered2_0/tapered_buf_3/in io_analog[9] 0.61fF
+C879 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/clk 0.60fF
+C880 gpio_analog[9] gpio_noesd[8] 1.10fF
+C881 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C882 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C883 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/R 0.27fF
+C884 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/UP 0.05fF
+C885 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C886 io_analog[7] ro_divider_buffered_0/ro_complete_0/a0 0.33fF
+C887 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C888 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C889 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C890 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
+C891 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C892 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C893 pll_full_buffered1_0/tapered_buf_1/in5 pll_full_buffered1_0/tapered_buf_1/in3 2.89fF
+C894 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/R 0.01fF
+C895 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C896 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
+C897 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in2 1.27fF
+C898 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C899 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C900 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C901 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C902 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C903 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C904 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C905 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C906 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.01fF
+C907 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/R 0.27fF
+C908 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in5 2.89fF
+C909 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C910 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 29.21fF
+C911 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C912 ro_divider_buffered_0/tapered_buf_2/in1 gpio_analog[5] 0.19fF
+C913 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C914 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C915 cp_buffered_0/tapered_buf_2/in5 cp_buffered_0/tapered_buf_2/in1 0.22fF
+C916 io_analog[10] div_pd_buffered_0/divider_0/mc2 0.64fF
+C917 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C918 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C919 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in1 0.22fF
+C920 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C921 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C922 div_pd_buffered_0/divider_0/tspc_0/Z1 div_pd_buffered_0/divider_0/tspc_0/Z4 0.00fF
+C923 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C924 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/Out 0.42fF
+C925 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in5 0.22fF
+C926 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/ro_complete_0/a0 26.29fF
+C927 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/in1 0.22fF
+C928 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C929 gpio_noesd[10] io_analog[10] 1.21fF
+C930 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in3 1.27fF
+C931 io_clamp_high[1] io_analog[5] 0.53fF
+C932 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C933 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C934 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/div 0.17fF
+C935 divider_buffered_0/tapered_buf_0/in2 divider_buffered_0/tapered_buf_0/in3 1.27fF
+C936 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF
+C937 pd_buffered_0/tapered_buf_2/in3 pd_buffered_0/tapered_buf_2/in4 4.78fF
+C938 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C939 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C940 divider_buffered_0/tapered_buf_1/in1 divider_buffered_0/divider_0/Out 0.20fF
+C941 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C942 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C943 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C944 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Q 0.51fF
+C945 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C946 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C947 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C948 gpio_noesd[8] io_analog[10] 3.39fF
+C949 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C950 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C951 div_pd_buffered_0/divider_0/tspc_0/Z2 div_pd_buffered_0/divider_0/tspc_0/Z3 0.16fF
+C952 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/clk 0.12fF
+C953 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.12fF
+C954 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 1.07fF
+C955 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in3 1.27fF
+C956 io_analog[4] io_analog[6] 1.25fF
+C957 gpio_noesd[12] gpio_noesd[8] 0.46fF
+C958 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/div 0.17fF
+C959 pll_full_buffered2_0/tapered_buf_3/in3 pll_full_buffered2_0/tapered_buf_3/in4 4.78fF
+C960 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.12fF
+C961 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C962 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/nor_1/B 1.21fF
+C963 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.01fF
+C964 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C965 gpio_noesd[11] io_analog[9] 3.74fF
+C966 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C967 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C968 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF
+C969 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_0/Z3 0.11fF
+C970 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C971 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C972 div_pd_buffered_0/pd_0/tspc_r_0/Z2 div_pd_buffered_0/pd_0/R 0.21fF
+C973 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/vco 0.45fF
+C974 pll_full_buffered2_0/pll_full_0/cp_0/upbar io_analog[9] 0.53fF
+C975 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/Z1 0.36fF
+C976 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C977 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/out1 0.06fF
+C978 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF
+C979 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/nor_1/B 0.30fF
+C980 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.11fF
+C981 gpio_noesd[11] gpio_noesd[7] 0.79fF
+C982 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.12fF
+C983 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C984 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/prescaler_0/Out 0.28fF
+C985 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in5 0.22fF
+C986 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C987 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C988 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/vco 0.45fF
+C989 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in5 2.89fF
+C990 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C991 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/nor_1/B 1.21fF
+C992 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C993 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C994 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C995 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C996 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C997 div_pd_buffered_0/tapered_buf_0/in1 div_pd_buffered_0/tapered_buf_0/in2 0.37fF
+C998 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in5 0.22fF
+C999 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/ro_complete_0/a1 26.29fF
+C1000 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1001 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1002 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z3 0.65fF
+C1003 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/B 0.20fF
+C1004 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1005 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1006 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1007 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1008 gpio_noesd[8] gpio_noesd[13] 0.55fF
+C1009 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1010 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1011 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in5 0.84fF
+C1012 io_analog[5] ro_divider_buffered_0/ro_complete_0/a2 0.35fF
+C1013 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1014 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1015 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C1016 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A 0.15fF
+C1017 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.09fF
+C1018 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/pd_0/R 0.21fF
+C1019 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/and_0/OUT 0.14fF
+C1020 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/clk 0.51fF
+C1021 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1022 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1023 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/clk 0.04fF
+C1024 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1025 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.07fF
+C1026 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1027 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1028 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1029 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.05fF
+C1030 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C1031 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in1 0.22fF
+C1032 io_analog[3] io_analog[6] 1.03fF
+C1033 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A 0.15fF
+C1034 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.09fF
+C1035 ro_divider_buffered_0/tapered_buf_4/in2 ro_divider_buffered_0/tapered_buf_4/in5 0.84fF
+C1036 ro_divider_buffered_0/tapered_buf_4/in3 ro_divider_buffered_0/tapered_buf_4/in4 4.78fF
+C1037 pd_buffered_0/pd_0/DIV io_analog[10] 0.52fF
+C1038 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1039 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1040 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1041 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
+C1042 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in2 0.37fF
+C1043 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1044 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.07fF
+C1045 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/B 0.08fF
+C1046 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C1047 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C1048 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/clk 0.12fF
+C1049 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C1050 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1051 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1052 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/tspc_2/a_630_n680# 0.04fF
+C1053 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_0/B 0.06fF
+C1054 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C1055 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1056 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in2 0.37fF
+C1057 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/Z1 0.04fF
+C1058 div_pd_buffered_0/divider_0/tspc_2/Z3 div_pd_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C1059 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/clk 0.05fF
+C1060 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in5 2.89fF
+C1061 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/R 0.36fF
+C1062 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1063 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1064 gpio_noesd[4] divider_buffered_0/tapered_buf_1/in5 26.29fF
+C1065 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.33fF
+C1066 pll_full_buffered2_0/tapered_buf_5/in5 gpio_noesd[7] 26.29fF
+C1067 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.13fF
+C1068 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C1069 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1070 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/tspc_1/Z2 1.07fF
+C1071 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1072 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1073 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1074 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1075 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/clk 0.01fF
+C1076 gpio_noesd[11] gpio_analog[10] 0.49fF
+C1077 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C1078 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
+C1079 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/A 0.04fF
+C1080 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/B 0.31fF
+C1081 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1082 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C1083 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.35fF
+C1084 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/vco 0.60fF
+C1085 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C1086 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
+C1087 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_1/B 0.06fF
+C1088 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/R 0.36fF
+C1089 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1090 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C1091 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.13fF
+C1092 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in2 0.84fF
+C1093 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C1094 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1095 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1096 io_analog[7] ro_divider_buffered_0/tapered_buf_7/in1 0.19fF
+C1097 gpio_noesd[14] pll_full_buffered1_0/pll_full_0/vco 0.69fF
+C1098 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/clk 0.14fF
+C1099 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.35fF
+C1100 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/vco 0.60fF
+C1101 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C1102 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1103 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/a3 0.09fF
+C1104 io_analog[9] div_pd_buffered_0/divider_0/clk 0.65fF
+C1105 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/tapered_buf_4/in2 0.37fF
+C1106 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 1.07fF
+C1107 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1108 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1109 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C1110 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C1111 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/UP 0.45fF
+C1112 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.00fF
+C1113 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in5 2.89fF
+C1114 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_0/B 0.00fF
+C1115 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_0/Q 0.14fF
+C1116 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1117 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/clk 0.01fF
+C1118 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_0/in1 0.19fF
+C1119 cp_buffered_0/cp_0/out cp_buffered_0/tapered_buf_1/in1 0.19fF
+C1120 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
+C1121 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1122 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.09fF
+C1123 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C1124 io_analog[8] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C1125 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C1126 divider_buffered_0/tapered_buf_0/in4 divider_buffered_0/tapered_buf_0/in3 4.78fF
+C1127 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C1128 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1129 ro_divider_buffered_0/tapered_buf_8/in2 ro_divider_buffered_0/tapered_buf_8/in5 0.84fF
+C1130 ro_divider_buffered_0/tapered_buf_8/in3 ro_divider_buffered_0/tapered_buf_8/in4 4.78fF
+C1131 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1132 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1133 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
+C1134 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
+C1135 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C1136 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C1137 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C1138 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C1139 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C1140 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/nor_1/A 0.15fF
+C1141 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/R 0.61fF
+C1142 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
+C1143 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF
+C1144 cp_buffered_0/tapered_buf_0/in2 cp_buffered_0/tapered_buf_0/in5 0.84fF
+C1145 cp_buffered_0/tapered_buf_0/in3 cp_buffered_0/tapered_buf_0/in4 4.78fF
+C1146 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1147 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/R 0.03fF
+C1148 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in2 0.37fF
+C1149 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1150 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1151 io_analog[6] ro_divider_buffered_0/ro_complete_0/a0 0.21fF
+C1152 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.45fF
+C1153 gpio_noesd[14] gpio_noesd[9] 2.58fF
+C1154 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
+C1155 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
+C1156 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C1157 gpio_analog[8] io_analog[10] 1.48fF
+C1158 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C1159 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C1160 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1161 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
+C1162 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_divider_buffered_0/divider_0/clk 1.36fF
+C1163 divider_buffered_0/divider_0/and_0/A divider_buffered_0/divider_0/and_0/B 0.18fF
+C1164 gpio_noesd[10] gpio_noesd[8] 0.51fF
+C1165 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1166 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1167 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/pll_full_0/pd_0/R 0.03fF
+C1168 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1169 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
+C1170 filter_buffered_0/tapered_buf_0/in1 filter_buffered_0/tapered_buf_0/in2 0.37fF
+C1171 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/A 0.15fF
+C1172 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1173 ro_divider_buffered_0/tapered_buf_6/in3 ro_divider_buffered_0/tapered_buf_6/in5 2.89fF
+C1174 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.03fF
+C1175 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/nor_1/B 0.30fF
+C1176 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C1177 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.06fF
+C1178 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in1 0.37fF
+C1179 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1180 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1181 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C1182 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1183 ashish_0/a io_analog[1] 8.93fF
+C1184 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C1185 divider_buffered_0/tapered_buf_1/in2 divider_buffered_0/tapered_buf_1/in1 0.37fF
+C1186 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1187 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C1188 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C1189 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1190 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_0/B 0.06fF
+C1191 div_pd_buffered_0/pd_0/R div_pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C1192 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in3 1.27fF
+C1193 div_pd_buffered_0/tapered_buf_1/in3 div_pd_buffered_0/tapered_buf_1/in5 2.89fF
+C1194 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C1195 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
+C1196 pll_full_buffered2_0/tapered_buf_4/in4 pll_full_buffered2_0/tapered_buf_4/in5 29.21fF
+C1197 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in5 29.21fF
+C1198 ro_divider_buffered_0/tapered_buf_3/in1 ro_divider_buffered_0/tapered_buf_3/in2 0.37fF
+C1199 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_3/in5 0.22fF
+C1200 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/tapered_buf_0/in1 0.22fF
+C1201 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1202 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.06fF
+C1203 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C1204 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1205 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1206 gpio_analog[7] io_analog[9] 1.40fF
+C1207 ro_divider_buffered_0/ro_complete_0/a3 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1208 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1209 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1210 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.14fF
+C1211 divider_buffered_0/divider_0/prescaler_0/tspc_2/D divider_buffered_0/divider_0/clk 0.26fF
+C1212 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1213 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1214 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1215 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C1216 pd_buffered_0/tapered_buf_0/in1 pd_buffered_0/tapered_buf_0/in5 0.22fF
+C1217 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C1218 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/and_0/B 0.08fF
+C1219 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/nor_0/B 0.22fF
+C1220 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C1221 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in3 1.27fF
+C1222 pll_full_buffered2_0/tapered_buf_3/in io_analog[10] 0.42fF
+C1223 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1224 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/out1 0.06fF
+C1225 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.06fF
+C1226 io_analog[4] io_analog[5] 20.14fF
+C1227 ro_divider_buffered_0/tapered_buf_4/in4 ro_divider_buffered_0/tapered_buf_4/in5 29.21fF
+C1228 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1229 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1230 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1231 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in2 0.84fF
+C1232 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1233 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.14fF
+C1234 pll_full_buffered1_0/tapered_buf_1/in1 pll_full_buffered1_0/tapered_buf_1/in5 0.22fF
+C1235 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C1236 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1237 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1238 pll_full_buffered2_0/tapered_buf_4/in pll_full_buffered2_0/tapered_buf_4/in1 0.19fF
+C1239 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1240 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1241 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1242 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_0/B 0.15fF
+C1243 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/divider_0/nor_0/B 0.42fF
+C1244 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z2 0.11fF
+C1245 io_analog[6] ro_complete_buffered_0/tapered_buf_4/in1 0.19fF
+C1246 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in5 2.89fF
+C1247 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/clk 0.29fF
+C1248 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
+C1249 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1250 io_analog[6] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
+C1251 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1252 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C1253 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.08fF
+C1254 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C1255 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1256 divider_buffered_0/tapered_buf_1/in4 divider_buffered_0/tapered_buf_1/in5 29.21fF
+C1257 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1258 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1259 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.30fF
+C1260 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1261 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z3 0.16fF
+C1262 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1263 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
+C1264 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/R 0.21fF
+C1265 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/UP 0.03fF
+C1266 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 0.04fF
+C1267 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1268 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/vco 0.05fF
+C1269 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C1270 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C1271 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C1272 pd_buffered_0/tapered_buf_0/in5 pd_buffered_0/tapered_buf_0/in2 0.84fF
+C1273 pd_buffered_0/tapered_buf_0/in4 pd_buffered_0/tapered_buf_0/in3 4.78fF
+C1274 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C1275 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in3 1.27fF
+C1276 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1277 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/nor_1/A 0.03fF
+C1278 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.01fF
+C1279 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1280 io_analog[4] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C1281 ro_divider_buffered_0/tapered_buf_7/in1 ro_divider_buffered_0/tapered_buf_7/in2 0.37fF
+C1282 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.30fF
+C1283 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C1284 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/a1 0.14fF
+C1285 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Q 0.55fF
+C1286 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 0.04fF
+C1287 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C1288 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/vco 0.05fF
+C1289 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in3 1.27fF
+C1290 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z4 0.15fF
+C1291 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_0/Q 0.22fF
+C1292 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C1293 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1294 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_divider_buffered_0/divider_0/tspc_2/Z4 0.65fF
+C1295 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/nor_0/B 0.47fF
+C1296 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C1297 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C1298 cp_buffered_0/tapered_buf_1/in1 cp_buffered_0/tapered_buf_1/in2 0.37fF
+C1299 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1300 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1301 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 0.10fF
+C1302 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
+C1303 io_analog[3] io_analog[5] 0.93fF
+C1304 io_analog[8] gpio_analog[6] 0.64fF
+C1305 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in3 2.89fF
+C1306 ro_divider_buffered_0/tapered_buf_8/in4 ro_divider_buffered_0/tapered_buf_8/in5 29.21fF
+C1307 gpio_noesd[11] io_analog[10] 1.30fF
+C1308 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
+C1309 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C1310 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C1311 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in1 0.22fF
+C1312 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1313 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1314 gpio_analog[4] gpio_noesd[4] 0.91fF
+C1315 pll_full_buffered2_0/pll_full_0/cp_0/upbar io_analog[10] 0.36fF
+C1316 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
+C1317 div_pd_buffered_0/tapered_buf_4/in1 div_pd_buffered_0/pd_0/DOWN 0.19fF
+C1318 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C1319 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.00fF
+C1320 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1321 divider_buffered_0/divider_0/tspc_2/Z2 divider_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C1322 divider_buffered_0/divider_0/tspc_2/Z3 divider_buffered_0/divider_0/Out 0.05fF
+C1323 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/A 0.04fF
+C1324 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
+C1325 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/ro_complete_0/a4 26.29fF
+C1326 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/ro_complete_0/a3 26.29fF
+C1327 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.30fF
+C1328 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/out1 0.31fF
+C1329 div_pd_buffered_0/divider_0/tspc_1/Z4 div_pd_buffered_0/divider_0/tspc_0/Q 0.15fF
+C1330 filter_buffered_0/tapered_buf_1/in1 gpio_analog[17] 0.19fF
+C1331 cp_buffered_0/tapered_buf_0/in4 cp_buffered_0/tapered_buf_0/in5 29.21fF
+C1332 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/clk 0.64fF
+C1333 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1334 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in5 2.89fF
+C1335 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1336 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 0.09fF
+C1337 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 0.09fF
+C1338 io_analog[7] ro_divider_buffered_0/ro_complete_0/a1 0.33fF
+C1339 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/Z3 0.38fF
+C1340 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.00fF
+C1341 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1342 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in5 0.22fF
+C1343 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C1344 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1345 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
+C1346 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z3 0.09fF
+C1347 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/REF 0.19fF
+C1348 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C1349 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1350 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1351 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1352 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/divider_0/mc2 0.34fF
+C1353 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C1354 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1355 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1356 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/and_0/B 0.78fF
+C1357 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C1358 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/A 0.01fF
+C1359 div_pd_buffered_0/divider_0/tspc_0/Z3 div_pd_buffered_0/divider_0/tspc_0/Q 0.05fF
+C1360 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in3 1.27fF
+C1361 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1362 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 0.09fF
+C1363 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 0.09fF
+C1364 io_analog[3] ro_divider_buffered_0/ro_complete_0/a2 0.24fF
+C1365 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C1366 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1367 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1368 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1369 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C1370 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C1371 filter_buffered_0/filter_0/a_4216_n5230# filter_buffered_0/filter_0/v 0.19fF
+C1372 pd_buffered_0/tapered_buf_1/in3 pd_buffered_0/tapered_buf_1/in2 1.27fF
+C1373 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C1374 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1375 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/vco 0.15fF
+C1376 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/nor_0/B 0.47fF
+C1377 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1378 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1379 pll_full_buffered2_0/tapered_buf_3/in2 pll_full_buffered2_0/tapered_buf_3/in5 0.84fF
+C1380 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/and_0/B 0.01fF
+C1381 div_pd_buffered_0/tapered_buf_0/in2 div_pd_buffered_0/tapered_buf_0/in5 0.84fF
+C1382 div_pd_buffered_0/tapered_buf_0/in3 div_pd_buffered_0/tapered_buf_0/in4 4.78fF
+C1383 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1384 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1385 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C1386 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in3 1.27fF
+C1387 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in5 2.89fF
+C1388 io_analog[7] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C1389 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/tapered_buf_2/in4 29.21fF
+C1390 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C1391 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1392 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/tspc_0/Z4 0.36fF
+C1393 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C1394 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1395 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/vco 0.15fF
+C1396 ro_divider_buffered_0/tapered_buf_4/in5 ro_divider_buffered_0/ro_complete_0/a4 26.29fF
+C1397 io_clamp_high[0] io_analog[4] 0.53fF
+C1398 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1399 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/divider_0/mc2 26.29fF
+C1400 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/a0 0.13fF
+C1401 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1402 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C1403 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C1404 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_1/in4 4.78fF
+C1405 div_pd_buffered_0/divider_0/tspc_1/Q div_pd_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C1406 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1407 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/clk 0.01fF
+C1408 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in3 1.27fF
+C1409 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1410 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.27fF
+C1411 pll_full_buffered1_0/pll_full_0/cp_0/vbias pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# 0.19fF
+C1412 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C1413 divider_buffered_0/tapered_buf_0/in4 divider_buffered_0/tapered_buf_0/in5 29.21fF
+C1414 pll_full_buffered2_0/tapered_buf_0/in5 pll_full_buffered2_0/tapered_buf_0/in3 2.89fF
+C1415 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1416 io_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.31fF
+C1417 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/clk 0.45fF
+C1418 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C1419 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.01fF
+C1420 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1421 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1422 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.18fF
+C1423 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/tspc_0/Z4 0.12fF
+C1424 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C1425 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_0/Q 0.14fF
+C1426 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/clk 0.01fF
+C1427 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.22fF
+C1428 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1429 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1430 divider_buffered_0/tapered_buf_1/in3 divider_buffered_0/tapered_buf_1/in4 4.78fF
+C1431 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C1432 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1433 divider_buffered_0/divider_0/nor_1/Z1 divider_buffered_0/divider_0/and_0/B 0.18fF
+C1434 pll_full_buffered1_0/tapered_buf_1/in1 io_analog[10] 0.19fF
+C1435 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.11fF
+C1436 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1437 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1438 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1439 gpio_analog[4] divider_buffered_0/tapered_buf_2/in1 0.19fF
+C1440 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.22fF
+C1441 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1442 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1443 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1444 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/DOWN 0.02fF
+C1445 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C1446 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1447 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C1448 io_analog[10] div_pd_buffered_0/divider_0/clk 0.61fF
+C1449 gpio_analog[10] div_pd_buffered_0/tapered_buf_3/in1 0.19fF
+C1450 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_3/in5 29.21fF
+C1451 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1452 pll_full_buffered2_0/tapered_buf_2/in3 pll_full_buffered2_0/tapered_buf_2/in2 1.27fF
+C1453 pll_full_buffered2_0/tapered_buf_2/in5 gpio_noesd[8] 26.29fF
+C1454 ro_divider_buffered_0/tapered_buf_1/in3 ro_divider_buffered_0/tapered_buf_1/in2 1.27fF
+C1455 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/mc2 0.04fF
+C1456 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C1457 gpio_noesd[8] pll_full_buffered2_0/tapered_buf_3/in 0.23fF
+C1458 div_pd_buffered_0/pd_0/tspc_r_1/Z2 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
+C1459 ro_divider_buffered_0/tapered_buf_0/in1 ro_divider_buffered_0/tapered_buf_0/in2 0.37fF
+C1460 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C1461 cp_buffered_0/tapered_buf_2/in1 gpio_analog[7] 0.19fF
+C1462 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/REF 0.12fF
+C1463 pll_full_buffered1_0/tapered_buf_1/in4 pll_full_buffered1_0/tapered_buf_1/in3 4.78fF
+C1464 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/div 0.04fF
+C1465 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C1466 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/vco 0.29fF
+C1467 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_5/in5 0.22fF
+C1468 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/and_0/OUT 0.14fF
+C1469 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/clk 0.51fF
+C1470 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in5 0.84fF
+C1471 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/in4 4.78fF
+C1472 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1473 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in3 1.27fF
+C1474 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C1475 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1476 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C1477 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1478 pll_full_buffered2_0/tapered_buf_1/in5 pll_full_buffered2_0/tapered_buf_1/in4 29.21fF
+C1479 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/div 0.04fF
+C1480 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C1481 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered2_0/pll_full_0/vco 0.29fF
+C1482 ro_divider_buffered_0/tapered_buf_0/in4 ro_divider_buffered_0/tapered_buf_0/in5 29.21fF
+C1483 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C1484 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C1485 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1486 pd_buffered_0/tapered_buf_3/in1 io_analog[10] 0.19fF
+C1487 pd_buffered_0/tapered_buf_3/in2 pd_buffered_0/tapered_buf_3/in3 1.27fF
+C1488 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
+C1489 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1490 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered1_0/pll_full_0/vco 1.27fF
+C1491 div_pd_buffered_0/tapered_buf_4/in2 div_pd_buffered_0/tapered_buf_4/in5 0.84fF
+C1492 div_pd_buffered_0/tapered_buf_4/in3 div_pd_buffered_0/tapered_buf_4/in4 4.78fF
+C1493 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/clk 0.45fF
+C1494 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/nor_1/B 0.06fF
+C1495 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_divider_buffered_0/divider_0/and_0/B 0.78fF
+C1496 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C1497 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1498 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C1499 pll_full_buffered2_0/tapered_buf_3/in1 pll_full_buffered2_0/tapered_buf_3/in 0.19fF
+C1500 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C1501 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1502 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1503 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/nor_0/B 0.15fF
+C1504 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in3 1.27fF
+C1505 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1506 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C1507 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C1508 io_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.27fF
+C1509 io_clamp_low[2] io_analog[6] 0.53fF
+C1510 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_0/Q 0.14fF
+C1511 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.04fF
+C1512 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C1513 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v pll_full_buffered2_0/pll_full_0/vco 1.27fF
+C1514 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered1_0/pll_full_0/div 0.04fF
+C1515 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1516 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.47fF
+C1517 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
+C1518 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C1519 div_pd_buffered_0/pd_0/tspc_r_0/Z1 div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C1520 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C1521 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1522 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C1523 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C1524 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1525 io_analog[5] ro_complete_buffered_0/ro_complete_0/a2 0.25fF
+C1526 cp_buffered_0/tapered_buf_0/in5 cp_buffered_0/cp_0/down 26.29fF
+C1527 ro_divider_buffered_0/tapered_buf_5/in1 ro_divider_buffered_0/tapered_buf_5/in5 0.22fF
+C1528 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/a_10_n50# 0.04fF
+C1529 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.03fF
+C1530 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 pll_full_buffered2_0/pll_full_0/div 0.04fF
+C1531 ro_divider_buffered_0/tapered_buf_1/in5 ro_divider_buffered_0/tapered_buf_1/in3 2.89fF
+C1532 io_analog[9] divider_buffered_0/tapered_buf_0/in1 0.19fF
+C1533 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.47fF
+C1534 gpio_noesd[10] gpio_noesd[11] 6.19fF
+C1535 div_pd_buffered_0/tapered_buf_2/in3 div_pd_buffered_0/tapered_buf_2/in5 2.89fF
+C1536 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF
+C1537 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1538 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_1/Q 0.51fF
+C1539 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1540 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 0.31fF
+C1541 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
+C1542 div_pd_buffered_0/pd_0/tspc_r_0/Z4 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1543 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
+C1544 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/DOWN 0.11fF
+C1545 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_3/in3 1.27fF
+C1546 divider_buffered_0/divider_0/and_0/B divider_buffered_0/divider_0/and_0/Z1 0.07fF
+C1547 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/B 0.20fF
+C1548 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1549 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1550 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/tapered_buf_3/in 0.03fF
+C1551 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
+C1552 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 0.38fF
+C1553 filter_buffered_0/tapered_buf_0/in2 filter_buffered_0/tapered_buf_0/in5 0.84fF
+C1554 filter_buffered_0/tapered_buf_0/in3 filter_buffered_0/tapered_buf_0/in4 4.78fF
+C1555 gpio_noesd[11] gpio_noesd[8] 0.55fF
+C1556 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a2 1.38fF
+C1557 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C1558 pll_full_buffered1_0/pll_full_0/pd_0/R pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C1559 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 divider_buffered_0/divider_0/prescaler_0/Out 0.08fF
+C1560 divider_buffered_0/tapered_buf_2/in5 divider_buffered_0/divider_0/clk 26.29fF
+C1561 gpio_analog[7] io_analog[10] 2.78fF
+C1562 pll_full_buffered2_0/pll_full_0/cp_0/upbar gpio_noesd[8] 0.21fF
+C1563 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a3 3.17fF
+C1564 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C1565 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in4 29.21fF
+C1566 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1567 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 0.31fF
+C1568 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.15fF
+C1569 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C1570 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.35fF
+C1571 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1572 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_4/in5 0.22fF
+C1573 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/tspc_2/Z2 0.20fF
+C1574 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C1575 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_divider_buffered_0/divider_0/nor_1/B 0.03fF
+C1576 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1577 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C1578 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
+C1579 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.29fF
+C1580 div_pd_buffered_0/tapered_buf_0/in4 div_pd_buffered_0/tapered_buf_0/in5 29.21fF
+C1581 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1582 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/ro_complete_0/a2 26.29fF
+C1583 gpio_analog[3] gpio_analog[4] 1.29fF
+C1584 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1585 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1586 pll_full_buffered2_0/pll_full_0/pd_0/R pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C1587 cp_buffered_0/cp_0/upbar cp_buffered_0/cp_0/down 0.02fF
+C1588 cp_buffered_0/tapered_buf_2/in2 cp_buffered_0/tapered_buf_2/in5 0.84fF
+C1589 io_analog[7] gpio_analog[6] 0.64fF
+C1590 io_analog[3] io_analog[4] 0.88fF
+C1591 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1592 ro_divider_buffered_0/tapered_buf_3/in2 ro_divider_buffered_0/tapered_buf_3/in5 0.84fF
+C1593 ro_divider_buffered_0/tapered_buf_3/in3 ro_divider_buffered_0/tapered_buf_3/in4 4.78fF
+C1594 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1595 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.35fF
+C1596 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C1597 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C1598 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.06fF
+C1599 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.29fF
+C1600 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in1 0.22fF
+C1601 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.05fF
+C1602 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_3/in3 2.89fF
+C1603 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/nor_0/B 0.35fF
+C1604 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/clk 0.60fF
+C1605 pll_full_buffered2_0/tapered_buf_2/in5 pll_full_buffered2_0/tapered_buf_2/in1 0.22fF
+C1606 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C1607 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1608 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C1609 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C1610 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
+C1611 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1612 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/A 0.01fF
+C1613 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/tspc_0/Q 0.05fF
+C1614 div_pd_buffered_0/divider_0/nor_1/B div_pd_buffered_0/divider_0/and_0/B 0.31fF
+C1615 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1616 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1617 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in3 2.89fF
+C1618 filter_buffered_0/tapered_buf_1/in2 filter_buffered_0/tapered_buf_1/in5 0.84fF
+C1619 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/R 0.61fF
+C1620 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.06fF
+C1621 pll_full_buffered2_0/tapered_buf_5/in2 pll_full_buffered2_0/tapered_buf_5/in3 1.27fF
+C1622 io_analog[6] ro_divider_buffered_0/ro_complete_0/a1 0.20fF
+C1623 io_analog[9] div_pd_buffered_0/tapered_buf_2/in1 0.19fF
+C1624 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1625 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.05fF
+C1626 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1627 ro_divider_buffered_0/ro_complete_0/a5 ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C1628 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C1629 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1630 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/R 0.29fF
+C1631 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C1632 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C1633 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1634 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1635 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/Out 1.14fF
+C1636 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/clk 0.01fF
+C1637 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
+C1638 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.14fF
+C1639 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1640 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
+C1641 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
+C1642 divider_buffered_0/tapered_buf_2/in3 divider_buffered_0/tapered_buf_2/in2 1.27fF
+C1643 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1644 io_analog[6] ro_divider_buffered_0/tapered_buf_6/in1 0.19fF
+C1645 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1646 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C1647 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C1648 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C1649 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1650 gpio_noesd[9] io_analog[9] 1.19fF
+C1651 div_pd_buffered_0/tapered_buf_3/in1 div_pd_buffered_0/tapered_buf_3/in2 0.37fF
+C1652 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1653 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
+C1654 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1655 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1656 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C1657 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B pll_full_buffered1_0/pll_full_0/div 0.27fF
+C1658 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_5/in5 2.89fF
+C1659 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/clk 0.04fF
+C1660 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Z2 0.23fF
+C1661 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1662 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1663 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/in5 29.21fF
+C1664 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_1/in5 0.22fF
+C1665 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_0/in5 26.29fF
+C1666 cp_buffered_0/tapered_buf_2/in3 cp_buffered_0/tapered_buf_2/in2 1.27fF
+C1667 gpio_noesd[9] gpio_noesd[7] 3.28fF
+C1668 io_analog[6] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C1669 divider_buffered_0/divider_0/tspc_0/Z1 divider_buffered_0/divider_0/tspc_0/Z3 0.06fF
+C1670 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.18fF
+C1671 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C1672 ro_divider_buffered_0/tapered_buf_7/in2 ro_divider_buffered_0/tapered_buf_7/in5 0.84fF
+C1673 ro_divider_buffered_0/tapered_buf_7/in3 ro_divider_buffered_0/tapered_buf_7/in4 4.78fF
+C1674 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1675 gpio_analog[5] ro_divider_buffered_0/divider_0/Out 0.75fF
+C1676 divider_buffered_0/tapered_buf_0/in5 divider_buffered_0/tapered_buf_0/in1 0.22fF
+C1677 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/and_0/B 0.08fF
+C1678 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C1679 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B pll_full_buffered2_0/pll_full_0/div 0.27fF
+C1680 div_pd_buffered_0/tapered_buf_4/in4 div_pd_buffered_0/tapered_buf_4/in5 29.21fF
+C1681 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C1682 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/tspc_1/Q 0.05fF
+C1683 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
+C1684 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C1685 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C1686 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C1687 divider_buffered_0/divider_0/nor_1/B divider_buffered_0/divider_0/and_0/B 0.31fF
+C1688 divider_buffered_0/divider_0/tspc_0/Z3 divider_buffered_0/divider_0/tspc_0/Q 0.05fF
+C1689 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C1690 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1691 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C1692 cp_buffered_0/tapered_buf_1/in2 cp_buffered_0/tapered_buf_1/in5 0.84fF
+C1693 cp_buffered_0/tapered_buf_1/in3 cp_buffered_0/tapered_buf_1/in4 4.78fF
+C1694 io_analog[3] ro_complete_buffered_0/tapered_buf_1/in1 0.19fF
+C1695 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 0.11fF
+C1696 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1697 io_analog[4] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C1698 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/Out 0.15fF
+C1699 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C1700 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q 0.51fF
+C1701 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C1702 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C1703 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C1704 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/in1 0.22fF
+C1705 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C1706 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1707 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C1708 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 div_pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
+C1709 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C1710 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
+C1711 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/nor_1/A 0.21fF
+C1712 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1713 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C1714 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
+C1715 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# div_pd_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C1716 div_pd_buffered_0/divider_0/tspc_2/Z1 div_pd_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C1717 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C1718 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1719 pd_buffered_0/tapered_buf_1/in5 pd_buffered_0/tapered_buf_1/in4 29.21fF
+C1720 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C1721 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C1722 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1723 ro_divider_buffered_0/tapered_buf_5/in3 ro_divider_buffered_0/tapered_buf_5/in5 2.89fF
+C1724 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C1725 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
+C1726 pd_buffered_0/tapered_buf_3/in5 pd_buffered_0/tapered_buf_3/in2 0.84fF
+C1727 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in3 4.78fF
+C1728 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1729 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 1.21fF
+C1730 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 0.09fF
+C1731 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered2_0/pll_full_0/ref 0.19fF
+C1732 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_divider_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C1733 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1734 div_pd_buffered_0/pd_0/tspc_r_0/z5 div_pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
+C1735 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
+C1736 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C1737 div_pd_buffered_0/divider_0/and_0/out1 div_pd_buffered_0/divider_0/and_0/Z1 0.36fF
+C1738 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
+C1739 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1740 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C1741 filter_buffered_0/tapered_buf_0/in4 filter_buffered_0/tapered_buf_0/in5 29.21fF
+C1742 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 4.79fF
+C1743 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_2/in2 0.37fF
+C1744 divider_buffered_0/divider_0/tspc_1/Z1 divider_buffered_0/divider_0/tspc_1/Z4 0.00fF
+C1745 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1746 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 1.21fF
+C1747 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C1748 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 pll_full_buffered1_0/pll_full_0/vco 0.19fF
+C1749 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1750 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT 0.14fF
+C1751 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/vco 0.51fF
+C1752 pll_full_buffered2_0/tapered_buf_3/in4 pll_full_buffered2_0/tapered_buf_3/in5 29.21fF
+C1753 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_divider_buffered_0/divider_0/nor_1/B 0.38fF
+C1754 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z1 0.00fF
+C1755 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C1756 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/divider_0/clk 0.05fF
+C1757 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C1758 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 div_pd_buffered_0/divider_0/prescaler_0/Out 0.05fF
+C1759 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.06fF
+C1760 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/UP 2.89fF
+C1761 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z3 0.05fF
+C1762 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z1 0.03fF
+C1763 div_pd_buffered_0/tapered_buf_0/in5 gpio_noesd[12] 26.29fF
+C1764 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_6/in2 0.37fF
+C1765 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1766 filter_buffered_0/filter_0/v filter_buffered_0/tapered_buf_1/in5 26.29fF
+C1767 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/in1 0.37fF
+C1768 gpio_noesd[14] io_analog[9] 3.54fF
+C1769 ro_divider_buffered_0/tapered_buf_3/in4 ro_divider_buffered_0/tapered_buf_3/in5 29.21fF
+C1770 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C1771 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C1772 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z2 0.14fF
+C1773 io_analog[4] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
+C1774 io_analog[3] ro_divider_buffered_0/ro_complete_0/a0 0.22fF
+C1775 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT 0.14fF
+C1776 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/vco 0.51fF
+C1777 pll_full_buffered2_0/tapered_buf_4/in2 pll_full_buffered2_0/tapered_buf_4/in1 0.37fF
+C1778 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1779 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/div 0.12fF
+C1780 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1781 ro_divider_buffered_0/ro_complete_0/a1 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.03fF
+C1782 gpio_noesd[14] gpio_noesd[7] 2.93fF
+C1783 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.08fF
+C1784 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C1785 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C1786 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/vco 0.12fF
+C1787 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C1788 ro_divider_buffered_0/divider_0/mc2 ro_divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C1789 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C1790 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_divider_buffered_0/divider_0/clk 1.43fF
+C1791 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/Z1 0.04fF
+C1792 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/tspc_2/Z2 0.01fF
+C1793 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q divider_buffered_0/divider_0/clk 0.05fF
+C1794 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/tapered_buf_3/in 0.32fF
+C1795 div_pd_buffered_0/tapered_buf_1/in1 io_analog[10] 0.19fF
+C1796 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C1797 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/clk 0.11fF
+C1798 ro_divider_buffered_0/tapered_buf_2/in5 ro_divider_buffered_0/tapered_buf_2/in1 0.22fF
+C1799 io_analog[4] ro_complete_buffered_0/ro_complete_0/a2 0.37fF
+C1800 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.01fF
+C1801 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/B 0.20fF
+C1802 pll_full_buffered2_0/tapered_buf_5/in3 pll_full_buffered2_0/tapered_buf_5/in4 4.78fF
+C1803 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
+C1804 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.30fF
+C1805 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1806 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/div 0.12fF
+C1807 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C1808 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.08fF
+C1809 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C1810 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C1811 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/vco 0.12fF
+C1812 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C1813 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.01fF
+C1814 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.31fF
+C1815 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1816 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C1817 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z3 0.65fF
+C1818 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C1819 divider_buffered_0/divider_0/and_0/out1 divider_buffered_0/divider_0/and_0/B 0.18fF
+C1820 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C1821 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C1822 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar pll_full_buffered2_0/tapered_buf_3/in 0.02fF
+C1823 pll_full_buffered2_0/tapered_buf_2/in4 pll_full_buffered2_0/tapered_buf_2/in3 4.78fF
+C1824 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
+C1825 ro_divider_buffered_0/tapered_buf_6/in1 ro_divider_buffered_0/tapered_buf_6/in2 0.37fF
+C1826 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/Out 0.19fF
+C1827 pll_full_buffered2_0/tapered_buf_1/in1 pll_full_buffered2_0/tapered_buf_1/in5 0.22fF
+C1828 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C1829 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
+C1830 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1831 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 0.09fF
+C1832 divider_buffered_0/divider_0/nor_0/Z1 divider_buffered_0/divider_0/nor_1/B 0.18fF
+C1833 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.31fF
+C1834 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C1835 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C1836 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in3 1.27fF
+C1837 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF
+C1838 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1839 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_3/in 5.03fF
+C1840 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C1841 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C1842 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C1843 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/UP 0.21fF
+C1844 div_pd_buffered_0/tapered_buf_1/in1 div_pd_buffered_0/tapered_buf_1/in2 0.37fF
+C1845 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C1846 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1847 io_analog[6] gpio_analog[6] 0.64fF
+C1848 io_analog[7] ro_complete_buffered_0/ro_complete_0/a1 0.23fF
+C1849 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
+C1850 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1851 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 0.09fF
+C1852 io_analog[7] io_analog[8] 1.38fF
+C1853 io_analog[3] ro_divider_buffered_0/ro_complete_0/a3 0.23fF
+C1854 ro_divider_buffered_0/tapered_buf_7/in4 ro_divider_buffered_0/tapered_buf_7/in5 29.21fF
+C1855 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/nor_1/B 0.35fF
+C1856 ro_divider_buffered_0/ro_complete_0/a4 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C1857 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C1858 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_divider_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1859 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/vco 0.55fF
+C1860 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1861 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C1862 div_pd_buffered_0/tapered_buf_4/in5 gpio_noesd[13] 26.29fF
+C1863 gpio_analog[3] io_analog[1] 1.96fF
+C1864 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C1865 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C1866 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C1867 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C1868 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_divider_buffered_0/divider_0/tspc_0/Z2 0.36fF
+C1869 divider_buffered_0/divider_0/mc2 divider_buffered_0/tapered_buf_0/in5 26.29fF
+C1870 io_analog[3] ro_complete_buffered_0/ro_complete_0/a2 0.22fF
+C1871 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1872 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1873 cp_buffered_0/tapered_buf_1/in4 cp_buffered_0/tapered_buf_1/in5 29.21fF
+C1874 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C1875 pll_full_buffered1_0/pll_full_0/cp_0/upbar pll_full_buffered1_0/pll_full_0/pd_0/DOWN 0.02fF
+C1876 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1877 gpio_noesd[14] gpio_analog[10] 2.60fF
+C1878 io_analog[5] ro_divider_buffered_0/ro_complete_0/a1 0.30fF
+C1879 ro_divider_buffered_0/tapered_buf_1/in4 ro_divider_buffered_0/tapered_buf_1/in5 29.21fF
+C1880 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in2 0.84fF
+C1881 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C1882 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C1883 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C1884 gpio_noesd[10] pd_buffered_0/pd_0/DOWN 0.54fF
+C1885 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C1886 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered1_0/pll_full_0/vco 1.36fF
+C1887 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_4/in4 4.78fF
+C1888 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Q 0.55fF
+C1889 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_divider_buffered_0/divider_0/clk 1.30fF
+C1890 filter_buffered_0/filter_0/a_4216_n2998# filter_buffered_0/filter_0/v 0.31fF
+C1891 gpio_analog[9] pd_buffered_0/tapered_buf_1/in1 0.19fF
+C1892 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_1/Z3 0.06fF
+C1893 div_pd_buffered_0/divider_0/and_0/OUT div_pd_buffered_0/divider_0/and_0/B 0.01fF
+C1894 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C1895 div_pd_buffered_0/divider_0/nor_0/B div_pd_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C1896 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1897 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C1898 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v pll_full_buffered2_0/pll_full_0/vco 1.36fF
+C1899 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C1900 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C1901 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1902 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B 0.06fF
+C1903 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
+C1904 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 div_pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
+C1905 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/R 0.27fF
+C1906 io_analog[8] io_analog[9] 1.33fF
+C1907 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z1 0.01fF
+C1908 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_0/Q 0.22fF
+C1909 gpio_analog[9] gpio_noesd[9] 1.46fF
+C1910 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/nor_1/B 1.21fF
+C1911 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1912 div_pd_buffered_0/divider_0/and_0/A div_pd_buffered_0/divider_0/and_0/B 0.18fF
+C1913 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1914 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in5 0.84fF
+C1915 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 3.73fF
+C1916 io_analog[5] ro_complete_buffered_0/ro_complete_0/a0 0.23fF
+C1917 filter_buffered_0/tapered_buf_0/in5 gpio_analog[17] 26.29fF
+C1918 pll_full_buffered1_0/tapered_buf_0/in5 pll_full_buffered1_0/tapered_buf_0/in4 29.21fF
+C1919 divider_buffered_0/divider_0/tspc_1/Z3 divider_buffered_0/divider_0/tspc_1/Z4 0.65fF
+C1920 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C1921 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C1922 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1923 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B 0.06fF
+C1924 pll_full_buffered1_0/pll_full_0/vco io_analog[10] 0.56fF
+C1925 ro_divider_buffered_0/ro_complete_0/a2 ro_divider_buffered_0/ro_complete_0/a1 3.18fF
+C1926 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1927 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1928 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C1929 pll_full_buffered2_0/pll_full_0/cp_0/vbias pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# 0.19fF
+C1930 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1931 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_divider_buffered_0/divider_0/and_0/A 0.80fF
+C1932 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1933 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C1934 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1935 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1936 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1937 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered1_0/pll_full_0/vco 1.46fF
+C1938 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/nor_0/B 0.22fF
+C1939 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1940 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
+C1941 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in3 1.27fF
+C1942 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/tspc_2/Z4 0.12fF
+C1943 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/tspc_2/Z2 1.07fF
+C1944 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z3 0.38fF
+C1945 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C1946 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1947 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1948 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1949 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1950 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a0 0.47fF
+C1951 io_clamp_low[1] io_analog[5] 0.53fF
+C1952 divider_buffered_0/divider_0/nor_1/A divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1953 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C1954 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1955 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C1956 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_buffered2_0/pll_full_0/vco 1.46fF
+C1957 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1958 pd_buffered_0/tapered_buf_3/in4 pd_buffered_0/tapered_buf_3/in5 29.21fF
+C1959 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1960 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_divider_buffered_0/divider_0/tspc_1/Z4 0.12fF
+C1961 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1962 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1963 divider_buffered_0/divider_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/Out 0.04fF
+C1964 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/tspc_2/Z2 0.40fF
+C1965 divider_buffered_0/divider_0/prescaler_0/tspc_0/D divider_buffered_0/divider_0/clk 0.29fF
+C1966 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1967 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF
+C1968 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C1969 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_1/in1 0.37fF
+C1970 ro_divider_buffered_0/divider_0/and_0/out1 ro_divider_buffered_0/divider_0/and_0/Z1 0.36fF
+C1971 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C1972 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1973 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1974 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C1975 gpio_analog[5] ro_divider_buffered_0/divider_0/mc2 0.49fF
+C1976 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1977 gpio_noesd[9] io_analog[10] 1.63fF
+C1978 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1979 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/Z3 0.20fF
+C1980 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/REF 0.04fF
+C1981 ashish_0/a gpio_analog[3] 0.27fF
+C1982 io_analog[0] io_analog[1] 8.34fF
+C1983 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered1_0/pll_full_0/vco 1.58fF
+C1984 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C1985 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1986 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_2/in5 29.21fF
+C1987 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1988 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/clk 0.11fF
+C1989 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C1990 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/vco 0.11fF
+C1991 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
+C1992 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C1993 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.03fF
+C1994 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/nor_1/A 0.35fF
+C1995 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1996 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C1997 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.03fF
+C1998 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# 0.32fF
+C1999 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C2000 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# pll_full_buffered2_0/pll_full_0/vco 1.58fF
+C2001 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C2002 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C2003 ro_divider_buffered_0/tapered_buf_6/in2 ro_divider_buffered_0/tapered_buf_6/in3 1.27fF
+C2004 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 0.14fF
+C2005 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C2006 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/vco 0.11fF
+C2007 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C2008 div_pd_buffered_0/tapered_buf_3/in2 div_pd_buffered_0/tapered_buf_3/in5 0.84fF
+C2009 div_pd_buffered_0/tapered_buf_3/in3 div_pd_buffered_0/tapered_buf_3/in4 4.78fF
+C2010 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/clk 0.12fF
+C2011 pll_full_buffered2_0/tapered_buf_1/in3 pll_full_buffered2_0/tapered_buf_1/in2 1.27fF
+C2012 pll_full_buffered2_0/pll_full_0/ref pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C2013 ro_divider_buffered_0/divider_0/and_0/OUT ro_divider_buffered_0/divider_0/clk 0.04fF
+C2014 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C2015 div_pd_buffered_0/tapered_buf_1/in2 div_pd_buffered_0/tapered_buf_1/in3 1.27fF
+C2016 div_pd_buffered_0/divider_0/mc2 div_pd_buffered_0/divider_0/and_0/A 0.16fF
+C2017 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/tspc_1/Q 0.04fF
+C2018 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.06fF
+C2019 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C2020 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C2021 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C2022 pd_buffered_0/tapered_buf_0/in2 pd_buffered_0/tapered_buf_0/in3 1.27fF
+C2023 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C2024 divider_buffered_0/divider_0/mc2 divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C2025 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# 0.32fF
+C2026 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C2027 ro_divider_buffered_0/tapered_buf_1/in1 io_analog[9] 0.19fF
+C2028 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 0.14fF
+C2029 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered1_0/pll_full_0/pd_0/UP 0.33fF
+C2030 io_analog[4] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
+C2031 gpio_analog[5] ro_divider_buffered_0/ro_complete_0/a3 0.13fF
+C2032 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/and_0/OUT 0.06fF
+C2033 ro_divider_buffered_0/tapered_buf_3/in5 ro_divider_buffered_0/ro_complete_0/a5 26.29fF
+C2034 gpio_noesd[14] gpio_analog[9] 2.63fF
+C2035 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C2036 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C2037 io_analog[7] ro_complete_buffered_0/tapered_buf_3/in1 0.19fF
+C2038 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C2039 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C2040 divider_buffered_0/tapered_buf_2/in1 divider_buffered_0/tapered_buf_2/in5 0.22fF
+C2041 ro_divider_buffered_0/tapered_buf_0/in5 ro_divider_buffered_0/tapered_buf_0/in2 0.84fF
+C2042 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_divider_buffered_0/divider_0/clk 0.64fF
+C2043 pll_full_buffered1_0/tapered_buf_1/in2 pll_full_buffered1_0/tapered_buf_1/in5 0.84fF
+C2044 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C2045 divider_buffered_0/divider_0/and_0/OUT divider_buffered_0/divider_0/and_0/out1 0.31fF
+C2046 div_pd_buffered_0/divider_0/nor_0/Z1 div_pd_buffered_0/divider_0/nor_1/B 0.18fF
+C2047 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C2048 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_2/in4 4.78fF
+C2049 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar 0.01fF
+C2050 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF
+C2051 div_pd_buffered_0/divider_0/nor_1/A div_pd_buffered_0/divider_0/tspc_0/Q 0.55fF
+C2052 cp_buffered_0/tapered_buf_1/in5 gpio_noesd[9] 26.29fF
+C2053 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C2054 divider_buffered_0/divider_0/tspc_1/Z2 divider_buffered_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C2055 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 pll_full_buffered2_0/pll_full_0/pd_0/UP 0.33fF
+C2056 ro_divider_buffered_0/tapered_buf_4/in1 ro_divider_buffered_0/tapered_buf_4/in5 0.22fF
+C2057 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C2058 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C2059 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C2060 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C2061 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C2062 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2063 gpio_noesd[7] pll_full_buffered2_0/tapered_buf_5/in 0.54fF
+C2064 divider_buffered_0/divider_0/prescaler_0/Out divider_buffered_0/divider_0/tspc_0/Z3 0.45fF
+C2065 pll_full_buffered2_0/tapered_buf_5/in5 pll_full_buffered2_0/tapered_buf_5/in1 0.22fF
+C2066 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C2067 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C2068 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C2069 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/and_0/A 0.01fF
+C2070 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_4/in5 29.21fF
+C2071 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/and_0/B 0.29fF
+C2072 div_pd_buffered_0/divider_0/nor_1/Z1 div_pd_buffered_0/divider_0/and_0/A 0.80fF
+C2073 div_pd_buffered_0/divider_0/tspc_2/Z2 div_pd_buffered_0/divider_0/tspc_2/Z4 0.36fF
+C2074 filter_buffered_0/tapered_buf_1/in3 filter_buffered_0/tapered_buf_1/in4 4.78fF
+C2075 divider_buffered_0/divider_0/tspc_0/Z2 divider_buffered_0/divider_0/nor_1/A 0.23fF
+C2076 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered1_0/pll_full_0/pd_0/R 0.01fF
+C2077 pll_full_buffered1_0/pll_full_0/pd_0/DOWN pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C2078 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_2/in5 0.22fF
+C2079 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C2080 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C2081 ashish_0/b io_analog[1] 4.11fF
+C2082 pll_full_buffered2_0/pll_full_0/cp_0/upbar pll_full_buffered2_0/tapered_buf_4/in 0.05fF
+C2083 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C2084 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C2085 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 divider_buffered_0/divider_0/and_0/OUT 0.05fF
+C2086 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_0/Z4 0.21fF
+C2087 div_pd_buffered_0/pd_0/DOWN div_pd_buffered_0/pd_0/R 0.36fF
+C2088 div_pd_buffered_0/pd_0/tspc_r_1/Z3 div_pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
+C2089 div_pd_buffered_0/pd_0/DIV div_pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C2090 div_pd_buffered_0/pd_0/tspc_r_1/Z1 div_pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C2091 ro_divider_buffered_0/divider_0/tspc_1/Q ro_divider_buffered_0/divider_0/tspc_2/Z3 0.45fF
+C2092 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_divider_buffered_0/divider_0/tspc_0/Q 0.04fF
+C2093 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/and_0/A 0.26fF
+C2094 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/divider_0/and_0/B 0.01fF
+C2095 div_pd_buffered_0/divider_0/tspc_1/Z2 div_pd_buffered_0/divider_0/tspc_1/Z4 0.36fF
+C2096 div_pd_buffered_0/divider_0/tspc_1/Z3 div_pd_buffered_0/divider_0/tspc_1/Q 0.05fF
+C2097 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# div_pd_buffered_0/divider_0/nor_1/B 0.35fF
+C2098 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# div_pd_buffered_0/divider_0/tspc_0/Z2 0.01fF
+C2099 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_buffered2_0/pll_full_0/pd_0/R 0.01fF
+C2100 pll_full_buffered2_0/tapered_buf_3/in pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C2101 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF
+C2102 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_1/in5 29.21fF
+C2103 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C2104 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C2105 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
+C2106 gpio_noesd[14] io_analog[10] 2.21fF
+C2107 io_analog[5] gpio_analog[6] 0.64fF
+C2108 io_analog[6] ro_complete_buffered_0/ro_complete_0/a1 0.22fF
+C2109 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.01fF
+C2110 io_analog[6] io_analog[8] 1.24fF
+C2111 io_analog[3] ro_divider_buffered_0/ro_complete_0/a4 0.19fF
+C2112 pd_buffered_0/tapered_buf_2/in5 pd_buffered_0/tapered_buf_2/in1 0.22fF
+C2113 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C2114 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C2115 io_analog[0] ashish_0/a 4.11fF
+C2116 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 0.13fF
+C2117 gpio_noesd[12] gpio_noesd[14] 2.57fF
+C2118 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered2_0/pll_full_0/divider_0/and_0/B 0.01fF
+C2119 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C2120 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/UP 0.03fF
+C2121 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C2122 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C2123 divider_buffered_0/divider_0/tspc_1/Q divider_buffered_0/divider_0/tspc_2/Z2 0.14fF
+C2124 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.04fF
+C2125 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q divider_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C2126 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/clk 0.01fF
+C2127 ro_divider_buffered_0/divider_0/nor_1/A ro_divider_buffered_0/divider_0/tspc_1/Z4 0.02fF
+C2128 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C2129 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_divider_buffered_0/divider_0/tspc_2/Z3 0.16fF
+C2130 ro_divider_buffered_0/divider_0/nor_0/B ro_divider_buffered_0/divider_0/tspc_2/Z4 0.22fF
+C2131 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_6/in5 0.84fF
+C2132 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_6/in4 4.78fF
+C2133 div_pd_buffered_0/divider_0/tspc_1/Z1 div_pd_buffered_0/divider_0/tspc_0/Q 0.01fF
+C2134 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 div_pd_buffered_0/divider_0/and_0/OUT 0.05fF
+C2135 io_analog[4] ro_complete_buffered_0/tapered_buf_6/in1 0.19fF
+C2136 io_analog[5] ro_complete_buffered_0/tapered_buf_5/in1 0.19fF
+C2137 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in 1.30fF
+C2138 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C2139 pll_full_buffered2_0/tapered_buf_4/in5 pll_full_buffered2_0/tapered_buf_4/out 26.29fF
+C2140 pll_full_buffered1_0/pll_full_0/ref pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 0.17fF
+C2141 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 0.13fF
+C2142 io_analog[4] ro_divider_buffered_0/ro_complete_0/a1 0.21fF
+C2143 ro_divider_buffered_0/tapered_buf_8/in1 ro_divider_buffered_0/tapered_buf_8/in5 0.22fF
+C2144 io_analog[9] pll_full_buffered2_0/pll_full_0/div 0.68fF
+C2145 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C2146 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C2147 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B 0.18fF
+C2148 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C2149 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C2150 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered1_0/pll_full_0/div 0.19fF
+C2151 div_pd_buffered_0/pd_0/tspc_r_0/Z3 div_pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
+C2152 div_pd_buffered_0/pd_0/REF div_pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
+C2153 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
+C2154 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered1_0/pll_full_0/vco 0.01fF
+C2155 divider_buffered_0/divider_0/tspc_2/Z1 divider_buffered_0/divider_0/tspc_2/Z3 0.06fF
+C2156 divider_buffered_0/divider_0/nor_0/B divider_buffered_0/divider_0/Out 0.44fF
+C2157 ro_divider_buffered_0/divider_0/nor_1/B ro_divider_buffered_0/divider_0/tspc_1/Z4 0.21fF
+C2158 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C2159 ro_divider_buffered_0/ro_complete_0/a0 ro_divider_buffered_0/divider_0/clk 0.05fF
+C2160 div_pd_buffered_0/divider_0/tspc_0/Z4 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C2161 div_pd_buffered_0/divider_0/prescaler_0/Out div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C2162 ro_divider_buffered_0/divider_0/and_0/A ro_divider_buffered_0/divider_0/and_0/B 0.18fF
+C2163 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 0.22fF
+C2164 gpio_analog[8] cp_buffered_0/cp_0/down 0.25fF
+C2165 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C2166 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 0.06fF
+C2167 cp_buffered_0/tapered_buf_0/in1 cp_buffered_0/tapered_buf_0/in5 0.22fF
+C2168 pd_buffered_0/tapered_buf_2/in5 gpio_noesd[10] 26.29fF
+C2169 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 pll_full_buffered1_0/pll_full_0/pd_0/R 0.21fF
+C2170 io_analog[5] ro_divider_buffered_0/tapered_buf_5/in1 0.19fF
+C2171 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B 0.18fF
+C2172 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C2173 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C2174 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 pll_full_buffered2_0/pll_full_0/div 0.19fF
+C2175 gpio_noesd[14] gpio_noesd[13] 2.55fF
+C2176 divider_buffered_0/divider_0/tspc_1/a_630_n680# divider_buffered_0/divider_0/tspc_0/Q 0.01fF
+C2177 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q 0.14fF
+C2178 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_buffered2_0/pll_full_0/vco 0.01fF
+C2179 div_pd_buffered_0/tapered_buf_2/in1 div_pd_buffered_0/tapered_buf_2/in2 0.37fF
+C2180 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
+C2181 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF
+C2182 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C2183 divider_buffered_0/divider_0/tspc_0/a_630_n680# divider_buffered_0/divider_0/tspc_0/Z3 0.05fF
+C2184 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C2185 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C2186 ro_divider_buffered_0/tapered_buf_0/in5 gpio_noesd[5] 26.29fF
+C2187 div_pd_buffered_0/pd_0/tspc_r_0/Qbar div_pd_buffered_0/pd_0/R 0.03fF
+C2188 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT pll_full_buffered1_0/pll_full_0/div 0.01fF
+C2189 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
Xpll_full_buffered1_0 vssa1 vssa1 pll_full_buffered1
+Xashish_0 io_analog[1] io_analog[0] gpio_analog[3] vssa1 vdd ashish_0/a ashish_0/b
++ ashish
Xpd_buffered_0 vssa1 vssa1 pd_buffered
-Xashish_0 ashish_0/von ashish_0/vop ashish_0/a ashish_0/b ashish_0/cm vssa1 vdd ashish
Xcp_buffered_0 vssa1 vssa1 cp_buffered
Xfilter_buffered_0 vssa1 gpio_analog[17] filter_buffered
Xro_divider_buffered_0 vssa1 vssa1 ro_divider_buffered
@@ -2257,1387 +2307,1380 @@
Xdivider_buffered_0 vssa1 vssa1 divider_buffered
Xro_complete_buffered_0 vssa1 ro_complete_buffered
Xdiv_pd_buffered_0 vssa1 vssa1 div_pd_buffered
-C2141 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2142 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2143 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2144 io_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2145 io_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2146 io_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2147 io_oeb[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2148 io_in_3v3[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2149 io_in_3v3[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2150 io_oeb[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2151 io_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2152 io_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2153 io_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2154 io_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2155 io_oeb[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2156 io_in_3v3[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2157 io_in_3v3[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2158 io_oeb[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2159 io_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2160 io_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2161 io_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2162 io_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2163 io_oeb[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2164 io_in_3v3[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2165 io_in_3v3[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2166 gpio_noesd[17] ro_complete_buffered_0/tapered_buf_0/out 2.32fF
-C2167 io_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2168 io_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2169 io_oeb[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2170 io_in_3v3[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2171 io_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2172 io_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2173 io_oeb[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2174 io_in_3v3[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2175 io_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2176 io_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2177 io_oeb[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2178 io_oeb[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2179 io_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2180 io_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2181 io_in_3v3[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2182 gpio_noesd[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2183 gpio_analog[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2184 io_oeb[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2185 io_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2186 io_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2187 io_in_3v3[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2188 gpio_noesd[15] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
-C2189 gpio_analog[15] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2190 io_in_3v3[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2191 io_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2192 io_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2193 io_oeb[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2194 io_oeb[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2195 io_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2196 io_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2197 io_in_3v3[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2198 gpio_noesd[14] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2199 gpio_analog[14] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
-C2200 vssd2 ro_complete_buffered_0/tapered_buf_0/out 25.38fF
-C2201 vssd1 ro_complete_buffered_0/tapered_buf_0/out 13.04fF
-C2202 vdda1 ro_complete_buffered_0/tapered_buf_0/out 68.83fF
-C2203 gpio_analog[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2204 gpio_noesd[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2205 io_in_3v3[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2206 io_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2207 io_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2208 io_oeb[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2209 gpio_analog[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2210 gpio_noesd[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2211 io_in_3v3[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2212 io_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2213 io_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2214 io_oeb[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2215 gpio_analog[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2216 gpio_noesd[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2217 io_in_3v3[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2218 io_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2219 io_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2220 io_oeb[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2221 gpio_analog[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2222 gpio_noesd[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2223 io_in_3v3[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2224 io_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2225 io_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2226 io_oeb[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2227 gpio_analog[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2228 gpio_noesd[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2229 io_in_3v3[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2230 io_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2231 io_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2232 io_oeb[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2233 gpio_analog[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2234 gpio_noesd[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2235 io_in_3v3[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2236 io_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2237 io_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2238 io_oeb[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2239 vdda2 ro_complete_buffered_0/tapered_buf_0/out 24.41fF
-C2240 io_oeb[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2241 io_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2242 io_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2243 io_in_3v3[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2244 gpio_analog[13] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2245 io_oeb[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2246 io_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2247 io_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2248 io_in_3v3[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2249 gpio_analog[12] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
-C2250 io_oeb[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2251 io_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2252 io_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2253 io_in_3v3[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2254 gpio_analog[11] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
-C2255 io_oeb[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2256 io_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2257 io_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2258 io_in_3v3[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2259 io_oeb[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2260 io_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2261 io_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2262 io_in_3v3[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2263 io_oeb[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2264 io_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2265 io_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2266 io_in_3v3[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2267 io_oeb[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2268 io_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2269 io_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2270 io_in_3v3[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2271 vssa2 ro_complete_buffered_0/tapered_buf_0/out 69.90fF
-C2272 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/out 5.71fF
-C2273 gpio_noesd[6] ro_complete_buffered_0/tapered_buf_0/out 5.70fF
-C2274 io_in_3v3[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2275 io_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2276 io_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2277 io_oeb[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
-C2278 vccd1 ro_complete_buffered_0/tapered_buf_0/out 39.84fF
-C2279 vccd2 ro_complete_buffered_0/tapered_buf_0/out 70.00fF
-C2280 io_analog[0] ro_complete_buffered_0/tapered_buf_0/out 19.99fF
-C2281 io_analog[1] ro_complete_buffered_0/tapered_buf_0/out 13.17fF
-C2282 io_analog[2] ro_complete_buffered_0/tapered_buf_0/out 12.57fF
-C2283 io_clamp_high[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2284 io_clamp_low[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2285 io_clamp_high[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2286 io_clamp_low[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2287 io_clamp_high[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2288 io_clamp_low[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
-C2289 user_irq[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2290 user_irq[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2291 user_irq[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2292 user_clock2 ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2293 la_oenb[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2294 la_data_out[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2295 la_data_in[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2296 la_oenb[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2297 la_data_out[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2298 la_data_in[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2299 la_oenb[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2300 la_data_out[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2301 la_data_in[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2302 la_oenb[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2303 la_data_out[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2304 la_data_in[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2305 la_oenb[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2306 la_data_out[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2307 la_data_in[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2308 la_oenb[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2309 la_data_out[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2310 la_data_in[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2311 la_oenb[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2312 la_data_out[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2313 la_data_in[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2314 la_oenb[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2315 la_data_out[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2316 la_data_in[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2317 la_oenb[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2318 la_data_out[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2319 la_data_in[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2320 la_oenb[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2321 la_data_out[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2322 la_data_in[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2323 la_oenb[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2324 la_data_out[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2325 la_data_in[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2326 la_oenb[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2327 la_data_out[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2328 la_data_in[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2329 la_oenb[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2330 la_data_out[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2331 la_data_in[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2332 la_oenb[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2333 la_data_out[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2334 la_data_in[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2335 la_oenb[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2336 la_data_out[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2337 la_data_in[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2338 la_oenb[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2339 la_data_out[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2340 la_data_in[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2341 la_oenb[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2342 la_data_out[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2343 la_data_in[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2344 la_oenb[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2345 la_data_out[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2346 la_data_in[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2347 la_oenb[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2348 la_data_out[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2349 la_data_in[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2350 la_oenb[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2351 la_data_out[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2352 la_data_in[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2353 la_oenb[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2354 la_data_out[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2355 la_data_in[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2356 la_oenb[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2357 la_data_out[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2358 la_data_in[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2359 la_oenb[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2360 la_data_out[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2361 la_data_in[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2362 la_oenb[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2363 la_data_out[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2364 la_data_in[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2365 la_oenb[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2366 la_data_out[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2367 la_data_in[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2368 la_oenb[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2369 la_data_out[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2370 la_data_in[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2371 la_oenb[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2372 la_data_out[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2373 la_data_in[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2374 la_oenb[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2375 la_data_out[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2376 la_data_in[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2377 la_oenb[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2378 la_data_out[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2379 la_data_in[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2380 la_oenb[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2381 la_data_out[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2382 la_data_in[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2383 la_oenb[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2384 la_data_out[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2385 la_data_in[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2386 la_oenb[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2387 la_data_out[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2388 la_data_in[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2389 la_oenb[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2390 la_data_out[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2391 la_data_in[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2392 la_oenb[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2393 la_data_out[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2394 la_data_in[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2395 la_oenb[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2396 la_data_out[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2397 la_data_in[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2398 la_oenb[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2399 la_data_out[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2400 la_data_in[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2401 la_oenb[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2402 la_data_out[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2403 la_data_in[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2404 la_oenb[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2405 la_data_out[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2406 la_data_in[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2407 la_oenb[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2408 la_data_out[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2409 la_data_in[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2410 la_oenb[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2411 la_data_out[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2412 la_data_in[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2413 la_oenb[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2414 la_data_out[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2415 la_data_in[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2416 la_oenb[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2417 la_data_out[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2418 la_data_in[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2419 la_oenb[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2420 la_data_out[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2421 la_data_in[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2422 la_oenb[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2423 la_data_out[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2424 la_data_in[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2425 la_oenb[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2426 la_data_out[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2427 la_data_in[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2428 la_oenb[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2429 la_data_out[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2430 la_data_in[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2431 la_oenb[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2432 la_data_out[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2433 la_data_in[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2434 la_oenb[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2435 la_data_out[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2436 la_data_in[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2437 la_oenb[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2438 la_data_out[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2439 la_data_in[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2440 la_oenb[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2441 la_data_out[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2442 la_data_in[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2443 la_oenb[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2444 la_data_out[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2445 la_data_in[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2446 la_oenb[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2447 la_data_out[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2448 la_data_in[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2449 la_oenb[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2450 la_data_out[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2451 la_data_in[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2452 la_oenb[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2453 la_data_out[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2454 la_data_in[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2455 la_oenb[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2456 la_data_out[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2457 la_data_in[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2458 la_oenb[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2459 la_data_out[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2460 la_data_in[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2461 la_oenb[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2462 la_data_out[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2463 la_data_in[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2464 la_oenb[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2465 la_data_out[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2466 la_data_in[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2467 la_oenb[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2468 la_data_out[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2469 la_data_in[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2470 la_oenb[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2471 la_data_out[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2472 la_data_in[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2473 la_oenb[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2474 la_data_out[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2475 la_data_in[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2476 la_oenb[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2477 la_data_out[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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-C2479 la_oenb[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2480 la_data_out[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2481 la_data_in[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2482 la_oenb[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2483 la_data_out[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2484 la_data_in[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2485 la_oenb[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2486 la_data_out[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2487 la_data_in[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2488 la_oenb[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2489 la_data_out[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2490 la_data_in[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2491 la_oenb[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2492 la_data_out[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2493 la_data_in[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2494 la_oenb[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2495 la_data_out[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2496 la_data_in[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2497 la_oenb[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2498 la_data_out[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2499 la_data_in[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2500 la_oenb[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2501 la_data_out[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2502 la_data_in[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2503 la_oenb[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2504 la_data_out[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2505 la_data_in[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2506 la_oenb[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2507 la_data_out[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2508 la_data_in[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2509 la_oenb[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2510 la_data_out[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2511 la_data_in[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2512 la_oenb[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2513 la_data_out[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2514 la_data_in[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2515 la_oenb[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2516 la_data_out[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2517 la_data_in[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2518 la_oenb[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2519 la_data_out[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2520 la_data_in[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2521 la_oenb[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2522 la_data_out[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2523 la_data_in[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2524 la_oenb[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2525 la_data_out[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2526 la_data_in[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2527 la_oenb[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2528 la_data_out[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2529 la_data_in[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2530 la_oenb[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2531 la_data_out[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2532 la_data_in[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2533 la_oenb[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2534 la_data_out[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2535 la_data_in[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2536 la_oenb[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2537 la_data_out[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2538 la_data_in[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2539 la_oenb[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2540 la_data_out[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2541 la_data_in[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2542 la_oenb[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2543 la_data_out[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2544 la_data_in[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2545 la_oenb[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2546 la_data_out[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2547 la_data_in[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2548 la_oenb[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2549 la_data_out[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2550 la_data_in[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2551 la_oenb[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2552 la_data_out[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2553 la_data_in[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2554 la_oenb[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2555 la_data_out[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2556 la_data_in[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2557 la_oenb[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2558 la_data_out[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2559 la_data_in[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2560 la_oenb[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2561 la_data_out[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2562 la_data_in[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2563 la_oenb[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2564 la_data_out[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2565 la_data_in[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2566 la_oenb[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2567 la_data_out[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2568 la_data_in[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2569 la_oenb[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2570 la_data_out[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2571 la_data_in[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2572 la_oenb[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2573 la_data_out[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2574 la_data_in[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2575 la_oenb[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2576 la_data_out[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2577 la_data_in[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2578 la_oenb[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2579 la_data_out[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2580 la_data_in[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2581 la_oenb[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2582 la_data_out[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2583 la_data_in[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2584 la_oenb[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2585 la_data_out[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2586 la_data_in[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2587 la_oenb[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2588 la_data_out[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2589 la_data_in[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2590 la_oenb[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2591 la_data_out[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2592 la_data_in[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2593 la_oenb[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2594 la_data_out[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2595 la_data_in[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2596 la_oenb[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2597 la_data_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2598 la_data_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2599 la_oenb[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2600 la_data_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2601 la_data_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2602 la_oenb[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2603 la_data_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2604 la_data_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2605 la_oenb[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2606 la_data_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2607 la_data_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2608 la_oenb[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2609 la_data_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2610 la_data_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2611 la_oenb[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2612 la_data_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2613 la_data_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2614 la_oenb[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2615 la_data_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2616 la_data_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2617 la_oenb[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2618 la_data_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2619 la_data_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2620 la_oenb[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2621 la_data_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2622 la_data_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2623 la_oenb[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2624 la_data_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2625 la_data_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2626 la_oenb[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2627 la_data_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2628 la_data_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2629 la_oenb[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2630 la_data_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2631 la_data_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2632 la_oenb[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2633 la_data_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2634 la_data_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2635 la_oenb[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2636 la_data_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2637 la_data_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2638 la_oenb[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2639 la_data_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2640 la_data_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2641 la_oenb[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2642 la_data_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2643 la_data_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2644 la_oenb[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2645 la_data_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2646 la_data_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2647 la_oenb[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2648 la_data_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2649 la_data_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2650 la_oenb[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2651 la_data_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2652 la_data_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2653 la_oenb[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2654 la_data_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2655 la_data_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2656 la_oenb[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2657 la_data_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2658 la_data_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2659 la_oenb[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2660 la_data_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2661 la_data_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2662 la_oenb[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2663 la_data_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2664 la_data_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2665 la_oenb[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2666 la_data_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2667 la_data_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2668 la_oenb[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2669 la_data_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2670 la_data_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2671 la_oenb[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2672 la_data_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2673 la_data_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2674 la_oenb[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2675 la_data_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2676 la_data_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2677 wbs_dat_o[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2678 wbs_dat_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2679 wbs_adr_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2680 wbs_dat_o[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2681 wbs_dat_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2682 wbs_adr_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2683 wbs_dat_o[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2684 wbs_dat_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2685 wbs_adr_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2686 wbs_dat_o[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2687 wbs_dat_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2688 wbs_adr_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2689 wbs_dat_o[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2690 wbs_dat_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2691 wbs_adr_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2692 wbs_dat_o[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2693 wbs_dat_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2694 wbs_adr_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2695 wbs_dat_o[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2696 wbs_dat_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2697 wbs_adr_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2698 wbs_dat_o[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2699 wbs_dat_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2700 wbs_adr_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2701 wbs_dat_o[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2702 wbs_dat_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2703 wbs_adr_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2704 wbs_dat_o[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2705 wbs_dat_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2706 wbs_adr_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2707 wbs_dat_o[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2708 wbs_dat_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2709 wbs_adr_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2710 wbs_dat_o[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2711 wbs_dat_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2712 wbs_adr_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2713 wbs_dat_o[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2714 wbs_dat_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2715 wbs_adr_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2716 wbs_dat_o[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2717 wbs_dat_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2718 wbs_adr_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2719 wbs_dat_o[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2720 wbs_dat_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2721 wbs_adr_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2722 wbs_dat_o[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2723 wbs_dat_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2724 wbs_adr_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2725 wbs_dat_o[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2726 wbs_dat_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2727 wbs_adr_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2728 wbs_dat_o[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2729 wbs_dat_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2730 wbs_adr_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2731 wbs_dat_o[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2732 wbs_dat_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2733 wbs_adr_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2734 wbs_dat_o[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2735 wbs_dat_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2736 wbs_adr_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2737 wbs_dat_o[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2738 wbs_dat_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2739 wbs_adr_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2740 wbs_dat_o[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2741 wbs_dat_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2742 wbs_adr_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2743 wbs_dat_o[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2744 wbs_dat_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2745 wbs_adr_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2746 wbs_dat_o[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2747 wbs_dat_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2748 wbs_adr_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2749 wbs_dat_o[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2750 wbs_dat_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2751 wbs_adr_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2752 wbs_dat_o[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2753 wbs_dat_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2754 wbs_adr_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2755 wbs_dat_o[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2756 wbs_dat_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2757 wbs_adr_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2758 wbs_dat_o[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2759 wbs_dat_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2760 wbs_adr_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2761 wbs_sel_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2762 wbs_dat_o[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2763 wbs_dat_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2764 wbs_adr_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2765 wbs_sel_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2766 wbs_dat_o[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2767 wbs_dat_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2768 wbs_adr_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2769 wbs_sel_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2770 wbs_dat_o[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2771 wbs_dat_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2772 wbs_adr_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2773 wbs_sel_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2774 wbs_dat_o[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2775 wbs_dat_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2776 wbs_adr_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2777 wbs_we_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2778 wbs_stb_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2779 wbs_cyc_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2780 wbs_ack_o ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2781 wb_rst_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2782 wb_clk_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
-C2783 gpio_noesd[12] ro_complete_buffered_0/tapered_buf_0/out 477.73fF
-C2784 div_pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2785 div_pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2786 div_pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2787 div_pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2788 div_pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2789 div_pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2790 div_pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2791 div_pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2792 div_pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2793 div_pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2794 div_pd_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
-C2795 div_pd_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
-C2796 div_pd_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
-C2797 div_pd_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
-C2798 div_pd_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2799 div_pd_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2800 div_pd_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2801 div_pd_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2802 div_pd_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.37fF
-C2803 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2804 div_pd_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2805 div_pd_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C2806 div_pd_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2807 div_pd_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2808 div_pd_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2809 div_pd_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
-C2810 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C2811 div_pd_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2812 div_pd_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C2813 div_pd_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2814 div_pd_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2815 div_pd_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2816 div_pd_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
-C2817 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C2818 div_pd_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 399.62fF
-C2819 div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C2820 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C2821 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.64fF
-C2822 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C2823 div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C2824 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C2825 div_pd_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
-C2826 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2827 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2828 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2829 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2830 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2831 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C2832 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2833 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2834 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C2835 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2836 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2837 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C2838 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2839 div_pd_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C2840 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2841 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2842 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2843 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C2844 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C2845 div_pd_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2846 div_pd_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2847 div_pd_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.39fF
-C2848 div_pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 6.33fF
-C2849 div_pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C2850 div_pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C2851 div_pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C2852 div_pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C2853 div_pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C2854 div_pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C2855 div_pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C2856 div_pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C2857 div_pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 9.05fF
-C2858 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2859 div_pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C2860 div_pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 6.57fF
-C2861 div_pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C2862 div_pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C2863 div_pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C2864 div_pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C2865 div_pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C2866 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C2867 div_pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C2868 div_pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 392.16fF
-C2869 gpio_noesd[13] ro_complete_buffered_0/tapered_buf_0/out 498.78fF
-C2870 div_pd_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2871 div_pd_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2872 div_pd_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2873 div_pd_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2874 div_pd_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2875 div_pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2876 div_pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2877 div_pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2878 div_pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2879 div_pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2880 gpio_analog[10] ro_complete_buffered_0/tapered_buf_0/out 79.52fF
-C2881 div_pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2882 div_pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2883 div_pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2884 div_pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2885 div_pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2886 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C2887 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2888 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2889 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2890 ro_complete_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2891 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C2892 ro_complete_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2893 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2894 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2895 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2896 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2897 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.26fF
-C2898 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
-C2899 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
-C2900 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
-C2901 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.48fF
-C2902 ro_complete_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
-C2903 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C2904 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C2905 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C2906 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C2907 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2908 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C2909 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/tapered_buf_0/out 26.79fF
-C2910 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C2911 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.45fF
-C2912 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C2913 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.13fF
-C2914 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C2915 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.70fF
-C2916 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C2917 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.26fF
-C2918 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2919 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.93fF
-C2920 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C2921 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.79fF
-C2922 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
-C2923 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C2924 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C2925 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C2926 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C2927 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2928 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C2929 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2930 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2931 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2932 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2933 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2934 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2935 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2936 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2937 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2938 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2939 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2940 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2941 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2942 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2943 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2944 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2945 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2946 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2947 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2948 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2949 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2950 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2951 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2952 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2953 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2954 divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C2955 divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C2956 divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C2957 divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C2958 divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C2959 divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 652.05fF
-C2960 divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 5.57fF
-C2961 divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
-C2962 divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
-C2963 divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
-C2964 divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
-C2965 divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2966 divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 7.56fF
-C2967 divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
-C2968 divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
-C2969 divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C2970 divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 5.34fF
-C2971 divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING
-C2972 divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2973 divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 1.79fF
-C2974 divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
-C2975 divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
-C2976 divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C2977 divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.23fF
-C2978 divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING
-C2979 divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C2980 divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.45fF
-C2981 divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.65fF
-C2982 divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.09fF
-C2983 divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.22fF
-C2984 divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.53fF
-C2985 divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.34fF **FLOATING
-C2986 divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 398.00fF
-C2987 divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.43fF
-C2988 divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 3.07fF
-C2989 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 2.81fF
-C2990 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 4.60fF
-C2991 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C2992 divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C2993 divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
-C2994 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C2995 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C2996 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C2997 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C2998 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C2999 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3000 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.41fF
-C3001 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.83fF
-C3002 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C3003 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.33fF **FLOATING
-C3004 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.78fF **FLOATING
-C3005 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.13fF
-C3006 divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 5.50fF
-C3007 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.37fF
-C3008 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.81fF
-C3009 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.16fF
-C3010 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3011 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.59fF **FLOATING
-C3012 divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3013 divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3014 divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.27fF
-C3015 divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3016 divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3017 divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3018 divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3019 divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3020 divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3021 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
-C3022 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
-C3023 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
-C3024 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
-C3025 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3026 pll_full_buffered2_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 33.25fF
-C3027 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3028 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3029 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3030 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
-C3031 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3032 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3033 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3034 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3035 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3036 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3037 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
-C3038 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3039 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3040 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C3041 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3042 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3043 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3044 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
-C3045 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3046 pll_full_buffered2_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 35.58fF
-C3047 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3048 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C3049 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
-C3050 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C3051 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3052 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3053 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
-C3054 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3055 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3056 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
-C3057 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3058 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
-C3059 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3060 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3061 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3062 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C3063 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3064 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3065 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C3066 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3067 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C3068 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3069 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3070 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3071 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C3072 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3073 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3074 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3075 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
-C3076 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3077 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3078 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3079 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3080 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3081 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3082 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3083 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
-C3084 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3085 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
-C3086 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3087 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
-C3088 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3089 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
-C3090 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3091 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
-C3092 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3093 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
-C3094 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
-C3095 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3096 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3097 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3098 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3099 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3100 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3101 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
-C3102 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
-C3103 pll_full_buffered2_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
-C3104 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3105 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
-C3106 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3107 pll_full_buffered2_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
-C3108 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
-C3109 pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
-C3110 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
-C3111 pll_full_buffered2_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
-C3112 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C3113 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C3114 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3115 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3116 pll_full_buffered2_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C3117 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C3118 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3119 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3120 pll_full_buffered2_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 25.17fF
-C3121 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3122 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3123 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3124 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3125 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C3126 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3127 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3128 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3129 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3130 pll_full_buffered2_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 390.59fF
-C3131 pll_full_buffered2_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 35.09fF
-C3132 pll_full_buffered2_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3133 pll_full_buffered2_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3134 pll_full_buffered2_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3135 pll_full_buffered2_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3136 pll_full_buffered2_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3137 io_analog[10] ro_complete_buffered_0/tapered_buf_0/out 463.31fF
-C3138 pll_full_buffered2_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C3139 pll_full_buffered2_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3140 pll_full_buffered2_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3141 pll_full_buffered2_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3142 pll_full_buffered2_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3143 io_analog[9] ro_complete_buffered_0/tapered_buf_0/out 841.04fF
-C3144 gpio_noesd[7] ro_complete_buffered_0/tapered_buf_0/out 658.30fF
-C3145 pll_full_buffered2_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3146 pll_full_buffered2_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3147 pll_full_buffered2_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3148 pll_full_buffered2_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3149 pll_full_buffered2_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3150 pll_full_buffered2_0/tapered_buf_5/in ro_complete_buffered_0/tapered_buf_0/out 4.76fF
-C3151 pll_full_buffered2_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.89fF
-C3152 pll_full_buffered2_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3153 pll_full_buffered2_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3154 pll_full_buffered2_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3155 pll_full_buffered2_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3156 pll_full_buffered2_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3157 pll_full_buffered2_0/tapered_buf_4/in ro_complete_buffered_0/tapered_buf_0/out 2.90fF
-C3158 pll_full_buffered2_0/tapered_buf_3/out ro_complete_buffered_0/tapered_buf_0/out 385.95fF
-C3159 pll_full_buffered2_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3160 pll_full_buffered2_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3161 pll_full_buffered2_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3162 pll_full_buffered2_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3163 pll_full_buffered2_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3164 gpio_noesd[8] ro_complete_buffered_0/tapered_buf_0/out 593.58fF
-C3165 pll_full_buffered2_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3166 pll_full_buffered2_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3167 pll_full_buffered2_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3168 pll_full_buffered2_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3169 pll_full_buffered2_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3170 ro_divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C3171 ro_divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3172 ro_divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3173 ro_divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3174 ro_divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3175 ro_divider_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3176 ro_divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3177 ro_divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3178 ro_divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3179 ro_divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3180 ro_divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3181 ro_divider_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3182 ro_divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
-C3183 ro_divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
-C3184 ro_divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
-C3185 ro_divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
-C3186 ro_divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3187 ro_divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 399.57fF
-C3188 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3189 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3190 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3191 ro_divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF
-C3192 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3193 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3194 ro_divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3195 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3196 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3197 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3198 ro_divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
-C3199 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3200 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3201 ro_divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C3202 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3203 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3204 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3205 ro_divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
-C3206 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3207 ro_divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 23.46fF
-C3208 ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3209 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C3210 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.69fF
-C3211 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C3212 ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3213 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3214 ro_divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
-C3215 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3216 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3217 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3218 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3219 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3220 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3221 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3222 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3223 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C3224 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3225 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3226 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C3227 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3228 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C3229 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3230 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3231 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3232 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C3233 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3234 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3235 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3236 ro_divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 397.55fF
-C3237 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
-C3238 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3239 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3240 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3241 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3242 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3243 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3244 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3245 ro_divider_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.44fF
-C3246 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3247 ro_divider_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.08fF
-C3248 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3249 ro_divider_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.75fF
-C3250 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3251 ro_divider_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.13fF
-C3252 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3253 ro_divider_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.91fF
-C3254 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3255 ro_divider_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.69fF
-C3256 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
-C3257 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3258 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3259 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3260 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3261 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3262 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3263 ro_divider_buffered_0/tapered_buf_8/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3264 ro_divider_buffered_0/tapered_buf_8/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3265 ro_divider_buffered_0/tapered_buf_8/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3266 ro_divider_buffered_0/tapered_buf_8/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3267 ro_divider_buffered_0/tapered_buf_8/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3268 io_analog[4] ro_complete_buffered_0/tapered_buf_0/out 241.82fF
-C3269 ro_divider_buffered_0/tapered_buf_7/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3270 ro_divider_buffered_0/tapered_buf_7/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3271 ro_divider_buffered_0/tapered_buf_7/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3272 ro_divider_buffered_0/tapered_buf_7/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3273 ro_divider_buffered_0/tapered_buf_7/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3274 io_analog[5] ro_complete_buffered_0/tapered_buf_0/out 328.44fF
-C3275 ro_divider_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3276 ro_divider_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3277 ro_divider_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3278 ro_divider_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3279 ro_divider_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3280 io_analog[6] ro_complete_buffered_0/tapered_buf_0/out 372.19fF
-C3281 ro_divider_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3282 ro_divider_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3283 ro_divider_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3284 ro_divider_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3285 ro_divider_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3286 io_analog[7] ro_complete_buffered_0/tapered_buf_0/out 410.44fF
-C3287 ro_divider_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3288 ro_divider_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3289 ro_divider_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3290 ro_divider_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3291 ro_divider_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3292 io_analog[8] ro_complete_buffered_0/tapered_buf_0/out 460.22fF
-C3293 ro_divider_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3294 ro_divider_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3295 ro_divider_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3296 ro_divider_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3297 ro_divider_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3298 io_analog[3] ro_complete_buffered_0/tapered_buf_0/out 151.29fF
-C3299 ro_divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3300 ro_divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3301 ro_divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3302 ro_divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3303 ro_divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3304 ro_divider_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3305 gpio_analog[17] ro_complete_buffered_0/tapered_buf_0/out 525.65fF
-C3306 filter_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3307 filter_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3308 filter_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3309 filter_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3310 filter_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3311 filter_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3312 filter_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3313 filter_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3314 filter_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3315 filter_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3316 filter_buffered_0/filter_0/v ro_complete_buffered_0/tapered_buf_0/out 476.79fF
-C3317 filter_buffered_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.47fF **FLOATING
-C3318 filter_buffered_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.03fF **FLOATING
-C3319 cp_buffered_0/cp_0/down ro_complete_buffered_0/tapered_buf_0/out 397.14fF
-C3320 cp_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3321 cp_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3322 cp_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3323 cp_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3324 cp_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3325 gpio_analog[8] ro_complete_buffered_0/tapered_buf_0/out 87.11fF
-C3326 gpio_noesd[9] ro_complete_buffered_0/tapered_buf_0/out 504.39fF
-C3327 cp_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3328 cp_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3329 cp_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3330 cp_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3331 cp_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3332 cp_buffered_0/cp_0/out ro_complete_buffered_0/tapered_buf_0/out 11.85fF
-C3333 cp_buffered_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 393.41fF
-C3334 cp_buffered_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3335 cp_buffered_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
-C3336 cp_buffered_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3337 cp_buffered_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
-C3338 cp_buffered_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 1.65fF **FLOATING
-C3339 cp_buffered_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 5.76fF **FLOATING
-C3340 cp_buffered_0/cp_0/a_1710_n2840# ro_complete_buffered_0/tapered_buf_0/out 5.24fF **FLOATING
-C3341 cp_buffered_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 3.19fF **FLOATING
-C3342 cp_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3343 cp_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3344 cp_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3345 cp_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3346 cp_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3347 gpio_analog[7] ro_complete_buffered_0/tapered_buf_0/out 68.61fF
-C3348 ashish_0/b ro_complete_buffered_0/tapered_buf_0/out 3.70fF
-C3349 ashish_0/a ro_complete_buffered_0/tapered_buf_0/out 1.62fF
-C3350 ashish_0/vop ro_complete_buffered_0/tapered_buf_0/out 24.86fF
-C3351 ashish_0/von ro_complete_buffered_0/tapered_buf_0/out 23.36fF
-C3352 ashish_0/cm ro_complete_buffered_0/tapered_buf_0/out 25.70fF
-C3353 gpio_noesd[11] ro_complete_buffered_0/tapered_buf_0/out 514.87fF
-C3354 pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3355 pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3356 pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3357 pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3358 pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3359 pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3360 pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3361 pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3362 pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3363 pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3364 gpio_analog[9] ro_complete_buffered_0/tapered_buf_0/out 75.73fF
-C3365 pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 5.76fF
-C3366 pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C3367 pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C3368 pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3369 pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3370 pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C3371 pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C3372 pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3373 pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3374 pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 8.46fF
-C3375 pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3376 pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3377 pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 390.67fF
-C3378 pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3379 pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3380 pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C3381 pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3382 pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3383 pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3384 pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3385 pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 388.56fF
-C3386 pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3387 pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3388 pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3389 pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3390 pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3391 gpio_noesd[10] ro_complete_buffered_0/tapered_buf_0/out 488.71fF
-C3392 pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3393 pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3394 pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3395 pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3396 pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3397 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
-C3398 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
-C3399 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
-C3400 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
-C3401 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3402 pll_full_buffered1_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 15.26fF
-C3403 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3404 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3405 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3406 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
-C3407 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3408 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3409 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3410 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3411 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3412 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3413 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
-C3414 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3415 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3416 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
-C3417 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3418 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3419 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3420 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
-C3421 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
-C3422 pll_full_buffered1_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 45.00fF
-C3423 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3424 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
-C3425 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
-C3426 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
-C3427 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
-C3428 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
-C3429 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
-C3430 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3431 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3432 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
-C3433 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3434 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
-C3435 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3436 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3437 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3438 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
-C3439 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3440 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
-C3441 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
-C3442 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
-C3443 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
-C3444 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
-C3445 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
-C3446 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
-C3447 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
-C3448 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
-C3449 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3450 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3451 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
-C3452 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3453 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3454 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3455 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3456 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3457 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3458 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3459 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
-C3460 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3461 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
-C3462 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3463 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
-C3464 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3465 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
-C3466 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3467 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
-C3468 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3469 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
-C3470 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
-C3471 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
-C3472 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
-C3473 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
-C3474 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
-C3475 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
-C3476 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
-C3477 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
-C3478 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
-C3479 pll_full_buffered1_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
-C3480 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3481 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
-C3482 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
-C3483 pll_full_buffered1_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
-C3484 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
-C3485 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
-C3486 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
-C3487 pll_full_buffered1_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
-C3488 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
-C3489 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
-C3490 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3491 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3492 pll_full_buffered1_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
-C3493 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
-C3494 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3495 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3496 pll_full_buffered1_0/pll_full_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 7.30fF
-C3497 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3498 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3499 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
-C3500 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
-C3501 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
-C3502 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
-C3503 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
-C3504 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
-C3505 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
-C3506 pll_full_buffered1_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 391.17fF
-C3507 pll_full_buffered1_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 14.90fF
-C3508 pll_full_buffered1_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
-C3509 pll_full_buffered1_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3510 pll_full_buffered1_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3511 pll_full_buffered1_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3512 pll_full_buffered1_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3513 pll_full_buffered1_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
-C3514 pll_full_buffered1_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
-C3515 pll_full_buffered1_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
-C3516 pll_full_buffered1_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
-C3517 pll_full_buffered1_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
-C3518 pll_full_buffered1_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
-C3519 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/out ro_complete_buffered_0/tapered_buf_0/out 386.27fF
-C3520 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
-C3521 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
-C3522 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
-C3523 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.32fF
+C2190 io_in_3v3[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2191 io_oeb[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2192 io_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2193 io_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2194 io_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2195 io_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2196 io_oeb[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2197 io_in_3v3[26] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2198 io_in_3v3[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2199 io_oeb[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2200 io_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2201 io_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2202 io_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2203 io_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2204 io_oeb[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2205 io_in_3v3[25] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2206 io_in_3v3[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2207 io_oeb[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2208 io_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2209 io_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2210 io_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2211 io_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2212 io_oeb[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2213 io_in_3v3[24] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2214 io_in_3v3[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2215 gpio_noesd[17] ro_complete_buffered_0/tapered_buf_0/out 2.32fF
+C2216 io_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2217 io_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2218 io_oeb[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2219 io_in_3v3[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2220 io_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2221 io_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2222 io_oeb[4] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2223 io_in_3v3[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2224 io_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2225 io_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2226 io_oeb[5] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2227 io_oeb[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2228 io_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2229 io_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2230 io_in_3v3[23] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2231 gpio_noesd[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2232 gpio_analog[16] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2233 io_oeb[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2234 io_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2235 io_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2236 io_in_3v3[22] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2237 gpio_noesd[15] ro_complete_buffered_0/tapered_buf_0/out 2.31fF
+C2238 gpio_analog[15] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2239 io_in_3v3[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2240 io_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2241 io_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2242 io_oeb[6] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2243 io_oeb[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2244 io_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2245 io_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2246 io_in_3v3[21] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2247 vssd1 ro_complete_buffered_0/tapered_buf_0/out 13.04fF
+C2248 gpio_analog[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2249 gpio_noesd[0] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2250 io_in_3v3[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2251 io_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2252 io_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2253 io_oeb[7] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2254 gpio_analog[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2255 gpio_noesd[1] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2256 io_in_3v3[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2257 io_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2258 io_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2259 io_oeb[8] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2260 gpio_analog[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2261 gpio_noesd[2] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2262 io_in_3v3[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2263 io_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2264 io_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2265 io_oeb[9] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2266 gpio_noesd[3] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2267 io_in_3v3[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2268 io_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2269 io_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2270 io_oeb[10] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2271 io_in_3v3[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2272 io_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2273 io_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2274 io_oeb[11] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2275 io_in_3v3[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2276 io_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2277 io_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2278 io_oeb[12] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2279 gpio_analog[14] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
+C2280 vssd2 ro_complete_buffered_0/tapered_buf_0/out 25.38fF
+C2281 vdda2 ro_complete_buffered_0/tapered_buf_0/out 24.41fF
+C2282 io_oeb[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2283 io_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2284 io_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2285 io_in_3v3[20] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2286 gpio_analog[13] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2287 io_oeb[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2288 io_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2289 io_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2290 io_in_3v3[19] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2291 gpio_analog[12] ro_complete_buffered_0/tapered_buf_0/out 2.30fF
+C2292 io_oeb[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2293 io_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2294 io_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2295 io_in_3v3[18] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2296 gpio_analog[11] ro_complete_buffered_0/tapered_buf_0/out 2.29fF
+C2297 io_oeb[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2298 io_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2299 io_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2300 io_in_3v3[17] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2301 io_oeb[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2302 io_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2303 io_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2304 io_in_3v3[16] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2305 io_oeb[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2306 io_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2307 io_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2308 io_in_3v3[15] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2309 io_oeb[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2310 io_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2311 io_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2312 io_in_3v3[14] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2313 vssa2 ro_complete_buffered_0/tapered_buf_0/out 69.90fF
+C2314 gpio_noesd[6] ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2315 io_in_3v3[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2316 io_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2317 io_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2318 io_oeb[13] ro_complete_buffered_0/tapered_buf_0/out 0.61fF
+C2319 vccd1 ro_complete_buffered_0/tapered_buf_0/out 39.84fF
+C2320 vccd2 ro_complete_buffered_0/tapered_buf_0/out 70.00fF
+C2321 io_clamp_high[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2322 io_clamp_low[0] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2323 io_clamp_high[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2324 io_clamp_low[1] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2325 io_clamp_high[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2326 io_clamp_low[2] ro_complete_buffered_0/tapered_buf_0/out 3.58fF
+C2327 user_irq[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2328 user_irq[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2329 user_irq[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2330 user_clock2 ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2331 la_oenb[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2332 la_data_out[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2333 la_data_in[127] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2334 la_oenb[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2335 la_data_out[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2336 la_data_in[126] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2337 la_oenb[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2338 la_data_out[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2339 la_data_in[125] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2340 la_oenb[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2341 la_data_out[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2342 la_data_in[124] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2343 la_oenb[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2344 la_data_out[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2345 la_data_in[123] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2346 la_oenb[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2347 la_data_out[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2348 la_data_in[122] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2349 la_oenb[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2350 la_data_out[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2351 la_data_in[121] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2352 la_oenb[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2353 la_data_out[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2354 la_data_in[120] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2355 la_oenb[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2356 la_data_out[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2357 la_data_in[119] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2358 la_oenb[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2359 la_data_out[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2360 la_data_in[118] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2361 la_oenb[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2362 la_data_out[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2363 la_data_in[117] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2364 la_oenb[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2365 la_data_out[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2366 la_data_in[116] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2367 la_oenb[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2368 la_data_out[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2369 la_data_in[115] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2370 la_oenb[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2371 la_data_out[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2372 la_data_in[114] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2373 la_oenb[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2374 la_data_out[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2375 la_data_in[113] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2376 la_oenb[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2377 la_data_out[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2378 la_data_in[112] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2379 la_oenb[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2380 la_data_out[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2381 la_data_in[111] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2382 la_oenb[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2383 la_data_out[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2384 la_data_in[110] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2385 la_oenb[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2386 la_data_out[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2387 la_data_in[109] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2388 la_oenb[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2389 la_data_out[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2390 la_data_in[108] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2391 la_oenb[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2392 la_data_out[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2393 la_data_in[107] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2394 la_oenb[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2395 la_data_out[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2396 la_data_in[106] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2397 la_oenb[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2398 la_data_out[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2399 la_data_in[105] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2400 la_oenb[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2401 la_data_out[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2402 la_data_in[104] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2403 la_oenb[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2404 la_data_out[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2405 la_data_in[103] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2406 la_oenb[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2407 la_data_out[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2408 la_data_in[102] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2409 la_oenb[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2410 la_data_out[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2411 la_data_in[101] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2412 la_oenb[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2413 la_data_out[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2414 la_data_in[100] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2415 la_oenb[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2416 la_data_out[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2417 la_data_in[99] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2418 la_oenb[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2419 la_data_out[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2420 la_data_in[98] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2421 la_oenb[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2422 la_data_out[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2423 la_data_in[97] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2424 la_oenb[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2425 la_data_out[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2426 la_data_in[96] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2427 la_oenb[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2428 la_data_out[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2429 la_data_in[95] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2430 la_oenb[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2431 la_data_out[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2432 la_data_in[94] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2433 la_oenb[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2434 la_data_out[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2435 la_data_in[93] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2436 la_oenb[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2437 la_data_out[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2438 la_data_in[92] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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+C2440 la_data_out[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2441 la_data_in[91] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2442 la_oenb[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2443 la_data_out[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2444 la_data_in[90] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2445 la_oenb[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2446 la_data_out[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2447 la_data_in[89] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2448 la_oenb[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2449 la_data_out[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2450 la_data_in[88] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2451 la_oenb[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2452 la_data_out[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2453 la_data_in[87] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2454 la_oenb[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2455 la_data_out[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2456 la_data_in[86] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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+C2458 la_data_out[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2459 la_data_in[85] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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+C2461 la_data_out[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2462 la_data_in[84] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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+C2464 la_data_out[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2465 la_data_in[83] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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+C2467 la_data_out[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2468 la_data_in[82] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
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+C2470 la_data_out[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2471 la_data_in[81] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2472 la_oenb[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2473 la_data_out[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2474 la_data_in[80] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2475 la_oenb[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2476 la_data_out[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2477 la_data_in[79] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2478 la_oenb[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2479 la_data_out[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2480 la_data_in[78] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2481 la_oenb[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2482 la_data_out[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2483 la_data_in[77] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2484 la_oenb[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2485 la_data_out[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2486 la_data_in[76] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2487 la_oenb[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2488 la_data_out[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2489 la_data_in[75] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2490 la_oenb[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2491 la_data_out[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2492 la_data_in[74] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2493 la_oenb[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2494 la_data_out[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2495 la_data_in[73] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2496 la_oenb[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2497 la_data_out[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2498 la_data_in[72] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2499 la_oenb[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2500 la_data_out[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2501 la_data_in[71] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2502 la_oenb[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2503 la_data_out[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2504 la_data_in[70] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2505 la_oenb[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2506 la_data_out[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2507 la_data_in[69] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2508 la_oenb[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2509 la_data_out[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2510 la_data_in[68] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2511 la_oenb[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2512 la_data_out[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2513 la_data_in[67] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2514 la_oenb[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2515 la_data_out[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2516 la_data_in[66] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2517 la_oenb[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2518 la_data_out[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2519 la_data_in[65] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2520 la_oenb[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2521 la_data_out[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2522 la_data_in[64] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2523 la_oenb[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2524 la_data_out[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2525 la_data_in[63] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2526 la_oenb[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2527 la_data_out[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2528 la_data_in[62] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2529 la_oenb[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2530 la_data_out[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2531 la_data_in[61] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2532 la_oenb[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2533 la_data_out[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2534 la_data_in[60] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2535 la_oenb[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2536 la_data_out[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2537 la_data_in[59] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2538 la_oenb[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2539 la_data_out[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2540 la_data_in[58] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2541 la_oenb[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2542 la_data_out[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2543 la_data_in[57] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2544 la_oenb[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2545 la_data_out[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2546 la_data_in[56] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2547 la_oenb[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2548 la_data_out[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2549 la_data_in[55] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2550 la_oenb[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2551 la_data_out[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2552 la_data_in[54] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2553 la_oenb[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2554 la_data_out[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2555 la_data_in[53] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2556 la_oenb[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2557 la_data_out[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2558 la_data_in[52] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2559 la_oenb[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2560 la_data_out[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2561 la_data_in[51] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2562 la_oenb[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2563 la_data_out[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2564 la_data_in[50] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2565 la_oenb[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2566 la_data_out[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2567 la_data_in[49] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2568 la_oenb[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2569 la_data_out[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2570 la_data_in[48] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2571 la_oenb[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2572 la_data_out[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2573 la_data_in[47] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2574 la_oenb[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2575 la_data_out[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2576 la_data_in[46] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2577 la_oenb[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2578 la_data_out[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2579 la_data_in[45] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2580 la_oenb[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2581 la_data_out[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2582 la_data_in[44] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2583 la_oenb[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2584 la_data_out[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2585 la_data_in[43] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2586 la_oenb[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2587 la_data_out[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2588 la_data_in[42] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2589 la_oenb[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2590 la_data_out[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2591 la_data_in[41] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2592 la_oenb[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2593 la_data_out[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2594 la_data_in[40] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2595 la_oenb[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2596 la_data_out[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2597 la_data_in[39] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2598 la_oenb[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2599 la_data_out[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2600 la_data_in[38] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2601 la_oenb[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2602 la_data_out[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2603 la_data_in[37] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2604 la_oenb[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2605 la_data_out[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2606 la_data_in[36] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2607 la_oenb[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2608 la_data_out[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2609 la_data_in[35] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2610 la_oenb[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2611 la_data_out[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2612 la_data_in[34] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2613 la_oenb[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2614 la_data_out[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2615 la_data_in[33] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2616 la_oenb[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2617 la_data_out[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2618 la_data_in[32] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2619 la_oenb[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2620 la_data_out[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2621 la_data_in[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2622 la_oenb[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2623 la_data_out[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2624 la_data_in[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2625 la_oenb[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2626 la_data_out[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2627 la_data_in[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2628 la_oenb[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2629 la_data_out[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2630 la_data_in[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2631 la_oenb[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2632 la_data_out[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2633 la_data_in[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2634 la_oenb[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2635 la_data_out[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2636 la_data_in[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2637 la_oenb[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2638 la_data_out[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2639 la_data_in[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2640 la_oenb[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2641 la_data_out[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2642 la_data_in[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2643 la_oenb[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2644 la_data_out[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2645 la_data_in[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2646 la_oenb[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2647 la_data_out[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2648 la_data_in[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2649 la_oenb[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2650 la_data_out[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2651 la_data_in[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2652 la_oenb[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2653 la_data_out[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2654 la_data_in[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2655 la_oenb[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2656 la_data_out[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2657 la_data_in[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2658 la_oenb[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2659 la_data_out[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2660 la_data_in[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2661 la_oenb[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2662 la_data_out[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2663 la_data_in[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2664 la_oenb[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2665 la_data_out[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2666 la_data_in[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2667 la_oenb[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2668 la_data_out[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2669 la_data_in[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2670 la_oenb[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2671 la_data_out[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2672 la_data_in[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2673 la_oenb[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2674 la_data_out[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2675 la_data_in[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2676 la_oenb[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2677 la_data_out[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2678 la_data_in[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2679 la_oenb[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2680 la_data_out[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2681 la_data_in[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2682 la_oenb[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2683 la_data_out[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2684 la_data_in[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2685 la_oenb[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2686 la_data_out[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2687 la_data_in[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2688 la_oenb[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2689 la_data_out[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2690 la_data_in[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2691 la_oenb[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2692 la_data_out[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2693 la_data_in[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2694 la_oenb[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2695 la_data_out[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2696 la_data_in[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2697 la_oenb[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2698 la_data_out[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2699 la_data_in[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2700 la_oenb[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2701 la_data_out[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2702 la_data_in[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2703 la_oenb[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2704 la_data_out[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2705 la_data_in[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2706 la_oenb[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2707 la_data_out[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2708 la_data_in[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2709 la_oenb[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2710 la_data_out[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2711 la_data_in[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2712 la_oenb[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2713 la_data_out[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2714 la_data_in[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2715 wbs_dat_o[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2716 wbs_dat_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2717 wbs_adr_i[31] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2718 wbs_dat_o[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2719 wbs_dat_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2720 wbs_adr_i[30] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2721 wbs_dat_o[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2722 wbs_dat_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2723 wbs_adr_i[29] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2724 wbs_dat_o[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2725 wbs_dat_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2726 wbs_adr_i[28] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2727 wbs_dat_o[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2728 wbs_dat_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2729 wbs_adr_i[27] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2730 wbs_dat_o[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2731 wbs_dat_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2732 wbs_adr_i[26] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2733 wbs_dat_o[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2734 wbs_dat_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2735 wbs_adr_i[25] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2736 wbs_dat_o[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2737 wbs_dat_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2738 wbs_adr_i[24] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2739 wbs_dat_o[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2740 wbs_dat_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2741 wbs_adr_i[23] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2742 wbs_dat_o[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2743 wbs_dat_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2744 wbs_adr_i[22] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2745 wbs_dat_o[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2746 wbs_dat_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2747 wbs_adr_i[21] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2748 wbs_dat_o[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2749 wbs_dat_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2750 wbs_adr_i[20] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2751 wbs_dat_o[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2752 wbs_dat_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2753 wbs_adr_i[19] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2754 wbs_dat_o[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2755 wbs_dat_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2756 wbs_adr_i[18] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2757 wbs_dat_o[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2758 wbs_dat_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2759 wbs_adr_i[17] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2760 wbs_dat_o[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2761 wbs_dat_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2762 wbs_adr_i[16] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2763 wbs_dat_o[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2764 wbs_dat_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2765 wbs_adr_i[15] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2766 wbs_dat_o[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2767 wbs_dat_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2768 wbs_adr_i[14] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2769 wbs_dat_o[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2770 wbs_dat_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2771 wbs_adr_i[13] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2772 wbs_dat_o[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2773 wbs_dat_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2774 wbs_adr_i[12] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2775 wbs_dat_o[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2776 wbs_dat_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2777 wbs_adr_i[11] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2778 wbs_dat_o[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2779 wbs_dat_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2780 wbs_adr_i[10] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2781 wbs_dat_o[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2782 wbs_dat_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2783 wbs_adr_i[9] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2784 wbs_dat_o[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2785 wbs_dat_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2786 wbs_adr_i[8] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2787 wbs_dat_o[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2788 wbs_dat_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2789 wbs_adr_i[7] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2790 wbs_dat_o[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2791 wbs_dat_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2792 wbs_adr_i[6] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2793 wbs_dat_o[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2794 wbs_dat_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2795 wbs_adr_i[5] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2796 wbs_dat_o[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2797 wbs_dat_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2798 wbs_adr_i[4] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2799 wbs_sel_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2800 wbs_dat_o[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2801 wbs_dat_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2802 wbs_adr_i[3] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2803 wbs_sel_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2804 wbs_dat_o[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2805 wbs_dat_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2806 wbs_adr_i[2] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2807 wbs_sel_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2808 wbs_dat_o[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2809 wbs_dat_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2810 wbs_adr_i[1] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2811 wbs_sel_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2812 wbs_dat_o[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2813 wbs_dat_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2814 wbs_adr_i[0] ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2815 wbs_we_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2816 wbs_stb_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2817 wbs_cyc_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2818 wbs_ack_o ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2819 wb_rst_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2820 wb_clk_i ro_complete_buffered_0/tapered_buf_0/out 0.63fF
+C2821 gpio_noesd[12] ro_complete_buffered_0/tapered_buf_0/out 476.99fF
+C2822 div_pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2823 div_pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2824 div_pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2825 div_pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2826 div_pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2827 div_pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2828 div_pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2829 div_pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2830 div_pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2831 div_pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2832 div_pd_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
+C2833 div_pd_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
+C2834 div_pd_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
+C2835 div_pd_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
+C2836 div_pd_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2837 div_pd_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2838 div_pd_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2839 div_pd_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2840 div_pd_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.37fF
+C2841 div_pd_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2842 div_pd_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2843 div_pd_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C2844 div_pd_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2845 div_pd_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2846 div_pd_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2847 div_pd_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
+C2848 div_pd_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C2849 div_pd_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2850 div_pd_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C2851 div_pd_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2852 div_pd_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2853 div_pd_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2854 div_pd_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
+C2855 div_pd_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C2856 div_pd_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 399.62fF
+C2857 div_pd_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C2858 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C2859 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.64fF
+C2860 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C2861 div_pd_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C2862 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C2863 div_pd_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
+C2864 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2865 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2866 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2867 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2868 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2869 div_pd_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C2870 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2871 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2872 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C2873 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2874 div_pd_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C2875 div_pd_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C2876 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C2877 div_pd_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C2878 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C2879 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C2880 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C2881 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C2882 div_pd_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C2883 div_pd_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2884 div_pd_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2885 div_pd_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.39fF
+C2886 div_pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 6.33fF
+C2887 div_pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C2888 div_pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C2889 div_pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C2890 div_pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C2891 div_pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C2892 div_pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C2893 div_pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C2894 div_pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C2895 div_pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 9.05fF
+C2896 div_pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2897 div_pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C2898 div_pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 6.57fF
+C2899 div_pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C2900 div_pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C2901 div_pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C2902 div_pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C2903 div_pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C2904 div_pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C2905 div_pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C2906 div_pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 392.16fF
+C2907 gpio_noesd[13] ro_complete_buffered_0/tapered_buf_0/out 498.04fF
+C2908 div_pd_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2909 div_pd_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2910 div_pd_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2911 div_pd_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2912 div_pd_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2913 div_pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2914 div_pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2915 div_pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2916 div_pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2917 div_pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2918 gpio_analog[10] ro_complete_buffered_0/tapered_buf_0/out 78.77fF
+C2919 div_pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2920 div_pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2921 div_pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2922 div_pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2923 div_pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2924 ro_complete_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C2925 ro_complete_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2926 ro_complete_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2927 ro_complete_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2928 ro_complete_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2929 gpio_analog[6] ro_complete_buffered_0/tapered_buf_0/out 148.15fF
+C2930 ro_complete_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2931 ro_complete_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2932 ro_complete_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2933 ro_complete_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2934 ro_complete_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2935 io_analog[2] ro_complete_buffered_0/tapered_buf_0/out 449.69fF
+C2936 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
+C2937 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
+C2938 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
+C2939 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.48fF
+C2940 ro_complete_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
+C2941 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C2942 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C2943 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C2944 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C2945 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2946 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C2947 ro_complete_buffered_0/DIGITAL_BUFFER_v1_0/in ro_complete_buffered_0/tapered_buf_0/out 26.79fF
+C2948 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C2949 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.45fF
+C2950 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C2951 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.13fF
+C2952 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C2953 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.70fF
+C2954 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C2955 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.26fF
+C2956 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2957 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.93fF
+C2958 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C2959 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.79fF
+C2960 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
+C2961 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C2962 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C2963 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C2964 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C2965 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C2966 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C2967 ro_complete_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2968 ro_complete_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2969 ro_complete_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2970 ro_complete_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2971 ro_complete_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2972 ro_complete_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2973 ro_complete_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2974 ro_complete_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2975 ro_complete_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2976 ro_complete_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2977 ro_complete_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2978 ro_complete_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2979 ro_complete_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2980 ro_complete_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2981 ro_complete_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2982 ro_complete_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2983 ro_complete_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2984 ro_complete_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2985 ro_complete_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2986 ro_complete_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2987 ro_complete_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2988 ro_complete_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2989 ro_complete_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2990 ro_complete_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2991 ro_complete_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2992 divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2993 divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C2994 divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C2995 divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C2996 divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C2997 gpio_noesd[4] ro_complete_buffered_0/tapered_buf_0/out 480.56fF
+C2998 divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C2999 divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3000 divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3001 divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3002 divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3003 divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
+C3004 divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
+C3005 divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
+C3006 divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
+C3007 divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3008 divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 7.61fF
+C3009 divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3010 divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3011 divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3012 divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF
+C3013 divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3014 divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3015 divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3016 divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3017 divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3018 divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3019 divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
+C3020 divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3021 divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3022 divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3023 divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3024 divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3025 divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3026 divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
+C3027 divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3028 divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 396.07fF
+C3029 divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3030 divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3031 divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.70fF
+C3032 divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3033 divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3034 divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3035 divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
+C3036 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3037 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3038 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3039 divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3040 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3041 divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3042 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3043 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3044 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3045 divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3046 divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3047 divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3048 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3049 divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3050 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3051 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3052 divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3053 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3054 divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3055 divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3056 divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3057 divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 393.27fF
+C3058 divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3059 divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3060 divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3061 divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3062 divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3063 gpio_analog[4] ro_complete_buffered_0/tapered_buf_0/out 113.63fF
+C3064 pll_full_buffered2_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3065 pll_full_buffered2_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3066 pll_full_buffered2_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3067 pll_full_buffered2_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3068 pll_full_buffered2_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3069 io_analog[10] ro_complete_buffered_0/tapered_buf_0/out 463.13fF
+C3070 pll_full_buffered2_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C3071 pll_full_buffered2_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3072 pll_full_buffered2_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3073 pll_full_buffered2_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3074 pll_full_buffered2_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3075 io_analog[9] ro_complete_buffered_0/tapered_buf_0/out 1803.99fF
+C3076 pll_full_buffered2_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
+C3077 pll_full_buffered2_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
+C3078 pll_full_buffered2_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
+C3079 pll_full_buffered2_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
+C3080 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3081 pll_full_buffered2_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 33.25fF
+C3082 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3083 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3084 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3085 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
+C3086 pll_full_buffered2_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3087 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3088 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3089 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3090 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3091 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3092 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
+C3093 pll_full_buffered2_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3094 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3095 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3096 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3097 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3098 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3099 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
+C3100 pll_full_buffered2_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3101 pll_full_buffered2_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 35.58fF
+C3102 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3103 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3104 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
+C3105 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3106 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3107 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3108 pll_full_buffered2_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
+C3109 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3110 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3111 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
+C3112 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3113 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
+C3114 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3115 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3116 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3117 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3118 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3119 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3120 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3121 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3122 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3123 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3124 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3125 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3126 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3127 pll_full_buffered2_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3128 pll_full_buffered2_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3129 pll_full_buffered2_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3130 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
+C3131 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3132 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3133 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3134 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3135 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3136 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3137 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3138 pll_full_buffered2_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
+C3139 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3140 pll_full_buffered2_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
+C3141 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3142 pll_full_buffered2_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
+C3143 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3144 pll_full_buffered2_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
+C3145 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3146 pll_full_buffered2_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
+C3147 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3148 pll_full_buffered2_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
+C3149 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
+C3150 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3151 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3152 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3153 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3154 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3155 pll_full_buffered2_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3156 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
+C3157 pll_full_buffered2_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
+C3158 pll_full_buffered2_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
+C3159 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3160 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
+C3161 pll_full_buffered2_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3162 pll_full_buffered2_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
+C3163 pll_full_buffered2_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
+C3164 pll_full_buffered2_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
+C3165 pll_full_buffered2_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
+C3166 pll_full_buffered2_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
+C3167 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C3168 pll_full_buffered2_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C3169 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3170 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3171 pll_full_buffered2_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C3172 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C3173 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3174 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3175 pll_full_buffered2_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_0/out 25.17fF
+C3176 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3177 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3178 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3179 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3180 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C3181 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3182 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3183 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3184 pll_full_buffered2_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3185 pll_full_buffered2_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 390.59fF
+C3186 pll_full_buffered2_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 35.09fF
+C3187 gpio_noesd[7] ro_complete_buffered_0/tapered_buf_0/out 657.51fF
+C3188 pll_full_buffered2_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3189 pll_full_buffered2_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3190 pll_full_buffered2_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3191 pll_full_buffered2_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3192 pll_full_buffered2_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3193 pll_full_buffered2_0/tapered_buf_5/in ro_complete_buffered_0/tapered_buf_0/out 4.76fF
+C3194 pll_full_buffered2_0/tapered_buf_4/out ro_complete_buffered_0/tapered_buf_0/out 385.89fF
+C3195 pll_full_buffered2_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3196 pll_full_buffered2_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3197 pll_full_buffered2_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3198 pll_full_buffered2_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3199 pll_full_buffered2_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3200 pll_full_buffered2_0/tapered_buf_4/in ro_complete_buffered_0/tapered_buf_0/out 2.90fF
+C3201 pll_full_buffered2_0/tapered_buf_3/out ro_complete_buffered_0/tapered_buf_0/out 385.95fF
+C3202 pll_full_buffered2_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3203 pll_full_buffered2_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3204 pll_full_buffered2_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3205 pll_full_buffered2_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3206 pll_full_buffered2_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3207 gpio_noesd[8] ro_complete_buffered_0/tapered_buf_0/out 592.83fF
+C3208 pll_full_buffered2_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3209 pll_full_buffered2_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3210 pll_full_buffered2_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3211 pll_full_buffered2_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3212 pll_full_buffered2_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3213 ro_divider_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3214 ro_divider_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3215 ro_divider_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3216 ro_divider_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3217 ro_divider_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3218 gpio_noesd[5] ro_complete_buffered_0/tapered_buf_0/out 466.66fF
+C3219 ro_divider_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3220 ro_divider_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3221 ro_divider_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3222 ro_divider_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3223 ro_divider_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3224 ro_divider_buffered_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.74fF
+C3225 ro_divider_buffered_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.25fF
+C3226 ro_divider_buffered_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.19fF
+C3227 ro_divider_buffered_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.93fF
+C3228 ro_divider_buffered_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3229 ro_divider_buffered_0/divider_0/Out ro_complete_buffered_0/tapered_buf_0/out 15.49fF
+C3230 ro_divider_buffered_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3231 ro_divider_buffered_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3232 ro_divider_buffered_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3233 ro_divider_buffered_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.33fF
+C3234 ro_divider_buffered_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3235 ro_divider_buffered_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3236 ro_divider_buffered_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3237 ro_divider_buffered_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3238 ro_divider_buffered_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3239 ro_divider_buffered_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3240 ro_divider_buffered_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.05fF
+C3241 ro_divider_buffered_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3242 ro_divider_buffered_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3243 ro_divider_buffered_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3244 ro_divider_buffered_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3245 ro_divider_buffered_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3246 ro_divider_buffered_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3247 ro_divider_buffered_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.04fF
+C3248 ro_divider_buffered_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3249 ro_divider_buffered_0/divider_0/clk ro_complete_buffered_0/tapered_buf_0/out 23.46fF
+C3250 ro_divider_buffered_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3251 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3252 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.69fF
+C3253 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3254 ro_divider_buffered_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3255 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3256 ro_divider_buffered_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.62fF
+C3257 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3258 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3259 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3260 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3261 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3262 ro_divider_buffered_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3263 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3264 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3265 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3266 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3267 ro_divider_buffered_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3268 ro_divider_buffered_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3269 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3270 ro_divider_buffered_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3271 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3272 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3273 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3274 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3275 ro_divider_buffered_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3276 ro_divider_buffered_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3277 ro_divider_buffered_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3278 ro_divider_buffered_0/divider_0/mc2 ro_complete_buffered_0/tapered_buf_0/out 397.55fF
+C3279 ro_divider_buffered_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.53fF
+C3280 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3281 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3282 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3283 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3284 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3285 ro_divider_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3286 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3287 ro_divider_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 416.44fF
+C3288 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3289 ro_divider_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 412.08fF
+C3290 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3291 ro_divider_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 402.75fF
+C3292 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3293 ro_divider_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 407.11fF
+C3294 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3295 ro_divider_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 398.91fF
+C3296 ro_divider_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3297 ro_divider_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 395.69fF
+C3298 ro_divider_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.13fF
+C3299 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3300 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3301 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3302 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3303 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3304 ro_divider_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3305 ro_divider_buffered_0/tapered_buf_8/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3306 ro_divider_buffered_0/tapered_buf_8/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3307 ro_divider_buffered_0/tapered_buf_8/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3308 ro_divider_buffered_0/tapered_buf_8/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3309 ro_divider_buffered_0/tapered_buf_8/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3310 io_analog[8] ro_complete_buffered_0/tapered_buf_0/out 459.92fF
+C3311 ro_divider_buffered_0/tapered_buf_7/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3312 ro_divider_buffered_0/tapered_buf_7/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3313 ro_divider_buffered_0/tapered_buf_7/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3314 ro_divider_buffered_0/tapered_buf_7/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3315 ro_divider_buffered_0/tapered_buf_7/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3316 io_analog[7] ro_complete_buffered_0/tapered_buf_0/out 410.14fF
+C3317 ro_divider_buffered_0/tapered_buf_6/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3318 ro_divider_buffered_0/tapered_buf_6/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3319 ro_divider_buffered_0/tapered_buf_6/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3320 ro_divider_buffered_0/tapered_buf_6/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3321 ro_divider_buffered_0/tapered_buf_6/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3322 io_analog[6] ro_complete_buffered_0/tapered_buf_0/out 371.89fF
+C3323 ro_divider_buffered_0/tapered_buf_5/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3324 ro_divider_buffered_0/tapered_buf_5/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3325 ro_divider_buffered_0/tapered_buf_5/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3326 ro_divider_buffered_0/tapered_buf_5/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3327 ro_divider_buffered_0/tapered_buf_5/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3328 io_analog[5] ro_complete_buffered_0/tapered_buf_0/out 328.14fF
+C3329 ro_divider_buffered_0/tapered_buf_4/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3330 ro_divider_buffered_0/tapered_buf_4/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3331 ro_divider_buffered_0/tapered_buf_4/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3332 ro_divider_buffered_0/tapered_buf_4/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3333 ro_divider_buffered_0/tapered_buf_4/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3334 io_analog[4] ro_complete_buffered_0/tapered_buf_0/out 241.52fF
+C3335 ro_divider_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3336 ro_divider_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3337 ro_divider_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3338 ro_divider_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3339 ro_divider_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3340 io_analog[3] ro_complete_buffered_0/tapered_buf_0/out 151.14fF
+C3341 ro_divider_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C3342 ro_divider_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3343 ro_divider_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3344 ro_divider_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3345 ro_divider_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3346 gpio_analog[5] ro_complete_buffered_0/tapered_buf_0/out 109.76fF
+C3347 gpio_analog[17] ro_complete_buffered_0/tapered_buf_0/out 525.65fF
+C3348 filter_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3349 filter_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3350 filter_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3351 filter_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3352 filter_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3353 filter_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3354 filter_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3355 filter_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3356 filter_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3357 filter_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3358 filter_buffered_0/filter_0/v ro_complete_buffered_0/tapered_buf_0/out 476.79fF
+C3359 filter_buffered_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.47fF **FLOATING
+C3360 filter_buffered_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.03fF **FLOATING
+C3361 cp_buffered_0/cp_0/down ro_complete_buffered_0/tapered_buf_0/out 397.14fF
+C3362 cp_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3363 cp_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3364 cp_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3365 cp_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3366 cp_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3367 gpio_analog[8] ro_complete_buffered_0/tapered_buf_0/out 86.34fF
+C3368 gpio_noesd[9] ro_complete_buffered_0/tapered_buf_0/out 503.64fF
+C3369 cp_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3370 cp_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3371 cp_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3372 cp_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3373 cp_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3374 cp_buffered_0/cp_0/out ro_complete_buffered_0/tapered_buf_0/out 11.85fF
+C3375 cp_buffered_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 393.41fF
+C3376 cp_buffered_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3377 cp_buffered_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
+C3378 cp_buffered_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3379 cp_buffered_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
+C3380 cp_buffered_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 1.65fF **FLOATING
+C3381 cp_buffered_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 5.76fF **FLOATING
+C3382 cp_buffered_0/cp_0/a_1710_n2840# ro_complete_buffered_0/tapered_buf_0/out 5.24fF **FLOATING
+C3383 cp_buffered_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 3.19fF **FLOATING
+C3384 cp_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3385 cp_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3386 cp_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3387 cp_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3388 cp_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3389 gpio_analog[7] ro_complete_buffered_0/tapered_buf_0/out 67.87fF
+C3390 gpio_noesd[11] ro_complete_buffered_0/tapered_buf_0/out 514.13fF
+C3391 pd_buffered_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3392 pd_buffered_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3393 pd_buffered_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3394 pd_buffered_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3395 pd_buffered_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3396 pd_buffered_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3397 pd_buffered_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3398 pd_buffered_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3399 pd_buffered_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3400 pd_buffered_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3401 gpio_analog[9] ro_complete_buffered_0/tapered_buf_0/out 74.98fF
+C3402 pd_buffered_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 5.76fF
+C3403 pd_buffered_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C3404 pd_buffered_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C3405 pd_buffered_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3406 pd_buffered_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3407 pd_buffered_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C3408 pd_buffered_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C3409 pd_buffered_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3410 pd_buffered_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3411 pd_buffered_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 8.46fF
+C3412 pd_buffered_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3413 pd_buffered_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3414 pd_buffered_0/pd_0/DIV ro_complete_buffered_0/tapered_buf_0/out 390.67fF
+C3415 pd_buffered_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3416 pd_buffered_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3417 pd_buffered_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C3418 pd_buffered_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3419 pd_buffered_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3420 pd_buffered_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3421 pd_buffered_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3422 pd_buffered_0/pd_0/REF ro_complete_buffered_0/tapered_buf_0/out 388.56fF
+C3423 pd_buffered_0/tapered_buf_3/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3424 pd_buffered_0/tapered_buf_3/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3425 pd_buffered_0/tapered_buf_3/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3426 pd_buffered_0/tapered_buf_3/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3427 pd_buffered_0/tapered_buf_3/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3428 gpio_noesd[10] ro_complete_buffered_0/tapered_buf_0/out 487.93fF
+C3429 pd_buffered_0/tapered_buf_2/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3430 pd_buffered_0/tapered_buf_2/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3431 pd_buffered_0/tapered_buf_2/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3432 pd_buffered_0/tapered_buf_2/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3433 pd_buffered_0/tapered_buf_2/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3434 ashish_0/b ro_complete_buffered_0/tapered_buf_0/out 3.76fF
+C3435 ashish_0/a ro_complete_buffered_0/tapered_buf_0/out 1.43fF
+C3436 io_analog[0] ro_complete_buffered_0/tapered_buf_0/out 49.99fF
+C3437 io_analog[1] ro_complete_buffered_0/tapered_buf_0/out 34.21fF
+C3438 gpio_analog[3] ro_complete_buffered_0/tapered_buf_0/out 229.38fF
+C3439 pll_full_buffered1_0/tapered_buf_0/in5 ro_complete_buffered_0/tapered_buf_0/out 619.27fF
+C3440 pll_full_buffered1_0/tapered_buf_0/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3441 pll_full_buffered1_0/tapered_buf_0/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3442 pll_full_buffered1_0/tapered_buf_0/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3443 pll_full_buffered1_0/tapered_buf_0/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3444 pll_full_buffered1_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/out 1.38fF
+C3445 pll_full_buffered1_0/tapered_buf_1/in5 ro_complete_buffered_0/tapered_buf_0/out 592.97fF
+C3446 pll_full_buffered1_0/tapered_buf_1/in4 ro_complete_buffered_0/tapered_buf_0/out 252.41fF
+C3447 pll_full_buffered1_0/tapered_buf_1/in3 ro_complete_buffered_0/tapered_buf_0/out 63.61fF
+C3448 pll_full_buffered1_0/tapered_buf_1/in2 ro_complete_buffered_0/tapered_buf_0/out 16.76fF
+C3449 pll_full_buffered1_0/tapered_buf_1/in1 ro_complete_buffered_0/tapered_buf_0/out 4.58fF
+C3450 pll_full_buffered1_0/pll_full_0/divider_0/and_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.65fF
+C3451 pll_full_buffered1_0/pll_full_0/divider_0/and_0/B ro_complete_buffered_0/tapered_buf_0/out 2.45fF
+C3452 pll_full_buffered1_0/pll_full_0/divider_0/and_0/A ro_complete_buffered_0/tapered_buf_0/out 2.35fF
+C3453 pll_full_buffered1_0/pll_full_0/divider_0/and_0/out1 ro_complete_buffered_0/tapered_buf_0/out 2.99fF
+C3454 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3455 pll_full_buffered1_0/pll_full_0/div ro_complete_buffered_0/tapered_buf_0/out 15.26fF
+C3456 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3457 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3458 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3459 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/B ro_complete_buffered_0/tapered_buf_0/out 6.48fF
+C3460 pll_full_buffered1_0/pll_full_0/divider_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3461 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3462 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3463 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3464 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3465 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3466 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/B ro_complete_buffered_0/tapered_buf_0/out 7.12fF
+C3467 pll_full_buffered1_0/pll_full_0/divider_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3468 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3469 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Q ro_complete_buffered_0/tapered_buf_0/out 3.14fF
+C3470 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3471 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3472 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3473 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/A ro_complete_buffered_0/tapered_buf_0/out 7.08fF
+C3474 pll_full_buffered1_0/pll_full_0/divider_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.15fF **FLOATING
+C3475 pll_full_buffered1_0/pll_full_0/vco ro_complete_buffered_0/tapered_buf_0/out 45.00fF
+C3476 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_1/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3477 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/D ro_complete_buffered_0/tapered_buf_0/out 2.64fF
+C3478 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Q ro_complete_buffered_0/tapered_buf_0/out 3.72fF
+C3479 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Q ro_complete_buffered_0/tapered_buf_0/out 3.61fF
+C3480 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/nand_0/z1 ro_complete_buffered_0/tapered_buf_0/out 0.36fF
+C3481 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/D ro_complete_buffered_0/tapered_buf_0/out 3.12fF
+C3482 pll_full_buffered1_0/pll_full_0/divider_0/and_0/OUT ro_complete_buffered_0/tapered_buf_0/out 5.67fF
+C3483 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3484 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3485 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.19fF
+C3486 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3487 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.47fF **FLOATING
+C3488 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3489 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3490 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3491 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.48fF
+C3492 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3493 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.14fF **FLOATING
+C3494 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/m1_2700_2190# ro_complete_buffered_0/tapered_buf_0/out 4.22fF **FLOATING
+C3495 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 0.86fF
+C3496 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/Out ro_complete_buffered_0/tapered_buf_0/out 4.59fF
+C3497 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.26fF
+C3498 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.46fF
+C3499 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.99fF
+C3500 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# ro_complete_buffered_0/tapered_buf_0/out 1.16fF **FLOATING
+C3501 pll_full_buffered1_0/pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# ro_complete_buffered_0/tapered_buf_0/out 2.11fF **FLOATING
+C3502 pll_full_buffered1_0/pll_full_0/divider_0/nor_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3503 pll_full_buffered1_0/pll_full_0/divider_0/nor_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3504 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/v ro_complete_buffered_0/tapered_buf_0/out 16.43fF
+C3505 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3506 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3507 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3508 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3509 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3510 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3511 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3512 pll_full_buffered1_0/pll_full_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_0/out 5.35fF
+C3513 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3514 pll_full_buffered1_0/pll_full_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_0/out 6.54fF
+C3515 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3516 pll_full_buffered1_0/pll_full_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_0/out 5.96fF
+C3517 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3518 pll_full_buffered1_0/pll_full_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_0/out 5.21fF
+C3519 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3520 pll_full_buffered1_0/pll_full_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_0/out 5.81fF
+C3521 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3522 pll_full_buffered1_0/pll_full_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/out 6.74fF
+C3523 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_0/out 15.12fF
+C3524 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/tapered_buf_0/out 0.78fF
+C3525 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/tapered_buf_0/out 1.50fF
+C3526 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/tapered_buf_0/out 1.30fF
+C3527 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/tapered_buf_0/out 0.56fF
+C3528 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/tapered_buf_0/out 1.14fF
+C3529 pll_full_buffered1_0/pll_full_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/tapered_buf_0/out 1.02fF
+C3530 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n5230# ro_complete_buffered_0/tapered_buf_0/out 418.90fF **FLOATING
+C3531 pll_full_buffered1_0/pll_full_0/filter_0/a_4216_n2998# ro_complete_buffered_0/tapered_buf_0/out 1.39fF **FLOATING
+C3532 pll_full_buffered1_0/pll_full_0/cp_0/vbias ro_complete_buffered_0/tapered_buf_0/out 2.41fF
+C3533 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_n2840# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3534 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_n2840# ro_complete_buffered_0/tapered_buf_0/out 1.71fF **FLOATING
+C3535 pll_full_buffered1_0/pll_full_0/cp_0/a_7110_0# ro_complete_buffered_0/tapered_buf_0/out 0.17fF **FLOATING
+C3536 pll_full_buffered1_0/pll_full_0/cp_0/a_6370_0# ro_complete_buffered_0/tapered_buf_0/out 0.40fF **FLOATING
+C3537 pll_full_buffered1_0/pll_full_0/cp_0/a_3060_0# ro_complete_buffered_0/tapered_buf_0/out 2.50fF **FLOATING
+C3538 pll_full_buffered1_0/pll_full_0/cp_0/a_1710_0# ro_complete_buffered_0/tapered_buf_0/out 7.47fF **FLOATING
+C3539 pll_full_buffered1_0/pll_full_0/cp_0/a_10_n50# ro_complete_buffered_0/tapered_buf_0/out 2.96fF **FLOATING
+C3540 pll_full_buffered1_0/pll_full_0/pd_0/UP ro_complete_buffered_0/tapered_buf_0/out 4.55fF
+C3541 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.39fF
+C3542 pll_full_buffered1_0/pll_full_0/pd_0/and_pd_0/Out1 ro_complete_buffered_0/tapered_buf_0/out 2.22fF
+C3543 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3544 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3545 pll_full_buffered1_0/pll_full_0/pd_0/R ro_complete_buffered_0/tapered_buf_0/out 3.05fF
+C3546 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.79fF
+C3547 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3548 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3549 pll_full_buffered1_0/pll_full_0/pd_0/DOWN ro_complete_buffered_0/tapered_buf_0/out 7.30fF
+C3550 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3551 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_1/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3552 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/z5 ro_complete_buffered_0/tapered_buf_0/out 1.10fF
+C3553 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z4 ro_complete_buffered_0/tapered_buf_0/out 1.07fF
+C3554 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar ro_complete_buffered_0/tapered_buf_0/out 0.88fF
+C3555 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z2 ro_complete_buffered_0/tapered_buf_0/out 1.22fF
+C3556 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z1 ro_complete_buffered_0/tapered_buf_0/out 0.67fF
+C3557 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Qbar1 ro_complete_buffered_0/tapered_buf_0/out 1.34fF
+C3558 pll_full_buffered1_0/pll_full_0/pd_0/tspc_r_0/Z3 ro_complete_buffered_0/tapered_buf_0/out 2.12fF
+C3559 pll_full_buffered1_0/pll_full_0/ref ro_complete_buffered_0/tapered_buf_0/out 391.17fF
+C3560 pll_full_buffered1_0/pll_full_0/cp_0/upbar ro_complete_buffered_0/tapered_buf_0/out 14.90fF
+C3561 gpio_noesd[14] ro_complete_buffered_0/tapered_buf_0/out 950.03fF
+C3562 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in5 ro_complete_buffered_0/tapered_buf_0/out 599.07fF
+C3563 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in4 ro_complete_buffered_0/tapered_buf_0/out 256.17fF
+C3564 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in3 ro_complete_buffered_0/tapered_buf_0/out 83.14fF
+C3565 pll_full_buffered1_0/DIGITAL_BUFFER_v1_0/in1 ro_complete_buffered_0/tapered_buf_0/out 5.32fF
.ends
