2022-03-22 04:24:15 - [INFO] - {{Project Git Info}} Repository: https://github.com/adithyasunil26/2.87GHz-MWG-MPW5.git | Branch: main | Commit: 654b87de919fb64952b256db9135b5264c8b5973
2022-03-22 04:24:15 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: microwave_signal_generator
2022-03-22 04:24:15 - [INFO] - {{Project Type Info}} analog
2022-03-22 04:24:15 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 578e65faf0257008833662b6c186ebef78e9c6ba
2022-03-22 04:24:15 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
2022-03-22 04:24:15 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2022-03-22 04:24:15 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'microwave_signal_generator/jobs/mpw_precheck/fe87c066-c32f-48c7-a8a0-162983d41cc7/logs'
2022-03-22 04:24:15 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-03-22 04:24:15 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-03-22 04:24:16 - [INFO] - An approved LICENSE (Apache-2.0) was found in microwave_signal_generator.
2022-03-22 04:24:16 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-03-22 04:24:17 - [INFO] - An approved LICENSE (Apache-2.0) was found in microwave_signal_generator.
2022-03-22 04:24:17 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-03-22 04:24:17 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in microwave_signal_generator/openlane/Makefile
2022-03-22 04:24:17 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 29 non-compliant file(s) with the SPDX Standard.
2022-03-22 04:24:17 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['microwave_signal_generator/Makefile', 'microwave_signal_generator/docs/Makefile', 'microwave_signal_generator/docs/environment.yml', 'microwave_signal_generator/docs/source/conf.py', 'microwave_signal_generator/docs/source/index.rst', 'microwave_signal_generator/netgen/run_lvs_por.sh', 'microwave_signal_generator/netgen/run_lvs_wrapper_verilog.sh', 'microwave_signal_generator/netgen/run_lvs_wrapper_xschem.sh', 'microwave_signal_generator/netlists/plots/cp.eps', 'microwave_signal_generator/netlists/plots/div.eps', 'microwave_signal_generator/netlists/plots/pfd.eps', 'microwave_signal_generator/verilog/dv/Makefile', 'microwave_signal_generator/verilog/dv/mprj_por/Makefile', 'microwave_signal_generator/verilog/dv/mprj_por/mprj_por.c', 'microwave_signal_generator/verilog/dv/mprj_por/mprj_por_tb.v']
2022-03-22 04:24:17 - [INFO] - For the full SPDX compliance report check: microwave_signal_generator/jobs/mpw_precheck/fe87c066-c32f-48c7-a8a0-162983d41cc7/logs/spdx_compliance_report.log
2022-03-22 04:24:17 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-03-22 04:24:17 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-03-22 04:24:17 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-03-22 04:24:17 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-03-22 04:24:18 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-03-22 04:24:18 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-03-22 04:24:18 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-03-22 04:24:18 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-03-22 04:24:19 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2022-03-22 04:24:19 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
2022-03-22 04:24:19 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2022-03-22 04:24:19 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2022-03-22 04:24:19 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2022-03-22 04:24:19 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2022-03-22 04:24:19 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (3576 instances). 
2022-03-22 04:24:19 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2022-03-22 04:24:19 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2022-03-22 04:24:19 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2022-03-22 04:24:19 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-03-22 04:24:19 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-03-22 04:24:45 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view microwave_signal_generator/jobs/mpw_precheck/fe87c066-c32f-48c7-a8a0-162983d41cc7/outputs/user_analog_project_wrapper.xor.gds
2022-03-22 04:24:45 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-03-22 04:24:45 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-03-22 04:25:28 - [INFO] - 0 DRC violations
2022-03-22 04:25:28 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:25:28 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-03-22 04:26:29 - [INFO] - No DRC Violations found
2022-03-22 04:26:29 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:26:29 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-03-22 04:27:17 - [INFO] - No DRC Violations found
2022-03-22 04:27:17 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:27:17 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-03-22 04:27:30 - [INFO] - No DRC Violations found
2022-03-22 04:27:30 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:27:30 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-03-22 04:27:32 - [INFO] - No DRC Violations found
2022-03-22 04:27:32 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:27:32 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-03-22 04:27:35 - [INFO] - No DRC Violations found
2022-03-22 04:27:35 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:27:35 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-03-22 04:27:38 - [INFO] - No DRC Violations found
2022-03-22 04:27:38 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-22 04:27:38 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'microwave_signal_generator/jobs/mpw_precheck/fe87c066-c32f-48c7-a8a0-162983d41cc7/logs'
2022-03-22 04:27:38 - [INFO] - {{SUCCESS}} All Checks Passed !!!