diff --git a/gds/user_analog_project_wrapper.gds b/gds/user_analog_project_wrapper.gds
index 3bea112..21ecc19 100644
--- a/gds/user_analog_project_wrapper.gds
+++ b/gds/user_analog_project_wrapper.gds
Binary files differ
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index a75319a..9fc6b79 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,6 +1,6 @@
 magic
 tech sky130A
-timestamp 1642809162
+timestamp 1642810278
 << metal2 >>
 rect 262 -400 318 240
 rect 853 -400 909 240
@@ -700,6 +700,10 @@
 rect -50 0 0 352000
 rect 292000 0 292050 352000
 rect -50 -50 292050 0
+use divider  divider_0
+timestamp 1640957771
+transform 1 0 166638 0 1 265093
+box -490 -235 4690 2150
 use divbuf  divbuf_6
 timestamp 1641017053
 transform 1 0 245858 0 1 309157
@@ -736,6 +740,18 @@
 timestamp 1641017053
 transform 1 0 244347 0 1 337471
 box -460 -1085 31200 495
+use cp  cp_0
+timestamp 1640911461
+transform 1 0 54462 0 1 195288
+box -415 -1715 4690 2035
+use pd  pd_0
+timestamp 1640958486
+transform 1 0 103126 0 1 258815
+box -215 -855 1685 810
+use filter  filter_0
+timestamp 1640983258
+transform 1 0 77692 0 1 317254
+box -1800 -11005 6240 390
 << labels >>
 flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
 port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 031e08f..d122e00 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,210 +106,495 @@
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
 + wbs_stb_i wbs_we_i
-C0 io_clamp_low[2] io_analog[6] 0.53fF
-C1 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
-C2 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
-C3 divbuf_7/OUT4 divbuf_7/OUT 1.11fF
-C4 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C5 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
-C6 divbuf_1/OUT3 divbuf_1/OUT5 0.01fF
-C7 divbuf_1/OUT2 divbuf_1/OUT 0.06fF
-C8 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
-C9 divbuf_0/OUT divbuf_0/OUT2 0.06fF
-C10 divbuf_3/OUT5 divbuf_3/OUT 43.38fF
-C11 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
-C12 divbuf_5/OUT5 divbuf_5/OUT 43.38fF
-C13 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF
-C14 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF
-C15 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
-C16 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF
-C17 divbuf_6/IN divbuf_6/OUT5 0.00fF
-C18 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF
-C19 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C20 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
-C21 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
-C22 divbuf_1/OUT4 divbuf_1/OUT 1.11fF
-C23 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C24 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
-C25 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
-C26 divbuf_0/OUT divbuf_0/OUT3 0.26fF
-C27 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C28 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C29 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C30 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF
-C31 divbuf_3/OUT5 divbuf_3/a_492_n240# 0.01fF
-C32 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
-C33 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF
-C34 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF
-C35 divbuf_6/OUT2 divbuf_6/OUT 0.06fF
-C36 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C37 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
-C38 io_clamp_high[1] io_analog[5] 0.53fF
-C39 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C40 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
-C41 divbuf_2/OUT3 divbuf_2/OUT 0.26fF
-C42 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C43 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
-C44 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
-C45 divbuf_4/OUT3 divbuf_4/OUT 0.26fF
-C46 divbuf_0/OUT divbuf_0/OUT4 1.11fF
-C47 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
-C48 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C49 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF
-C50 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C51 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF
-C52 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF
-C53 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C54 divbuf_6/OUT4 divbuf_6/OUT 1.11fF
-C55 divbuf_0/OUT5 divbuf_0/OUT3 0.01fF
-C56 io_clamp_low[0] io_analog[4] 0.53fF
-C57 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C58 divbuf_2/OUT5 divbuf_2/OUT 43.38fF
-C59 divbuf_4/OUT5 divbuf_4/OUT 43.38fF
-C60 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF
-C61 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C62 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF
-C63 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF
-C64 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF
-C65 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C66 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF
-C67 divbuf_3/OUT5 divbuf_3/IN 0.00fF
-C68 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
-C69 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
-C70 divbuf_5/IN divbuf_5/OUT5 0.00fF
-C71 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C72 divbuf_0/OUT5 divbuf_0/OUT4 20.26fF
-C73 divbuf_1/a_492_n240# divbuf_1/OUT5 0.01fF
-C74 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
-C75 divbuf_0/OUT divbuf_0/OUT5 43.38fF
-C76 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C77 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
-C78 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C79 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF
-C80 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF
-C81 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF
-C82 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF
-C83 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF
-C84 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF
-C85 divbuf_1/IN divbuf_1/OUT5 0.00fF
-C86 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF
-C87 divbuf_3/OUT2 divbuf_3/OUT 0.06fF
-C88 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C89 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF
-C90 divbuf_5/OUT2 divbuf_5/OUT 0.06fF
-C91 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF
-C92 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF
-C93 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C94 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF
-C95 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF
-C96 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF
-C97 divbuf_7/OUT3 divbuf_7/OUT 0.26fF
-C98 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
-C99 divbuf_1/OUT2 divbuf_1/OUT5 0.02fF
-C100 divbuf_3/OUT4 divbuf_3/OUT 1.11fF
-C101 divbuf_5/OUT4 divbuf_5/OUT 1.11fF
-C102 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C103 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C104 divbuf_0/OUT5 divbuf_0/IN 0.00fF
-C105 divbuf_3/OUT2 divbuf_3/a_492_n240# 0.42fF
-C106 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF
-C107 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF
-C108 io_clamp_high[2] io_analog[6] 0.53fF
-C109 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
-C110 divbuf_2/IN divbuf_2/OUT5 0.00fF
-C111 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
-C112 divbuf_7/OUT5 divbuf_7/OUT 43.38fF
-C113 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C114 divbuf_1/OUT4 divbuf_1/OUT5 20.26fF
-C115 divbuf_1/OUT3 divbuf_1/OUT 0.26fF
-C116 divbuf_4/IN divbuf_4/OUT5 0.00fF
-C117 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
-C118 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
-C119 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF
-C120 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C121 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C122 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C123 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF
-C124 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF
-C125 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF
-C126 io_clamp_low[1] io_analog[5] 0.53fF
-C127 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF
-C128 divbuf_2/OUT2 divbuf_2/OUT 0.06fF
-C129 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C130 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF
-C131 divbuf_4/OUT2 divbuf_4/OUT 0.06fF
-C132 divbuf_1/OUT5 divbuf_1/OUT 43.38fF
-C133 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C134 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
-C135 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C136 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
-C137 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
-C138 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
-C139 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF
-C140 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF
-C141 divbuf_6/OUT3 divbuf_6/OUT 0.26fF
-C142 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF
-C143 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
-C144 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
-C145 divbuf_2/OUT4 divbuf_2/OUT 1.11fF
-C146 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C147 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C148 divbuf_4/OUT4 divbuf_4/OUT 1.11fF
-C149 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C150 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
-C151 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF
-C152 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C153 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF
-C154 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
-C155 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
-C156 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C157 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF
-C158 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
-C159 divbuf_6/OUT5 divbuf_6/OUT 43.38fF
-C160 io_clamp_high[0] io_analog[4] 0.53fF
-C161 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
-C162 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
-C163 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
-C164 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF
-C165 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C166 divbuf_7/IN divbuf_7/OUT5 0.00fF
-C167 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C168 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C169 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF
-C170 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C171 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF
-C172 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF
-C173 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
-C174 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C175 divbuf_1/a_492_n240# divbuf_1/OUT 0.00fF
-C176 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C177 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
-C178 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C179 divbuf_0/OUT2 divbuf_0/OUT3 1.37fF
-C180 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C181 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF
-C182 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C183 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF
-C184 divbuf_7/OUT2 divbuf_7/OUT 0.06fF
-C185 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF
-C186 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C187 divbuf_3/OUT3 divbuf_3/OUT 0.26fF
-C188 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF
-C189 divbuf_5/OUT3 divbuf_5/OUT 0.26fF
-C190 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C191 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C192 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
-C193 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF
+C0 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C2 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
+C3 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C4 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
+C5 divbuf_5/a_492_n240# divbuf_5/OUT 0.00fF
+C6 divbuf_0/OUT divbuf_0/OUT5 43.38fF
+C7 divider_0/nor_1/B divider_0/and_0/B 0.31fF
+C8 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
+C9 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
+C10 divbuf_6/OUT4 divbuf_6/OUT 1.11fF
+C11 divbuf_1/a_492_n240# divbuf_1/OUT2 0.42fF
+C12 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C13 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF
+C14 divbuf_4/a_492_n240# divbuf_4/IN 0.13fF
+C15 divider_0/and_0/OUT divider_0/clk 0.04fF
+C16 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
+C17 pd_0/tspc_r_0/Z3 pd_0/R 0.27fF
+C18 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C19 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
+C20 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
+C21 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
+C22 io_clamp_high[0] io_analog[4] 0.53fF
+C23 divbuf_4/OUT5 divbuf_4/OUT 43.38fF
+C24 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
+C25 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
+C26 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
+C27 pd_0/REF pd_0/tspc_r_1/Z1 0.17fF
+C28 divbuf_6/a_492_n240# divbuf_6/IN 0.13fF
+C29 divbuf_4/OUT4 divbuf_4/OUT 1.11fF
+C30 divbuf_0/OUT divbuf_0/a_492_n240# 0.00fF
+C31 divbuf_0/OUT3 divbuf_0/OUT2 1.37fF
+C32 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C33 divbuf_3/OUT3 divbuf_3/OUT 0.26fF
+C34 divbuf_3/OUT4 divbuf_3/OUT5 20.26fF
+C35 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z3 0.05fF
+C36 divbuf_7/OUT2 divbuf_7/OUT3 1.37fF
+C37 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C38 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C39 divider_0/nor_1/B divider_0/tspc_0/a_630_n680# 0.01fF
+C40 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C41 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
+C42 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
+C43 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
+C44 divider_0/and_0/A divider_0/and_0/B 0.18fF
+C45 divbuf_5/IN divbuf_5/OUT5 0.00fF
+C46 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C47 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_0/z1 0.24fF
+C48 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/Out 0.19fF
+C49 divbuf_0/OUT5 divbuf_0/a_492_n240# 0.01fF
+C50 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
+C51 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.26fF
+C52 pd_0/DOWN pd_0/R 0.36fF
+C53 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
+C54 pd_0/DIV pd_0/tspc_r_0/z5 0.04fF
+C55 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
+C56 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C57 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
+C58 pd_0/tspc_r_1/Qbar1 pd_0/UP 0.11fF
+C59 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
+C60 cp_0/a_10_n50# cp_0/vbias 0.19fF
+C61 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
+C62 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
+C63 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.45fF
+C64 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C65 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C66 divbuf_3/OUT5 divbuf_3/OUT 43.38fF
+C67 divbuf_7/OUT2 divbuf_7/OUT5 0.02fF
+C68 divbuf_7/OUT3 divbuf_7/OUT4 5.16fF
+C69 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
+C70 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C71 pd_0/R pd_0/tspc_r_1/Z3 0.29fF
+C72 divbuf_1/OUT5 divbuf_1/OUT 43.38fF
+C73 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C74 divbuf_5/OUT2 divbuf_5/OUT 0.06fF
+C75 divbuf_5/OUT3 divbuf_5/OUT5 0.01fF
+C76 divbuf_4/a_492_n240# divbuf_4/OUT 0.00fF
+C77 divbuf_0/OUT divbuf_0/OUT2 0.06fF
+C78 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
+C79 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C80 divbuf_3/a_492_n240# divbuf_3/OUT2 0.42fF
+C81 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/Q 0.04fF
+C82 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
+C83 pd_0/UP pd_0/and_pd_0/Out1 0.33fF
+C84 divbuf_2/OUT2 divbuf_2/OUT3 1.37fF
+C85 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C86 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
+C87 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
+C88 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
+C89 divbuf_2/OUT5 divbuf_2/IN 0.00fF
+C90 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
+C91 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
+C92 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
+C93 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF
+C94 divbuf_1/a_492_n240# divbuf_1/IN 0.13fF
+C95 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
+C96 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
+C97 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
+C98 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
+C99 divbuf_6/a_492_n240# divbuf_6/OUT5 0.01fF
+C100 divbuf_0/OUT5 divbuf_0/OUT2 0.02fF
+C101 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
+C102 divider_0/mc2 divider_0/nor_1/A 0.04fF
+C103 divider_0/nor_1/A divider_0/prescaler_0/Out 0.15fF
+C104 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.64fF
+C105 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF
+C106 pd_0/DIV pd_0/tspc_r_0/Qbar1 0.12fF
+C107 divbuf_7/OUT3 divbuf_7/OUT 0.26fF
+C108 divbuf_7/OUT4 divbuf_7/OUT5 20.26fF
+C109 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C110 divider_0/tspc_0/Z1 divider_0/nor_1/A 0.03fF
+C111 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C112 pd_0/R pd_0/UP 0.45fF
+C113 io_clamp_low[2] io_analog[6] 0.53fF
+C114 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C115 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
+C116 divider_0/tspc_0/Z4 divider_0/prescaler_0/Out 0.12fF
+C117 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C118 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C119 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
+C120 divbuf_5/OUT4 divbuf_5/OUT 1.11fF
+C121 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C122 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF
+C123 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z3 0.33fF
+C124 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
+C125 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Out1 0.05fF
+C126 divbuf_2/OUT2 divbuf_2/OUT5 0.02fF
+C127 divbuf_2/OUT3 divbuf_2/OUT4 5.16fF
+C128 divbuf_0/OUT2 divbuf_0/a_492_n240# 0.42fF
+C129 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
+C130 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
+C131 divbuf_2/OUT2 divbuf_2/OUT 0.06fF
+C132 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C133 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_0/D 0.16fF
+C134 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Q 0.05fF
+C135 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
+C136 divbuf_5/a_492_n240# divbuf_5/IN 0.13fF
+C137 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C138 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
+C139 pd_0/REF pd_0/tspc_r_1/z5 0.04fF
+C140 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
+C141 divbuf_6/OUT2 divbuf_6/OUT3 1.37fF
+C142 divbuf_1/OUT5 divbuf_1/OUT2 0.02fF
+C143 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
+C144 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
+C145 pd_0/tspc_r_0/Z3 pd_0/DOWN 0.03fF
+C146 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
+C147 divbuf_7/OUT5 divbuf_7/OUT 43.38fF
+C148 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
+C149 divbuf_1/OUT5 divbuf_1/a_492_n240# 0.01fF
+C150 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
+C151 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
+C152 divider_0/tspc_0/Q divider_0/tspc_0/Z3 0.05fF
+C153 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF
+C154 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C155 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.01fF
+C156 pd_0/R pd_0/tspc_r_1/Qbar 0.03fF
+C157 divbuf_2/a_492_n240# divbuf_2/OUT5 0.01fF
+C158 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C159 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
+C160 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
+C161 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF
+C162 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF
+C163 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C164 divbuf_3/a_492_n240# divbuf_3/OUT 0.00fF
+C165 divbuf_7/a_492_n240# divbuf_7/OUT2 0.42fF
+C166 divbuf_2/OUT4 divbuf_2/OUT5 20.26fF
+C167 divbuf_2/a_492_n240# divbuf_2/OUT 0.00fF
+C168 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF
+C169 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C170 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
+C171 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
+C172 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
+C173 divider_0/prescaler_0/tspc_0/Q divider_0/clk 0.05fF
+C174 divbuf_2/OUT4 divbuf_2/OUT 1.11fF
+C175 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
+C176 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
+C177 divider_0/mc2 divider_0/and_0/B 0.20fF
+C178 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
+C179 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C180 cp_0/upbar cp_0/down 0.02fF
+C181 pd_0/R pd_0/and_pd_0/Z1 0.02fF
+C182 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
+C183 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C184 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.03fF
+C185 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
+C186 divbuf_6/OUT2 divbuf_6/OUT5 0.02fF
+C187 divbuf_6/OUT3 divbuf_6/OUT4 5.16fF
+C188 divbuf_1/OUT divbuf_1/OUT3 0.26fF
+C189 divbuf_1/OUT5 divbuf_1/OUT4 20.26fF
+C190 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C191 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF
+C192 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
+C193 pd_0/DIV pd_0/tspc_r_0/Z2 0.19fF
+C194 filter_0/a_4216_n2998# filter_0/v 0.31fF
+C195 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.05fF
+C196 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C197 io_clamp_high[1] io_analog[5] 0.53fF
+C198 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
+C199 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
+C200 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
+C201 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C202 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C203 divbuf_4/OUT2 divbuf_4/OUT5 0.02fF
+C204 divbuf_3/IN divbuf_3/OUT5 0.00fF
+C205 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
+C206 divider_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.01fF
+C207 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/Q 0.19fF
+C208 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.14fF
+C209 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C210 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
+C211 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
+C212 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C213 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C214 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
+C215 divider_0/nor_0/B divider_0/Out 0.22fF
+C216 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.29fF
+C217 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
+C218 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
+C219 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
+C220 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C221 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
+C222 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
+C223 divbuf_5/a_492_n240# divbuf_5/OUT5 0.01fF
+C224 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C225 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
+C226 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
+C227 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
+C228 divider_0/nor_1/B divider_0/and_0/A 0.26fF
+C229 divbuf_6/OUT3 divbuf_6/OUT 0.26fF
+C230 divbuf_6/OUT4 divbuf_6/OUT5 20.26fF
+C231 divider_0/mc2 divider_0/and_0/OUT 0.05fF
+C232 divider_0/nor_1/A divider_0/and_0/B 0.08fF
+C233 pd_0/DIV pd_0/R 0.51fF
+C234 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C235 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
+C236 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C237 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
+C238 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/Q 0.20fF
+C239 pd_0/REF pd_0/tspc_r_1/Qbar1 0.12fF
+C240 io_clamp_low[0] io_analog[4] 0.53fF
+C241 divbuf_1/OUT5 divbuf_1/IN 0.00fF
+C242 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C243 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
+C244 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.06fF
+C245 divbuf_4/OUT3 divbuf_4/OUT 0.26fF
+C246 divbuf_4/OUT4 divbuf_4/OUT5 20.26fF
+C247 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C248 divbuf_3/OUT2 divbuf_3/OUT 0.06fF
+C249 divbuf_3/OUT3 divbuf_3/OUT5 0.01fF
+C250 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
+C251 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/D 0.32fF
+C252 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
+C253 divbuf_7/a_492_n240# divbuf_7/OUT 0.00fF
+C254 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C255 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C256 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C257 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
+C258 pd_0/DOWN pd_0/UP 0.46fF
+C259 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
+C260 divbuf_1/OUT2 divbuf_1/OUT3 1.37fF
+C261 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C262 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
+C263 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
+C264 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C265 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C266 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
+C267 divbuf_5/OUT2 divbuf_5/OUT3 1.37fF
+C268 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF
+C269 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C270 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
+C271 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
+C272 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/Out 0.08fF
+C273 divbuf_6/OUT5 divbuf_6/OUT 43.38fF
+C274 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
+C275 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C276 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C277 divider_0/tspc_0/Z4 divider_0/tspc_0/a_630_n680# 0.12fF
+C278 divbuf_4/a_492_n240# divbuf_4/OUT2 0.42fF
+C279 pd_0/tspc_r_0/Qbar1 pd_0/R 0.01fF
+C280 pd_0/DIV pd_0/tspc_r_0/Z4 0.02fF
+C281 pd_0/DOWN pd_0/tspc_r_0/Qbar 0.21fF
+C282 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
+C283 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
+C284 divider_0/mc2 divider_0/and_0/out1 0.06fF
+C285 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Q 0.04fF
+C286 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C287 pd_0/tspc_r_1/Z3 pd_0/UP 0.03fF
+C288 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
+C289 pd_0/REF pd_0/tspc_r_1/Z2 0.19fF
+C290 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
+C291 divbuf_6/a_492_n240# divbuf_6/OUT2 0.42fF
+C292 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
+C293 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C294 divbuf_3/OUT4 divbuf_3/OUT 1.11fF
+C295 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
+C296 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/tspc_2/D 0.04fF
+C297 divbuf_7/IN divbuf_7/OUT5 0.00fF
+C298 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C299 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C300 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C301 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
+C302 pd_0/R pd_0/REF 0.61fF
+C303 divbuf_1/OUT3 divbuf_1/OUT4 5.16fF
+C304 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C305 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
+C306 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C307 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C308 cp_0/a_1710_0# cp_0/out 0.84fF
+C309 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.02fF
+C310 divbuf_5/OUT2 divbuf_5/OUT5 0.02fF
+C311 divbuf_5/OUT3 divbuf_5/OUT4 5.16fF
+C312 divbuf_4/a_492_n240# divbuf_4/OUT5 0.01fF
+C313 divbuf_3/a_492_n240# divbuf_3/IN 0.13fF
+C314 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C315 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
+C316 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
+C317 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/Out 0.11fF
+C318 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
+C319 divbuf_2/a_492_n240# divbuf_2/IN 0.13fF
+C320 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
+C321 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
+C322 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C323 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
+C324 filter_0/a_4216_n5230# filter_0/v 0.19fF
+C325 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C326 divider_0/prescaler_0/Out divider_0/clk 0.51fF
+C327 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C328 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
+C329 divider_0/prescaler_0/tspc_0/Q divider_0/prescaler_0/nand_1/z1 0.01fF
+C330 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/Out 0.05fF
+C331 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
+C332 pd_0/DIV pd_0/tspc_r_0/Z3 0.65fF
+C333 divbuf_7/OUT2 divbuf_7/OUT 0.06fF
+C334 divbuf_7/OUT3 divbuf_7/OUT5 0.01fF
+C335 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
+C336 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
+C337 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C338 divider_0/mc2 divider_0/nor_0/B 0.15fF
+C339 pd_0/R pd_0/tspc_r_1/Qbar1 0.30fF
+C340 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.45fF
+C341 cp_0/a_1710_0# cp_0/down 0.32fF
+C342 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C343 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C344 divbuf_5/OUT3 divbuf_5/OUT 0.26fF
+C345 divbuf_5/OUT4 divbuf_5/OUT5 20.26fF
+C346 divbuf_2/a_492_n240# divbuf_2/OUT2 0.42fF
+C347 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
+C348 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C349 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/Out 0.28fF
+C350 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C351 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C352 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
+C353 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/Out 0.91fF
+C354 pd_0/DOWN pd_0/tspc_r_0/z5 0.03fF
+C355 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
+C356 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C357 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C358 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF
+C359 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C360 divbuf_0/IN divbuf_0/OUT5 0.00fF
+C361 divider_0/mc2 divider_0/nor_1/B 0.06fF
+C362 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
+C363 divider_0/tspc_0/Z1 divider_0/tspc_0/Z3 0.06fF
+C364 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C365 pd_0/R pd_0/and_pd_0/Out1 0.33fF
+C366 pd_0/REF pd_0/tspc_r_1/Z4 0.02fF
+C367 pd_0/UP pd_0/tspc_r_1/Qbar 0.21fF
+C368 divbuf_6/a_492_n240# divbuf_6/OUT 0.00fF
+C369 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C370 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_1/z1 0.21fF
+C371 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
+C372 divbuf_7/OUT4 divbuf_7/OUT 1.11fF
+C373 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C374 io_clamp_high[2] io_analog[6] 0.53fF
+C375 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
+C376 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C377 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C378 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
+C379 pd_0/R pd_0/tspc_r_1/Z2 0.21fF
+C380 divbuf_5/OUT5 divbuf_5/OUT 43.38fF
+C381 divbuf_0/OUT3 divbuf_0/OUT4 5.16fF
+C382 divbuf_0/IN divbuf_0/a_492_n240# 0.13fF
+C383 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C384 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF
+C385 divbuf_3/a_492_n240# divbuf_3/OUT5 0.01fF
+C386 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C387 pd_0/UP pd_0/and_pd_0/Z1 0.06fF
+C388 divbuf_7/a_492_n240# divbuf_7/IN 0.13fF
+C389 divbuf_2/OUT3 divbuf_2/OUT5 0.01fF
+C390 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF
+C391 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
+C392 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
+C393 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
+C394 divbuf_2/OUT3 divbuf_2/OUT 0.26fF
+C395 divider_0/mc2 divider_0/and_0/A 0.16fF
+C396 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
+C397 divider_0/tspc_0/Z2 divider_0/tspc_0/Z3 0.16fF
+C398 divbuf_5/a_492_n240# divbuf_5/OUT2 0.42fF
+C399 divbuf_0/OUT divbuf_0/OUT3 0.26fF
+C400 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C401 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
+C402 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
+C403 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
+C404 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/Out 0.11fF
+C405 divbuf_6/IN divbuf_6/OUT5 0.00fF
+C406 divbuf_1/OUT divbuf_1/OUT2 0.06fF
+C407 divbuf_1/OUT5 divbuf_1/OUT3 0.01fF
+C408 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C409 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF
+C410 divider_0/nor_1/A divider_0/tspc_0/Z3 0.38fF
+C411 pd_0/DIV pd_0/tspc_r_0/Z1 0.17fF
+C412 pd_0/tspc_r_0/Qbar1 pd_0/DOWN 0.11fF
+C413 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_2/a_740_n680# 0.01fF
+C414 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
+C415 io_clamp_low[1] io_analog[5] 0.53fF
+C416 divbuf_1/OUT divbuf_1/a_492_n240# 0.00fF
+C417 divider_0/mc2 divider_0/prescaler_0/tspc_0/a_630_n680# 0.33fF
+C418 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C419 divider_0/tspc_0/Z4 divider_0/tspc_0/Z3 0.65fF
+C420 cp_0/a_1710_n2840# cp_0/out 0.61fF
+C421 divbuf_4/IN divbuf_4/OUT5 0.00fF
+C422 divbuf_0/OUT3 divbuf_0/OUT5 0.01fF
+C423 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF
+C424 divbuf_3/OUT2 divbuf_3/OUT3 1.37fF
+C425 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.44fF
+C426 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/Out 0.21fF
+C427 pd_0/tspc_r_1/Qbar pd_0/and_pd_0/Z1 0.02fF
+C428 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C429 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C430 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
+C431 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF
+C432 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C433 divbuf_4/OUT2 divbuf_4/OUT3 1.37fF
+C434 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
+C435 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
+C436 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
+C437 cp_0/a_1710_n2840# cp_0/upbar 0.29fF
+C438 divbuf_2/OUT5 divbuf_2/OUT 43.38fF
+C439 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C440 divbuf_0/OUT divbuf_0/OUT4 1.11fF
+C441 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
+C442 divider_0/and_0/OUT divider_0/prescaler_0/tspc_0/D 0.03fF
+C443 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
+C444 pd_0/UP pd_0/tspc_r_1/z5 0.03fF
+C445 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
+C446 divbuf_6/OUT2 divbuf_6/OUT 0.06fF
+C447 divbuf_6/OUT3 divbuf_6/OUT5 0.01fF
+C448 divbuf_1/OUT divbuf_1/OUT4 1.11fF
+C449 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
+C450 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C451 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
+C452 divider_0/nor_1/A divider_0/and_0/A 0.01fF
+C453 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
+C454 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
+C455 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
+C456 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
+C457 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
+C458 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.15fF
+C459 divider_0/nor_0/B divider_0/and_0/B 0.29fF
+C460 pd_0/REF pd_0/tspc_r_1/Z3 0.65fF
+C461 divbuf_0/OUT4 divbuf_0/OUT5 20.26fF
+C462 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C463 divbuf_4/OUT2 divbuf_4/OUT 0.06fF
+C464 divbuf_4/OUT3 divbuf_4/OUT5 0.01fF
+C465 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C466 divbuf_3/OUT2 divbuf_3/OUT5 0.02fF
+C467 divbuf_3/OUT3 divbuf_3/OUT4 5.16fF
+C468 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/Out 0.04fF
+C469 divbuf_7/a_492_n240# divbuf_7/OUT5 0.01fF
+C470 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C471 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
+C472 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
+C473 divbuf_4/OUT3 divbuf_4/OUT4 5.16fF
+C474 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
+C475 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
+Xpd_0 VDD gnd pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R pd
+Xcp_0 cp_0/vbias vdd gnd cp_0/out cp_0/down cp_0/upbar cp
+Xfilter_0 gnd filter_0/v filter
 Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4
 + ro_complete_0/a3 ro_complete_0/a2 ro_complete
 Xdivbuf_0 VDD divbuf_0/IN divbuf_0/OUT divbuf_0/OUT2 divbuf_0/OUT3 divbuf_0/OUT4 divbuf_0/OUT5
 + gnd divbuf
 Xdivbuf_1 VDD divbuf_1/IN divbuf_1/OUT divbuf_1/OUT2 divbuf_1/OUT3 divbuf_1/OUT4 divbuf_1/OUT5
 + gnd divbuf
-Xdivbuf_3 VDD divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 divbuf_3/OUT5
-+ gnd divbuf
 Xdivbuf_2 VDD divbuf_2/IN divbuf_2/OUT divbuf_2/OUT2 divbuf_2/OUT3 divbuf_2/OUT4 divbuf_2/OUT5
 + gnd divbuf
+Xdivbuf_3 VDD divbuf_3/IN divbuf_3/OUT divbuf_3/OUT2 divbuf_3/OUT3 divbuf_3/OUT4 divbuf_3/OUT5
++ gnd divbuf
 Xdivbuf_4 VDD divbuf_4/IN divbuf_4/OUT divbuf_4/OUT2 divbuf_4/OUT3 divbuf_4/OUT4 divbuf_4/OUT5
 + gnd divbuf
 Xdivbuf_5 VDD divbuf_5/IN divbuf_5/OUT divbuf_5/OUT2 divbuf_5/OUT3 divbuf_5/OUT4 divbuf_5/OUT5
@@ -318,751 +603,843 @@
 + gnd divbuf
 Xdivbuf_7 VDD divbuf_7/IN divbuf_7/OUT divbuf_7/OUT2 divbuf_7/OUT3 divbuf_7/OUT4 divbuf_7/OUT5
 + gnd divbuf
-C194 io_analog[4] VDD 25.05fF
-C195 io_analog[5] VDD 25.05fF
-C196 io_analog[6] VDD 25.05fF
-C197 io_in_3v3[0] VDD 0.61fF
-C198 io_oeb[26] VDD 0.61fF
-C199 io_in[0] VDD 0.61fF
-C200 io_out[26] VDD 0.61fF
-C201 io_out[0] VDD 0.61fF
-C202 io_in[26] VDD 0.61fF
-C203 io_oeb[0] VDD 0.61fF
-C204 io_in_3v3[26] VDD 0.61fF
-C205 io_in_3v3[1] VDD 0.61fF
-C206 io_oeb[25] VDD 0.61fF
-C207 io_in[1] VDD 0.61fF
-C208 io_out[25] VDD 0.61fF
-C209 io_out[1] VDD 0.61fF
-C210 io_in[25] VDD 0.61fF
-C211 io_oeb[1] VDD 0.61fF
-C212 io_in_3v3[25] VDD 0.61fF
-C213 io_in_3v3[2] VDD 0.61fF
-C214 io_oeb[24] VDD 0.61fF
-C215 io_in[2] VDD 0.61fF
-C216 io_out[24] VDD 0.61fF
-C217 io_out[2] VDD 0.61fF
-C218 io_in[24] VDD 0.61fF
-C219 io_oeb[2] VDD 0.61fF
-C220 io_in_3v3[24] VDD 0.61fF
-C221 io_in_3v3[3] VDD 0.61fF
-C222 gpio_noesd[17] VDD 0.61fF
-C223 io_in[3] VDD 0.61fF
-C224 gpio_analog[17] VDD 0.61fF
-C225 io_out[3] VDD 0.61fF
-C226 io_oeb[3] VDD 0.61fF
-C227 io_in_3v3[4] VDD 0.61fF
-C228 io_in[4] VDD 0.61fF
-C229 io_out[4] VDD 0.61fF
-C230 io_oeb[4] VDD 0.61fF
-C231 io_oeb[23] VDD 0.61fF
-C232 io_out[23] VDD 0.61fF
-C233 io_in[23] VDD 0.61fF
-C234 io_in_3v3[23] VDD 0.61fF
-C235 gpio_noesd[16] VDD 0.61fF
-C236 gpio_analog[16] VDD 0.61fF
-C237 io_in_3v3[5] VDD 0.61fF
-C238 io_in[5] VDD 0.61fF
-C239 io_out[5] VDD 0.61fF
-C240 io_oeb[5] VDD 0.61fF
-C241 io_oeb[22] VDD 0.61fF
-C242 io_out[22] VDD 0.61fF
-C243 io_in[22] VDD 0.61fF
-C244 io_in_3v3[22] VDD 0.61fF
-C245 gpio_noesd[15] VDD 0.61fF
-C246 gpio_analog[15] VDD 0.61fF
-C247 io_in_3v3[6] VDD 0.61fF
-C248 io_in[6] VDD 0.61fF
-C249 io_out[6] VDD 0.61fF
-C250 io_oeb[6] VDD 0.61fF
-C251 io_oeb[21] VDD 0.61fF
-C252 io_out[21] VDD 0.61fF
-C253 io_in[21] VDD 0.61fF
-C254 io_in_3v3[21] VDD 0.61fF
-C255 gpio_noesd[14] VDD 0.61fF
-C256 gpio_analog[14] VDD 0.61fF
-C257 vssa1 VDD 26.08fF
-C258 vssd2 VDD 13.04fF
-C259 vssd1 VDD 13.04fF
-C260 vdda2 VDD 13.04fF
-C261 vdda1 VDD 26.08fF
-C262 io_oeb[20] VDD 0.61fF
-C263 io_out[20] VDD 0.61fF
-C264 io_in[20] VDD 0.61fF
-C265 io_in_3v3[20] VDD 0.61fF
-C266 gpio_noesd[13] VDD 0.61fF
-C267 gpio_analog[13] VDD 0.61fF
-C268 gpio_analog[0] VDD 0.61fF
-C269 gpio_noesd[0] VDD 0.61fF
-C270 io_in_3v3[7] VDD 0.61fF
-C271 io_in[7] VDD 0.61fF
-C272 io_out[7] VDD 0.61fF
-C273 io_oeb[7] VDD 0.61fF
-C274 io_oeb[19] VDD 0.61fF
-C275 io_out[19] VDD 0.61fF
-C276 io_in[19] VDD 0.61fF
-C277 io_in_3v3[19] VDD 0.61fF
-C278 gpio_noesd[12] VDD 0.61fF
-C279 gpio_analog[12] VDD 0.61fF
-C280 gpio_analog[1] VDD 0.61fF
-C281 gpio_noesd[1] VDD 0.61fF
-C282 io_in_3v3[8] VDD 0.61fF
-C283 io_in[8] VDD 0.61fF
-C284 io_out[8] VDD 0.61fF
-C285 io_oeb[8] VDD 0.61fF
-C286 io_oeb[18] VDD 0.61fF
-C287 io_out[18] VDD 0.61fF
-C288 io_in[18] VDD 0.61fF
-C289 io_in_3v3[18] VDD 0.61fF
-C290 gpio_noesd[11] VDD 0.61fF
-C291 gpio_analog[11] VDD 0.61fF
-C292 gpio_analog[2] VDD 0.61fF
-C293 gpio_noesd[2] VDD 0.61fF
-C294 io_in_3v3[9] VDD 0.61fF
-C295 io_in[9] VDD 0.61fF
-C296 io_out[9] VDD 0.61fF
-C297 io_oeb[9] VDD 0.61fF
-C298 io_oeb[17] VDD 0.61fF
-C299 io_out[17] VDD 0.61fF
-C300 io_in[17] VDD 0.61fF
-C301 io_in_3v3[17] VDD 0.61fF
-C302 gpio_noesd[10] VDD 0.61fF
-C303 gpio_analog[10] VDD 0.61fF
-C304 gpio_analog[3] VDD 0.61fF
-C305 gpio_noesd[3] VDD 0.61fF
-C306 io_in_3v3[10] VDD 0.61fF
-C307 io_in[10] VDD 0.61fF
-C308 io_out[10] VDD 0.61fF
-C309 io_oeb[10] VDD 0.61fF
-C310 io_oeb[16] VDD 0.61fF
-C311 io_out[16] VDD 0.61fF
-C312 io_in[16] VDD 0.61fF
-C313 io_in_3v3[16] VDD 0.61fF
-C314 gpio_noesd[9] VDD 0.61fF
-C315 gpio_analog[9] VDD 0.61fF
-C316 gpio_analog[4] VDD 0.61fF
-C317 gpio_noesd[4] VDD 0.61fF
-C318 io_in_3v3[11] VDD 0.61fF
-C319 io_in[11] VDD 0.61fF
-C320 io_out[11] VDD 0.61fF
-C321 io_oeb[11] VDD 0.61fF
-C322 io_oeb[15] VDD 0.61fF
-C323 io_out[15] VDD 0.61fF
-C324 io_in[15] VDD 0.61fF
-C325 io_in_3v3[15] VDD 0.61fF
-C326 gpio_noesd[8] VDD 0.61fF
-C327 gpio_analog[8] VDD 0.61fF
-C328 gpio_analog[5] VDD 0.61fF
-C329 gpio_noesd[5] VDD 0.61fF
-C330 io_in_3v3[12] VDD 0.61fF
-C331 io_in[12] VDD 0.61fF
-C332 io_out[12] VDD 0.61fF
-C333 io_oeb[12] VDD 0.61fF
-C334 io_oeb[14] VDD 0.61fF
-C335 io_out[14] VDD 0.61fF
-C336 io_in[14] VDD 0.61fF
-C337 io_in_3v3[14] VDD 0.61fF
-C338 gpio_noesd[7] VDD 0.61fF
-C339 gpio_analog[7] VDD 0.61fF
-C340 vssa2 VDD 13.04fF
-C341 gpio_analog[6] VDD 0.61fF
-C342 gpio_noesd[6] VDD 0.61fF
-C343 io_in_3v3[13] VDD 0.61fF
-C344 io_in[13] VDD 0.61fF
-C345 io_out[13] VDD 0.61fF
-C346 io_oeb[13] VDD 0.61fF
-C347 vccd1 VDD 13.04fF
-C348 vccd2 VDD 13.04fF
-C349 io_analog[0] VDD 6.83fF
-C350 io_analog[10] VDD 6.83fF
-C351 io_analog[1] VDD 6.83fF
-C352 io_analog[2] VDD 6.83fF
-C353 io_analog[3] VDD 6.83fF
-C354 io_clamp_high[0] VDD 3.58fF
-C355 io_clamp_low[0] VDD 3.58fF
-C356 io_clamp_high[1] VDD 3.58fF
-C357 io_clamp_low[1] VDD 3.58fF
-C358 io_clamp_high[2] VDD 3.58fF
-C359 io_clamp_low[2] VDD 3.58fF
-C360 io_analog[7] VDD 6.83fF
-C361 io_analog[8] VDD 6.83fF
-C362 io_analog[9] VDD 6.83fF
-C363 user_irq[2] VDD 0.63fF
-C364 user_irq[1] VDD 0.63fF
-C365 user_irq[0] VDD 0.63fF
-C366 user_clock2 VDD 0.63fF
-C367 la_oenb[127] VDD 0.63fF
-C368 la_data_out[127] VDD 0.63fF
-C369 la_data_in[127] VDD 0.63fF
-C370 la_oenb[126] VDD 0.63fF
-C371 la_data_out[126] VDD 0.63fF
-C372 la_data_in[126] VDD 0.63fF
-C373 la_oenb[125] VDD 0.63fF
-C374 la_data_out[125] VDD 0.63fF
-C375 la_data_in[125] VDD 0.63fF
-C376 la_oenb[124] VDD 0.63fF
-C377 la_data_out[124] VDD 0.63fF
-C378 la_data_in[124] VDD 0.63fF
-C379 la_oenb[123] VDD 0.63fF
-C380 la_data_out[123] VDD 0.63fF
-C381 la_data_in[123] VDD 0.63fF
-C382 la_oenb[122] VDD 0.63fF
-C383 la_data_out[122] VDD 0.63fF
-C384 la_data_in[122] VDD 0.63fF
-C385 la_oenb[121] VDD 0.63fF
-C386 la_data_out[121] VDD 0.63fF
-C387 la_data_in[121] VDD 0.63fF
-C388 la_oenb[120] VDD 0.63fF
-C389 la_data_out[120] VDD 0.63fF
-C390 la_data_in[120] VDD 0.63fF
-C391 la_oenb[119] VDD 0.63fF
-C392 la_data_out[119] VDD 0.63fF
-C393 la_data_in[119] VDD 0.63fF
-C394 la_oenb[118] VDD 0.63fF
-C395 la_data_out[118] VDD 0.63fF
-C396 la_data_in[118] VDD 0.63fF
-C397 la_oenb[117] VDD 0.63fF
-C398 la_data_out[117] VDD 0.63fF
-C399 la_data_in[117] VDD 0.63fF
-C400 la_oenb[116] VDD 0.63fF
-C401 la_data_out[116] VDD 0.63fF
-C402 la_data_in[116] VDD 0.63fF
-C403 la_oenb[115] VDD 0.63fF
-C404 la_data_out[115] VDD 0.63fF
-C405 la_data_in[115] VDD 0.63fF
-C406 la_oenb[114] VDD 0.63fF
-C407 la_data_out[114] VDD 0.63fF
-C408 la_data_in[114] VDD 0.63fF
-C409 la_oenb[113] VDD 0.63fF
-C410 la_data_out[113] VDD 0.63fF
-C411 la_data_in[113] VDD 0.63fF
-C412 la_oenb[112] VDD 0.63fF
-C413 la_data_out[112] VDD 0.63fF
-C414 la_data_in[112] VDD 0.63fF
-C415 la_oenb[111] VDD 0.63fF
-C416 la_data_out[111] VDD 0.63fF
-C417 la_data_in[111] VDD 0.63fF
-C418 la_oenb[110] VDD 0.63fF
-C419 la_data_out[110] VDD 0.63fF
-C420 la_data_in[110] VDD 0.63fF
-C421 la_oenb[109] VDD 0.63fF
-C422 la_data_out[109] VDD 0.63fF
-C423 la_data_in[109] VDD 0.63fF
-C424 la_oenb[108] VDD 0.63fF
-C425 la_data_out[108] VDD 0.63fF
-C426 la_data_in[108] VDD 0.63fF
-C427 la_oenb[107] VDD 0.63fF
-C428 la_data_out[107] VDD 0.63fF
-C429 la_data_in[107] VDD 0.63fF
-C430 la_oenb[106] VDD 0.63fF
-C431 la_data_out[106] VDD 0.63fF
-C432 la_data_in[106] VDD 0.63fF
-C433 la_oenb[105] VDD 0.63fF
-C434 la_data_out[105] VDD 0.63fF
-C435 la_data_in[105] VDD 0.63fF
-C436 la_oenb[104] VDD 0.63fF
-C437 la_data_out[104] VDD 0.63fF
-C438 la_data_in[104] VDD 0.63fF
-C439 la_oenb[103] VDD 0.63fF
-C440 la_data_out[103] VDD 0.63fF
-C441 la_data_in[103] VDD 0.63fF
-C442 la_oenb[102] VDD 0.63fF
-C443 la_data_out[102] VDD 0.63fF
-C444 la_data_in[102] VDD 0.63fF
-C445 la_oenb[101] VDD 0.63fF
-C446 la_data_out[101] VDD 0.63fF
-C447 la_data_in[101] VDD 0.63fF
-C448 la_oenb[100] VDD 0.63fF
-C449 la_data_out[100] VDD 0.63fF
-C450 la_data_in[100] VDD 0.63fF
-C451 la_oenb[99] VDD 0.63fF
-C452 la_data_out[99] VDD 0.63fF
-C453 la_data_in[99] VDD 0.63fF
-C454 la_oenb[98] VDD 0.63fF
-C455 la_data_out[98] VDD 0.63fF
-C456 la_data_in[98] VDD 0.63fF
-C457 la_oenb[97] VDD 0.63fF
-C458 la_data_out[97] VDD 0.63fF
-C459 la_data_in[97] VDD 0.63fF
-C460 la_oenb[96] VDD 0.63fF
-C461 la_data_out[96] VDD 0.63fF
-C462 la_data_in[96] VDD 0.63fF
-C463 la_oenb[95] VDD 0.63fF
-C464 la_data_out[95] VDD 0.63fF
-C465 la_data_in[95] VDD 0.63fF
-C466 la_oenb[94] VDD 0.63fF
-C467 la_data_out[94] VDD 0.63fF
-C468 la_data_in[94] VDD 0.63fF
-C469 la_oenb[93] VDD 0.63fF
-C470 la_data_out[93] VDD 0.63fF
-C471 la_data_in[93] VDD 0.63fF
-C472 la_oenb[92] VDD 0.63fF
-C473 la_data_out[92] VDD 0.63fF
-C474 la_data_in[92] VDD 0.63fF
-C475 la_oenb[91] VDD 0.63fF
-C476 la_data_out[91] VDD 0.63fF
-C477 la_data_in[91] VDD 0.63fF
-C478 la_oenb[90] VDD 0.63fF
-C479 la_data_out[90] VDD 0.63fF
-C480 la_data_in[90] VDD 0.63fF
-C481 la_oenb[89] VDD 0.63fF
-C482 la_data_out[89] VDD 0.63fF
-C483 la_data_in[89] VDD 0.63fF
-C484 la_oenb[88] VDD 0.63fF
-C485 la_data_out[88] VDD 0.63fF
-C486 la_data_in[88] VDD 0.63fF
-C487 la_oenb[87] VDD 0.63fF
-C488 la_data_out[87] VDD 0.63fF
-C489 la_data_in[87] VDD 0.63fF
-C490 la_oenb[86] VDD 0.63fF
-C491 la_data_out[86] VDD 0.63fF
-C492 la_data_in[86] VDD 0.63fF
-C493 la_oenb[85] VDD 0.63fF
-C494 la_data_out[85] VDD 0.63fF
-C495 la_data_in[85] VDD 0.63fF
-C496 la_oenb[84] VDD 0.63fF
-C497 la_data_out[84] VDD 0.63fF
-C498 la_data_in[84] VDD 0.63fF
-C499 la_oenb[83] VDD 0.63fF
-C500 la_data_out[83] VDD 0.63fF
-C501 la_data_in[83] VDD 0.63fF
-C502 la_oenb[82] VDD 0.63fF
-C503 la_data_out[82] VDD 0.63fF
-C504 la_data_in[82] VDD 0.63fF
-C505 la_oenb[81] VDD 0.63fF
-C506 la_data_out[81] VDD 0.63fF
-C507 la_data_in[81] VDD 0.63fF
-C508 la_oenb[80] VDD 0.63fF
-C509 la_data_out[80] VDD 0.63fF
-C510 la_data_in[80] VDD 0.63fF
-C511 la_oenb[79] VDD 0.63fF
-C512 la_data_out[79] VDD 0.63fF
-C513 la_data_in[79] VDD 0.63fF
-C514 la_oenb[78] VDD 0.63fF
-C515 la_data_out[78] VDD 0.63fF
-C516 la_data_in[78] VDD 0.63fF
-C517 la_oenb[77] VDD 0.63fF
-C518 la_data_out[77] VDD 0.63fF
-C519 la_data_in[77] VDD 0.63fF
-C520 la_oenb[76] VDD 0.63fF
-C521 la_data_out[76] VDD 0.63fF
-C522 la_data_in[76] VDD 0.63fF
-C523 la_oenb[75] VDD 0.63fF
-C524 la_data_out[75] VDD 0.63fF
-C525 la_data_in[75] VDD 0.63fF
-C526 la_oenb[74] VDD 0.63fF
-C527 la_data_out[74] VDD 0.63fF
-C528 la_data_in[74] VDD 0.63fF
-C529 la_oenb[73] VDD 0.63fF
-C530 la_data_out[73] VDD 0.63fF
-C531 la_data_in[73] VDD 0.63fF
-C532 la_oenb[72] VDD 0.63fF
-C533 la_data_out[72] VDD 0.63fF
-C534 la_data_in[72] VDD 0.63fF
-C535 la_oenb[71] VDD 0.63fF
-C536 la_data_out[71] VDD 0.63fF
-C537 la_data_in[71] VDD 0.63fF
-C538 la_oenb[70] VDD 0.63fF
-C539 la_data_out[70] VDD 0.63fF
-C540 la_data_in[70] VDD 0.63fF
-C541 la_oenb[69] VDD 0.63fF
-C542 la_data_out[69] VDD 0.63fF
-C543 la_data_in[69] VDD 0.63fF
-C544 la_oenb[68] VDD 0.63fF
-C545 la_data_out[68] VDD 0.63fF
-C546 la_data_in[68] VDD 0.63fF
-C547 la_oenb[67] VDD 0.63fF
-C548 la_data_out[67] VDD 0.63fF
-C549 la_data_in[67] VDD 0.63fF
-C550 la_oenb[66] VDD 0.63fF
-C551 la_data_out[66] VDD 0.63fF
-C552 la_data_in[66] VDD 0.63fF
-C553 la_oenb[65] VDD 0.63fF
-C554 la_data_out[65] VDD 0.63fF
-C555 la_data_in[65] VDD 0.63fF
-C556 la_oenb[64] VDD 0.63fF
-C557 la_data_out[64] VDD 0.63fF
-C558 la_data_in[64] VDD 0.63fF
-C559 la_oenb[63] VDD 0.63fF
-C560 la_data_out[63] VDD 0.63fF
-C561 la_data_in[63] VDD 0.63fF
-C562 la_oenb[62] VDD 0.63fF
-C563 la_data_out[62] VDD 0.63fF
-C564 la_data_in[62] VDD 0.63fF
-C565 la_oenb[61] VDD 0.63fF
-C566 la_data_out[61] VDD 0.63fF
-C567 la_data_in[61] VDD 0.63fF
-C568 la_oenb[60] VDD 0.63fF
-C569 la_data_out[60] VDD 0.63fF
-C570 la_data_in[60] VDD 0.63fF
-C571 la_oenb[59] VDD 0.63fF
-C572 la_data_out[59] VDD 0.63fF
-C573 la_data_in[59] VDD 0.63fF
-C574 la_oenb[58] VDD 0.63fF
-C575 la_data_out[58] VDD 0.63fF
-C576 la_data_in[58] VDD 0.63fF
-C577 la_oenb[57] VDD 0.63fF
-C578 la_data_out[57] VDD 0.63fF
-C579 la_data_in[57] VDD 0.63fF
-C580 la_oenb[56] VDD 0.63fF
-C581 la_data_out[56] VDD 0.63fF
-C582 la_data_in[56] VDD 0.63fF
-C583 la_oenb[55] VDD 0.63fF
-C584 la_data_out[55] VDD 0.63fF
-C585 la_data_in[55] VDD 0.63fF
-C586 la_oenb[54] VDD 0.63fF
-C587 la_data_out[54] VDD 0.63fF
-C588 la_data_in[54] VDD 0.63fF
-C589 la_oenb[53] VDD 0.63fF
-C590 la_data_out[53] VDD 0.63fF
-C591 la_data_in[53] VDD 0.63fF
-C592 la_oenb[52] VDD 0.63fF
-C593 la_data_out[52] VDD 0.63fF
-C594 la_data_in[52] VDD 0.63fF
-C595 la_oenb[51] VDD 0.63fF
-C596 la_data_out[51] VDD 0.63fF
-C597 la_data_in[51] VDD 0.63fF
-C598 la_oenb[50] VDD 0.63fF
-C599 la_data_out[50] VDD 0.63fF
-C600 la_data_in[50] VDD 0.63fF
-C601 la_oenb[49] VDD 0.63fF
-C602 la_data_out[49] VDD 0.63fF
-C603 la_data_in[49] VDD 0.63fF
-C604 la_oenb[48] VDD 0.63fF
-C605 la_data_out[48] VDD 0.63fF
-C606 la_data_in[48] VDD 0.63fF
-C607 la_oenb[47] VDD 0.63fF
-C608 la_data_out[47] VDD 0.63fF
-C609 la_data_in[47] VDD 0.63fF
-C610 la_oenb[46] VDD 0.63fF
-C611 la_data_out[46] VDD 0.63fF
-C612 la_data_in[46] VDD 0.63fF
-C613 la_oenb[45] VDD 0.63fF
-C614 la_data_out[45] VDD 0.63fF
-C615 la_data_in[45] VDD 0.63fF
-C616 la_oenb[44] VDD 0.63fF
-C617 la_data_out[44] VDD 0.63fF
-C618 la_data_in[44] VDD 0.63fF
-C619 la_oenb[43] VDD 0.63fF
-C620 la_data_out[43] VDD 0.63fF
-C621 la_data_in[43] VDD 0.63fF
-C622 la_oenb[42] VDD 0.63fF
-C623 la_data_out[42] VDD 0.63fF
-C624 la_data_in[42] VDD 0.63fF
-C625 la_oenb[41] VDD 0.63fF
-C626 la_data_out[41] VDD 0.63fF
-C627 la_data_in[41] VDD 0.63fF
-C628 la_oenb[40] VDD 0.63fF
-C629 la_data_out[40] VDD 0.63fF
-C630 la_data_in[40] VDD 0.63fF
-C631 la_oenb[39] VDD 0.63fF
-C632 la_data_out[39] VDD 0.63fF
-C633 la_data_in[39] VDD 0.63fF
-C634 la_oenb[38] VDD 0.63fF
-C635 la_data_out[38] VDD 0.63fF
-C636 la_data_in[38] VDD 0.63fF
-C637 la_oenb[37] VDD 0.63fF
-C638 la_data_out[37] VDD 0.63fF
-C639 la_data_in[37] VDD 0.63fF
-C640 la_oenb[36] VDD 0.63fF
-C641 la_data_out[36] VDD 0.63fF
-C642 la_data_in[36] VDD 0.63fF
-C643 la_oenb[35] VDD 0.63fF
-C644 la_data_out[35] VDD 0.63fF
-C645 la_data_in[35] VDD 0.63fF
-C646 la_oenb[34] VDD 0.63fF
-C647 la_data_out[34] VDD 0.63fF
-C648 la_data_in[34] VDD 0.63fF
-C649 la_oenb[33] VDD 0.63fF
-C650 la_data_out[33] VDD 0.63fF
-C651 la_data_in[33] VDD 0.63fF
-C652 la_oenb[32] VDD 0.63fF
-C653 la_data_out[32] VDD 0.63fF
-C654 la_data_in[32] VDD 0.63fF
-C655 la_oenb[31] VDD 0.63fF
-C656 la_data_out[31] VDD 0.63fF
-C657 la_data_in[31] VDD 0.63fF
-C658 la_oenb[30] VDD 0.63fF
-C659 la_data_out[30] VDD 0.63fF
-C660 la_data_in[30] VDD 0.63fF
-C661 la_oenb[29] VDD 0.63fF
-C662 la_data_out[29] VDD 0.63fF
-C663 la_data_in[29] VDD 0.63fF
-C664 la_oenb[28] VDD 0.63fF
-C665 la_data_out[28] VDD 0.63fF
-C666 la_data_in[28] VDD 0.63fF
-C667 la_oenb[27] VDD 0.63fF
-C668 la_data_out[27] VDD 0.63fF
-C669 la_data_in[27] VDD 0.63fF
-C670 la_oenb[26] VDD 0.63fF
-C671 la_data_out[26] VDD 0.63fF
-C672 la_data_in[26] VDD 0.63fF
-C673 la_oenb[25] VDD 0.63fF
-C674 la_data_out[25] VDD 0.63fF
-C675 la_data_in[25] VDD 0.63fF
-C676 la_oenb[24] VDD 0.63fF
-C677 la_data_out[24] VDD 0.63fF
-C678 la_data_in[24] VDD 0.63fF
-C679 la_oenb[23] VDD 0.63fF
-C680 la_data_out[23] VDD 0.63fF
-C681 la_data_in[23] VDD 0.63fF
-C682 la_oenb[22] VDD 0.63fF
-C683 la_data_out[22] VDD 0.63fF
-C684 la_data_in[22] VDD 0.63fF
-C685 la_oenb[21] VDD 0.63fF
-C686 la_data_out[21] VDD 0.63fF
-C687 la_data_in[21] VDD 0.63fF
-C688 la_oenb[20] VDD 0.63fF
-C689 la_data_out[20] VDD 0.63fF
-C690 la_data_in[20] VDD 0.63fF
-C691 la_oenb[19] VDD 0.63fF
-C692 la_data_out[19] VDD 0.63fF
-C693 la_data_in[19] VDD 0.63fF
-C694 la_oenb[18] VDD 0.63fF
-C695 la_data_out[18] VDD 0.63fF
-C696 la_data_in[18] VDD 0.63fF
-C697 la_oenb[17] VDD 0.63fF
-C698 la_data_out[17] VDD 0.63fF
-C699 la_data_in[17] VDD 0.63fF
-C700 la_oenb[16] VDD 0.63fF
-C701 la_data_out[16] VDD 0.63fF
-C702 la_data_in[16] VDD 0.63fF
-C703 la_oenb[15] VDD 0.63fF
-C704 la_data_out[15] VDD 0.63fF
-C705 la_data_in[15] VDD 0.63fF
-C706 la_oenb[14] VDD 0.63fF
-C707 la_data_out[14] VDD 0.63fF
-C708 la_data_in[14] VDD 0.63fF
-C709 la_oenb[13] VDD 0.63fF
-C710 la_data_out[13] VDD 0.63fF
-C711 la_data_in[13] VDD 0.63fF
-C712 la_oenb[12] VDD 0.63fF
-C713 la_data_out[12] VDD 0.63fF
-C714 la_data_in[12] VDD 0.63fF
-C715 la_oenb[11] VDD 0.63fF
-C716 la_data_out[11] VDD 0.63fF
-C717 la_data_in[11] VDD 0.63fF
-C718 la_oenb[10] VDD 0.63fF
-C719 la_data_out[10] VDD 0.63fF
-C720 la_data_in[10] VDD 0.63fF
-C721 la_oenb[9] VDD 0.63fF
-C722 la_data_out[9] VDD 0.63fF
-C723 la_data_in[9] VDD 0.63fF
-C724 la_oenb[8] VDD 0.63fF
-C725 la_data_out[8] VDD 0.63fF
-C726 la_data_in[8] VDD 0.63fF
-C727 la_oenb[7] VDD 0.63fF
-C728 la_data_out[7] VDD 0.63fF
-C729 la_data_in[7] VDD 0.63fF
-C730 la_oenb[6] VDD 0.63fF
-C731 la_data_out[6] VDD 0.63fF
-C732 la_data_in[6] VDD 0.63fF
-C733 la_oenb[5] VDD 0.63fF
-C734 la_data_out[5] VDD 0.63fF
-C735 la_data_in[5] VDD 0.63fF
-C736 la_oenb[4] VDD 0.63fF
-C737 la_data_out[4] VDD 0.63fF
-C738 la_data_in[4] VDD 0.63fF
-C739 la_oenb[3] VDD 0.63fF
-C740 la_data_out[3] VDD 0.63fF
-C741 la_data_in[3] VDD 0.63fF
-C742 la_oenb[2] VDD 0.63fF
-C743 la_data_out[2] VDD 0.63fF
-C744 la_data_in[2] VDD 0.63fF
-C745 la_oenb[1] VDD 0.63fF
-C746 la_data_out[1] VDD 0.63fF
-C747 la_data_in[1] VDD 0.63fF
-C748 la_oenb[0] VDD 0.63fF
-C749 la_data_out[0] VDD 0.63fF
-C750 la_data_in[0] VDD 0.63fF
-C751 wbs_dat_o[31] VDD 0.63fF
-C752 wbs_dat_i[31] VDD 0.63fF
-C753 wbs_adr_i[31] VDD 0.63fF
-C754 wbs_dat_o[30] VDD 0.63fF
-C755 wbs_dat_i[30] VDD 0.63fF
-C756 wbs_adr_i[30] VDD 0.63fF
-C757 wbs_dat_o[29] VDD 0.63fF
-C758 wbs_dat_i[29] VDD 0.63fF
-C759 wbs_adr_i[29] VDD 0.63fF
-C760 wbs_dat_o[28] VDD 0.63fF
-C761 wbs_dat_i[28] VDD 0.63fF
-C762 wbs_adr_i[28] VDD 0.63fF
-C763 wbs_dat_o[27] VDD 0.63fF
-C764 wbs_dat_i[27] VDD 0.63fF
-C765 wbs_adr_i[27] VDD 0.63fF
-C766 wbs_dat_o[26] VDD 0.63fF
-C767 wbs_dat_i[26] VDD 0.63fF
-C768 wbs_adr_i[26] VDD 0.63fF
-C769 wbs_dat_o[25] VDD 0.63fF
-C770 wbs_dat_i[25] VDD 0.63fF
-C771 wbs_adr_i[25] VDD 0.63fF
-C772 wbs_dat_o[24] VDD 0.63fF
-C773 wbs_dat_i[24] VDD 0.63fF
-C774 wbs_adr_i[24] VDD 0.63fF
-C775 wbs_dat_o[23] VDD 0.63fF
-C776 wbs_dat_i[23] VDD 0.63fF
-C777 wbs_adr_i[23] VDD 0.63fF
-C778 wbs_dat_o[22] VDD 0.63fF
-C779 wbs_dat_i[22] VDD 0.63fF
-C780 wbs_adr_i[22] VDD 0.63fF
-C781 wbs_dat_o[21] VDD 0.63fF
-C782 wbs_dat_i[21] VDD 0.63fF
-C783 wbs_adr_i[21] VDD 0.63fF
-C784 wbs_dat_o[20] VDD 0.63fF
-C785 wbs_dat_i[20] VDD 0.63fF
-C786 wbs_adr_i[20] VDD 0.63fF
-C787 wbs_dat_o[19] VDD 0.63fF
-C788 wbs_dat_i[19] VDD 0.63fF
-C789 wbs_adr_i[19] VDD 0.63fF
-C790 wbs_dat_o[18] VDD 0.63fF
-C791 wbs_dat_i[18] VDD 0.63fF
-C792 wbs_adr_i[18] VDD 0.63fF
-C793 wbs_dat_o[17] VDD 0.63fF
-C794 wbs_dat_i[17] VDD 0.63fF
-C795 wbs_adr_i[17] VDD 0.63fF
-C796 wbs_dat_o[16] VDD 0.63fF
-C797 wbs_dat_i[16] VDD 0.63fF
-C798 wbs_adr_i[16] VDD 0.63fF
-C799 wbs_dat_o[15] VDD 0.63fF
-C800 wbs_dat_i[15] VDD 0.63fF
-C801 wbs_adr_i[15] VDD 0.63fF
-C802 wbs_dat_o[14] VDD 0.63fF
-C803 wbs_dat_i[14] VDD 0.63fF
-C804 wbs_adr_i[14] VDD 0.63fF
-C805 wbs_dat_o[13] VDD 0.63fF
-C806 wbs_dat_i[13] VDD 0.63fF
-C807 wbs_adr_i[13] VDD 0.63fF
-C808 wbs_dat_o[12] VDD 0.63fF
-C809 wbs_dat_i[12] VDD 0.63fF
-C810 wbs_adr_i[12] VDD 0.63fF
-C811 wbs_dat_o[11] VDD 0.63fF
-C812 wbs_dat_i[11] VDD 0.63fF
-C813 wbs_adr_i[11] VDD 0.63fF
-C814 wbs_dat_o[10] VDD 0.63fF
-C815 wbs_dat_i[10] VDD 0.63fF
-C816 wbs_adr_i[10] VDD 0.63fF
-C817 wbs_dat_o[9] VDD 0.63fF
-C818 wbs_dat_i[9] VDD 0.63fF
-C819 wbs_adr_i[9] VDD 0.63fF
-C820 wbs_dat_o[8] VDD 0.63fF
-C821 wbs_dat_i[8] VDD 0.63fF
-C822 wbs_adr_i[8] VDD 0.63fF
-C823 wbs_dat_o[7] VDD 0.63fF
-C824 wbs_dat_i[7] VDD 0.63fF
-C825 wbs_adr_i[7] VDD 0.63fF
-C826 wbs_dat_o[6] VDD 0.63fF
-C827 wbs_dat_i[6] VDD 0.63fF
-C828 wbs_adr_i[6] VDD 0.63fF
-C829 wbs_dat_o[5] VDD 0.63fF
-C830 wbs_dat_i[5] VDD 0.63fF
-C831 wbs_adr_i[5] VDD 0.63fF
-C832 wbs_dat_o[4] VDD 0.63fF
-C833 wbs_dat_i[4] VDD 0.63fF
-C834 wbs_adr_i[4] VDD 0.63fF
-C835 wbs_sel_i[3] VDD 0.63fF
-C836 wbs_dat_o[3] VDD 0.63fF
-C837 wbs_dat_i[3] VDD 0.63fF
-C838 wbs_adr_i[3] VDD 0.63fF
-C839 wbs_sel_i[2] VDD 0.63fF
-C840 wbs_dat_o[2] VDD 0.63fF
-C841 wbs_dat_i[2] VDD 0.63fF
-C842 wbs_adr_i[2] VDD 0.63fF
-C843 wbs_sel_i[1] VDD 0.63fF
-C844 wbs_dat_o[1] VDD 0.63fF
-C845 wbs_dat_i[1] VDD 0.63fF
-C846 wbs_adr_i[1] VDD 0.63fF
-C847 wbs_sel_i[0] VDD 0.63fF
-C848 wbs_dat_o[0] VDD 0.63fF
-C849 wbs_dat_i[0] VDD 0.63fF
-C850 wbs_adr_i[0] VDD 0.63fF
-C851 wbs_we_i VDD 0.63fF
-C852 wbs_stb_i VDD 0.63fF
-C853 wbs_cyc_i VDD 0.63fF
-C854 wbs_ack_o VDD 0.63fF
-C855 wb_rst_i VDD 0.63fF
-C856 wb_clk_i VDD 0.63fF
-C857 divbuf_7/OUT VDD 363.82fF
-C858 divbuf_7/OUT5 VDD 350.37fF
-C859 divbuf_7/OUT4 VDD 133.72fF
-C860 divbuf_7/OUT3 VDD 34.03fF
-C861 divbuf_7/OUT2 VDD 8.71fF
-C862 divbuf_7/IN VDD 0.89fF
-C863 divbuf_7/a_492_n240# VDD 2.46fF **FLOATING
-C864 divbuf_6/OUT VDD 363.82fF
-C865 divbuf_6/OUT5 VDD 350.37fF
-C866 divbuf_6/OUT4 VDD 133.72fF
-C867 divbuf_6/OUT3 VDD 34.03fF
-C868 divbuf_6/OUT2 VDD 8.71fF
-C869 divbuf_6/IN VDD 0.89fF
-C870 divbuf_6/a_492_n240# VDD 2.46fF **FLOATING
-C871 divbuf_5/OUT VDD 363.82fF
-C872 divbuf_5/OUT5 VDD 350.37fF
-C873 divbuf_5/OUT4 VDD 133.72fF
-C874 divbuf_5/OUT3 VDD 34.03fF
-C875 divbuf_5/OUT2 VDD 8.71fF
-C876 divbuf_5/IN VDD 0.89fF
-C877 divbuf_5/a_492_n240# VDD 2.46fF **FLOATING
-C878 divbuf_4/OUT VDD 363.82fF
-C879 divbuf_4/OUT5 VDD 350.37fF
-C880 divbuf_4/OUT4 VDD 133.72fF
-C881 divbuf_4/OUT3 VDD 34.03fF
-C882 divbuf_4/OUT2 VDD 8.71fF
-C883 divbuf_4/IN VDD 0.89fF
-C884 divbuf_4/a_492_n240# VDD 2.46fF **FLOATING
-C885 divbuf_2/OUT VDD 363.82fF
-C886 divbuf_2/OUT5 VDD 350.37fF
-C887 divbuf_2/OUT4 VDD 133.72fF
-C888 divbuf_2/OUT3 VDD 34.03fF
-C889 divbuf_2/OUT2 VDD 8.71fF
-C890 divbuf_2/IN VDD 0.89fF
-C891 divbuf_2/a_492_n240# VDD 2.46fF **FLOATING
-C892 divbuf_3/OUT VDD 363.82fF
-C893 divbuf_3/OUT5 VDD 350.37fF
-C894 divbuf_3/OUT4 VDD 133.72fF
-C895 divbuf_3/OUT3 VDD 34.03fF
-C896 divbuf_3/OUT2 VDD 8.71fF
-C897 divbuf_3/IN VDD 0.89fF
-C898 divbuf_3/a_492_n240# VDD 2.46fF **FLOATING
-C899 divbuf_1/OUT VDD 363.82fF
-C900 divbuf_1/OUT5 VDD 350.37fF
-C901 divbuf_1/OUT4 VDD 133.72fF
-C902 divbuf_1/OUT3 VDD 34.03fF
-C903 divbuf_1/OUT2 VDD 8.71fF
-C904 divbuf_1/IN VDD 0.89fF
-C905 divbuf_1/a_492_n240# VDD 2.46fF **FLOATING
-C906 divbuf_0/OUT VDD 363.82fF
-C907 divbuf_0/OUT5 VDD 350.37fF
-C908 divbuf_0/OUT4 VDD 133.72fF
-C909 divbuf_0/OUT3 VDD 34.03fF
-C910 divbuf_0/OUT2 VDD 8.71fF
-C911 divbuf_0/IN VDD 0.89fF
-C912 divbuf_0/a_492_n240# VDD 2.46fF **FLOATING
-C913 ro_complete_0/cbank_2/v VDD 17.84fF
-C914 ro_complete_0/cbank_2/switch_5/vin VDD 0.78fF
-C915 ro_complete_0/cbank_2/switch_4/vin VDD 1.50fF
-C916 ro_complete_0/cbank_2/switch_2/vin VDD 1.30fF
-C917 ro_complete_0/cbank_2/switch_3/vin VDD 0.56fF
-C918 ro_complete_0/cbank_2/switch_1/vin VDD 1.14fF
-C919 ro_complete_0/cbank_2/switch_0/vin VDD 1.02fF
-C920 ro_complete_0/cbank_1/v VDD 16.34fF
-C921 ro_complete_0/cbank_1/switch_5/vin VDD 0.78fF
-C922 ro_complete_0/a0 VDD 7.88fF
-C923 ro_complete_0/cbank_1/switch_4/vin VDD 1.50fF
-C924 ro_complete_0/a1 VDD 5.39fF
-C925 ro_complete_0/cbank_1/switch_2/vin VDD 1.30fF
-C926 ro_complete_0/a3 VDD 6.85fF
-C927 ro_complete_0/cbank_1/switch_3/vin VDD 0.56fF
-C928 ro_complete_0/a2 VDD 5.48fF
-C929 ro_complete_0/cbank_1/switch_1/vin VDD 1.14fF
-C930 ro_complete_0/a4 VDD 5.36fF
-C931 ro_complete_0/cbank_1/switch_0/vin VDD 1.02fF
-C932 ro_complete_0/a5 VDD 5.19fF
-C933 ro_complete_0/cbank_0/v VDD 14.98fF
-C934 ro_complete_0/cbank_0/switch_5/vin VDD 0.78fF
-C935 ro_complete_0/cbank_0/switch_4/vin VDD 1.50fF
-C936 ro_complete_0/cbank_0/switch_2/vin VDD 1.30fF
-C937 ro_complete_0/cbank_0/switch_3/vin VDD 0.56fF
-C938 ro_complete_0/cbank_0/switch_1/vin VDD 1.14fF
-C939 ro_complete_0/cbank_0/switch_0/vin VDD 1.02fF
-C940 ro_complete_0/ro_var_extend_0/vcont VDD 0.27fF
+Xdivider_0 gnd vdd divider_0/Out divider_0/clk divider_0/mc2 divider
+C476 io_analog[4] vdd 25.05fF
+C477 io_analog[5] vdd 25.05fF
+C478 io_analog[6] vdd 25.05fF
+C479 io_in_3v3[0] vdd 0.61fF
+C480 io_oeb[26] vdd 0.61fF
+C481 io_in[0] vdd 0.61fF
+C482 io_out[26] vdd 0.61fF
+C483 io_out[0] vdd 0.61fF
+C484 io_in[26] vdd 0.61fF
+C485 io_oeb[0] vdd 0.61fF
+C486 io_in_3v3[26] vdd 0.61fF
+C487 io_in_3v3[1] vdd 0.61fF
+C488 io_oeb[25] vdd 0.61fF
+C489 io_in[1] vdd 0.61fF
+C490 io_out[25] vdd 0.61fF
+C491 io_out[1] vdd 0.61fF
+C492 io_in[25] vdd 0.61fF
+C493 io_oeb[1] vdd 0.61fF
+C494 io_in_3v3[25] vdd 0.61fF
+C495 io_in_3v3[2] vdd 0.61fF
+C496 io_oeb[24] vdd 0.61fF
+C497 io_in[2] vdd 0.61fF
+C498 io_out[24] vdd 0.61fF
+C499 io_out[2] vdd 0.61fF
+C500 io_in[24] vdd 0.61fF
+C501 io_oeb[2] vdd 0.61fF
+C502 io_in_3v3[24] vdd 0.61fF
+C503 io_in_3v3[3] vdd 0.61fF
+C504 gpio_noesd[17] vdd 0.61fF
+C505 io_in[3] vdd 0.61fF
+C506 gpio_analog[17] vdd 0.61fF
+C507 io_out[3] vdd 0.61fF
+C508 io_oeb[3] vdd 0.61fF
+C509 io_in_3v3[4] vdd 0.61fF
+C510 io_in[4] vdd 0.61fF
+C511 io_out[4] vdd 0.61fF
+C512 io_oeb[4] vdd 0.61fF
+C513 io_oeb[23] vdd 0.61fF
+C514 io_out[23] vdd 0.61fF
+C515 io_in[23] vdd 0.61fF
+C516 io_in_3v3[23] vdd 0.61fF
+C517 gpio_noesd[16] vdd 0.61fF
+C518 gpio_analog[16] vdd 0.61fF
+C519 io_in_3v3[5] vdd 0.61fF
+C520 io_in[5] vdd 0.61fF
+C521 io_out[5] vdd 0.61fF
+C522 io_oeb[5] vdd 0.61fF
+C523 io_oeb[22] vdd 0.61fF
+C524 io_out[22] vdd 0.61fF
+C525 io_in[22] vdd 0.61fF
+C526 io_in_3v3[22] vdd 0.61fF
+C527 gpio_noesd[15] vdd 0.61fF
+C528 gpio_analog[15] vdd 0.61fF
+C529 io_in_3v3[6] vdd 0.61fF
+C530 io_in[6] vdd 0.61fF
+C531 io_out[6] vdd 0.61fF
+C532 io_oeb[6] vdd 0.61fF
+C533 io_oeb[21] vdd 0.61fF
+C534 io_out[21] vdd 0.61fF
+C535 io_in[21] vdd 0.61fF
+C536 io_in_3v3[21] vdd 0.61fF
+C537 gpio_noesd[14] vdd 0.61fF
+C538 gpio_analog[14] vdd 0.61fF
+C539 vssa1 vdd 26.08fF
+C540 vssd2 vdd 13.04fF
+C541 vssd1 vdd 13.04fF
+C542 vdda2 vdd 13.04fF
+C543 vdda1 vdd 26.08fF
+C544 io_oeb[20] vdd 0.61fF
+C545 io_out[20] vdd 0.61fF
+C546 io_in[20] vdd 0.61fF
+C547 io_in_3v3[20] vdd 0.61fF
+C548 gpio_noesd[13] vdd 0.61fF
+C549 gpio_analog[13] vdd 0.61fF
+C550 gpio_analog[0] vdd 0.61fF
+C551 gpio_noesd[0] vdd 0.61fF
+C552 io_in_3v3[7] vdd 0.61fF
+C553 io_in[7] vdd 0.61fF
+C554 io_out[7] vdd 0.61fF
+C555 io_oeb[7] vdd 0.61fF
+C556 io_oeb[19] vdd 0.61fF
+C557 io_out[19] vdd 0.61fF
+C558 io_in[19] vdd 0.61fF
+C559 io_in_3v3[19] vdd 0.61fF
+C560 gpio_noesd[12] vdd 0.61fF
+C561 gpio_analog[12] vdd 0.61fF
+C562 gpio_analog[1] vdd 0.61fF
+C563 gpio_noesd[1] vdd 0.61fF
+C564 io_in_3v3[8] vdd 0.61fF
+C565 io_in[8] vdd 0.61fF
+C566 io_out[8] vdd 0.61fF
+C567 io_oeb[8] vdd 0.61fF
+C568 io_oeb[18] vdd 0.61fF
+C569 io_out[18] vdd 0.61fF
+C570 io_in[18] vdd 0.61fF
+C571 io_in_3v3[18] vdd 0.61fF
+C572 gpio_noesd[11] vdd 0.61fF
+C573 gpio_analog[11] vdd 0.61fF
+C574 gpio_analog[2] vdd 0.61fF
+C575 gpio_noesd[2] vdd 0.61fF
+C576 io_in_3v3[9] vdd 0.61fF
+C577 io_in[9] vdd 0.61fF
+C578 io_out[9] vdd 0.61fF
+C579 io_oeb[9] vdd 0.61fF
+C580 io_oeb[17] vdd 0.61fF
+C581 io_out[17] vdd 0.61fF
+C582 io_in[17] vdd 0.61fF
+C583 io_in_3v3[17] vdd 0.61fF
+C584 gpio_noesd[10] vdd 0.61fF
+C585 gpio_analog[10] vdd 0.61fF
+C586 gpio_analog[3] vdd 0.61fF
+C587 gpio_noesd[3] vdd 0.61fF
+C588 io_in_3v3[10] vdd 0.61fF
+C589 io_in[10] vdd 0.61fF
+C590 io_out[10] vdd 0.61fF
+C591 io_oeb[10] vdd 0.61fF
+C592 io_oeb[16] vdd 0.61fF
+C593 io_out[16] vdd 0.61fF
+C594 io_in[16] vdd 0.61fF
+C595 io_in_3v3[16] vdd 0.61fF
+C596 gpio_noesd[9] vdd 0.61fF
+C597 gpio_analog[9] vdd 0.61fF
+C598 gpio_analog[4] vdd 0.61fF
+C599 gpio_noesd[4] vdd 0.61fF
+C600 io_in_3v3[11] vdd 0.61fF
+C601 io_in[11] vdd 0.61fF
+C602 io_out[11] vdd 0.61fF
+C603 io_oeb[11] vdd 0.61fF
+C604 io_oeb[15] vdd 0.61fF
+C605 io_out[15] vdd 0.61fF
+C606 io_in[15] vdd 0.61fF
+C607 io_in_3v3[15] vdd 0.61fF
+C608 gpio_noesd[8] vdd 0.61fF
+C609 gpio_analog[8] vdd 0.61fF
+C610 gpio_analog[5] vdd 0.61fF
+C611 gpio_noesd[5] vdd 0.61fF
+C612 io_in_3v3[12] vdd 0.61fF
+C613 io_in[12] vdd 0.61fF
+C614 io_out[12] vdd 0.61fF
+C615 io_oeb[12] vdd 0.61fF
+C616 io_oeb[14] vdd 0.61fF
+C617 io_out[14] vdd 0.61fF
+C618 io_in[14] vdd 0.61fF
+C619 io_in_3v3[14] vdd 0.61fF
+C620 gpio_noesd[7] vdd 0.61fF
+C621 gpio_analog[7] vdd 0.61fF
+C622 vssa2 vdd 13.04fF
+C623 gpio_analog[6] vdd 0.61fF
+C624 gpio_noesd[6] vdd 0.61fF
+C625 io_in_3v3[13] vdd 0.61fF
+C626 io_in[13] vdd 0.61fF
+C627 io_out[13] vdd 0.61fF
+C628 io_oeb[13] vdd 0.61fF
+C629 vccd1 vdd 13.04fF
+C630 vccd2 vdd 13.04fF
+C631 io_analog[0] vdd 6.83fF
+C632 io_analog[10] vdd 6.83fF
+C633 io_analog[1] vdd 6.83fF
+C634 io_analog[2] vdd 6.83fF
+C635 io_analog[3] vdd 6.83fF
+C636 io_clamp_high[0] vdd 3.58fF
+C637 io_clamp_low[0] vdd 3.58fF
+C638 io_clamp_high[1] vdd 3.58fF
+C639 io_clamp_low[1] vdd 3.58fF
+C640 io_clamp_high[2] vdd 3.58fF
+C641 io_clamp_low[2] vdd 3.58fF
+C642 io_analog[7] vdd 6.83fF
+C643 io_analog[8] vdd 6.83fF
+C644 io_analog[9] vdd 6.83fF
+C645 user_irq[2] vdd 0.63fF
+C646 user_irq[1] vdd 0.63fF
+C647 user_irq[0] vdd 0.63fF
+C648 user_clock2 vdd 0.63fF
+C649 la_oenb[127] vdd 0.63fF
+C650 la_data_out[127] vdd 0.63fF
+C651 la_data_in[127] vdd 0.63fF
+C652 la_oenb[126] vdd 0.63fF
+C653 la_data_out[126] vdd 0.63fF
+C654 la_data_in[126] vdd 0.63fF
+C655 la_oenb[125] vdd 0.63fF
+C656 la_data_out[125] vdd 0.63fF
+C657 la_data_in[125] vdd 0.63fF
+C658 la_oenb[124] vdd 0.63fF
+C659 la_data_out[124] vdd 0.63fF
+C660 la_data_in[124] vdd 0.63fF
+C661 la_oenb[123] vdd 0.63fF
+C662 la_data_out[123] vdd 0.63fF
+C663 la_data_in[123] vdd 0.63fF
+C664 la_oenb[122] vdd 0.63fF
+C665 la_data_out[122] vdd 0.63fF
+C666 la_data_in[122] vdd 0.63fF
+C667 la_oenb[121] vdd 0.63fF
+C668 la_data_out[121] vdd 0.63fF
+C669 la_data_in[121] vdd 0.63fF
+C670 la_oenb[120] vdd 0.63fF
+C671 la_data_out[120] vdd 0.63fF
+C672 la_data_in[120] vdd 0.63fF
+C673 la_oenb[119] vdd 0.63fF
+C674 la_data_out[119] vdd 0.63fF
+C675 la_data_in[119] vdd 0.63fF
+C676 la_oenb[118] vdd 0.63fF
+C677 la_data_out[118] vdd 0.63fF
+C678 la_data_in[118] vdd 0.63fF
+C679 la_oenb[117] vdd 0.63fF
+C680 la_data_out[117] vdd 0.63fF
+C681 la_data_in[117] vdd 0.63fF
+C682 la_oenb[116] vdd 0.63fF
+C683 la_data_out[116] vdd 0.63fF
+C684 la_data_in[116] vdd 0.63fF
+C685 la_oenb[115] vdd 0.63fF
+C686 la_data_out[115] vdd 0.63fF
+C687 la_data_in[115] vdd 0.63fF
+C688 la_oenb[114] vdd 0.63fF
+C689 la_data_out[114] vdd 0.63fF
+C690 la_data_in[114] vdd 0.63fF
+C691 la_oenb[113] vdd 0.63fF
+C692 la_data_out[113] vdd 0.63fF
+C693 la_data_in[113] vdd 0.63fF
+C694 la_oenb[112] vdd 0.63fF
+C695 la_data_out[112] vdd 0.63fF
+C696 la_data_in[112] vdd 0.63fF
+C697 la_oenb[111] vdd 0.63fF
+C698 la_data_out[111] vdd 0.63fF
+C699 la_data_in[111] vdd 0.63fF
+C700 la_oenb[110] vdd 0.63fF
+C701 la_data_out[110] vdd 0.63fF
+C702 la_data_in[110] vdd 0.63fF
+C703 la_oenb[109] vdd 0.63fF
+C704 la_data_out[109] vdd 0.63fF
+C705 la_data_in[109] vdd 0.63fF
+C706 la_oenb[108] vdd 0.63fF
+C707 la_data_out[108] vdd 0.63fF
+C708 la_data_in[108] vdd 0.63fF
+C709 la_oenb[107] vdd 0.63fF
+C710 la_data_out[107] vdd 0.63fF
+C711 la_data_in[107] vdd 0.63fF
+C712 la_oenb[106] vdd 0.63fF
+C713 la_data_out[106] vdd 0.63fF
+C714 la_data_in[106] vdd 0.63fF
+C715 la_oenb[105] vdd 0.63fF
+C716 la_data_out[105] vdd 0.63fF
+C717 la_data_in[105] vdd 0.63fF
+C718 la_oenb[104] vdd 0.63fF
+C719 la_data_out[104] vdd 0.63fF
+C720 la_data_in[104] vdd 0.63fF
+C721 la_oenb[103] vdd 0.63fF
+C722 la_data_out[103] vdd 0.63fF
+C723 la_data_in[103] vdd 0.63fF
+C724 la_oenb[102] vdd 0.63fF
+C725 la_data_out[102] vdd 0.63fF
+C726 la_data_in[102] vdd 0.63fF
+C727 la_oenb[101] vdd 0.63fF
+C728 la_data_out[101] vdd 0.63fF
+C729 la_data_in[101] vdd 0.63fF
+C730 la_oenb[100] vdd 0.63fF
+C731 la_data_out[100] vdd 0.63fF
+C732 la_data_in[100] vdd 0.63fF
+C733 la_oenb[99] vdd 0.63fF
+C734 la_data_out[99] vdd 0.63fF
+C735 la_data_in[99] vdd 0.63fF
+C736 la_oenb[98] vdd 0.63fF
+C737 la_data_out[98] vdd 0.63fF
+C738 la_data_in[98] vdd 0.63fF
+C739 la_oenb[97] vdd 0.63fF
+C740 la_data_out[97] vdd 0.63fF
+C741 la_data_in[97] vdd 0.63fF
+C742 la_oenb[96] vdd 0.63fF
+C743 la_data_out[96] vdd 0.63fF
+C744 la_data_in[96] vdd 0.63fF
+C745 la_oenb[95] vdd 0.63fF
+C746 la_data_out[95] vdd 0.63fF
+C747 la_data_in[95] vdd 0.63fF
+C748 la_oenb[94] vdd 0.63fF
+C749 la_data_out[94] vdd 0.63fF
+C750 la_data_in[94] vdd 0.63fF
+C751 la_oenb[93] vdd 0.63fF
+C752 la_data_out[93] vdd 0.63fF
+C753 la_data_in[93] vdd 0.63fF
+C754 la_oenb[92] vdd 0.63fF
+C755 la_data_out[92] vdd 0.63fF
+C756 la_data_in[92] vdd 0.63fF
+C757 la_oenb[91] vdd 0.63fF
+C758 la_data_out[91] vdd 0.63fF
+C759 la_data_in[91] vdd 0.63fF
+C760 la_oenb[90] vdd 0.63fF
+C761 la_data_out[90] vdd 0.63fF
+C762 la_data_in[90] vdd 0.63fF
+C763 la_oenb[89] vdd 0.63fF
+C764 la_data_out[89] vdd 0.63fF
+C765 la_data_in[89] vdd 0.63fF
+C766 la_oenb[88] vdd 0.63fF
+C767 la_data_out[88] vdd 0.63fF
+C768 la_data_in[88] vdd 0.63fF
+C769 la_oenb[87] vdd 0.63fF
+C770 la_data_out[87] vdd 0.63fF
+C771 la_data_in[87] vdd 0.63fF
+C772 la_oenb[86] vdd 0.63fF
+C773 la_data_out[86] vdd 0.63fF
+C774 la_data_in[86] vdd 0.63fF
+C775 la_oenb[85] vdd 0.63fF
+C776 la_data_out[85] vdd 0.63fF
+C777 la_data_in[85] vdd 0.63fF
+C778 la_oenb[84] vdd 0.63fF
+C779 la_data_out[84] vdd 0.63fF
+C780 la_data_in[84] vdd 0.63fF
+C781 la_oenb[83] vdd 0.63fF
+C782 la_data_out[83] vdd 0.63fF
+C783 la_data_in[83] vdd 0.63fF
+C784 la_oenb[82] vdd 0.63fF
+C785 la_data_out[82] vdd 0.63fF
+C786 la_data_in[82] vdd 0.63fF
+C787 la_oenb[81] vdd 0.63fF
+C788 la_data_out[81] vdd 0.63fF
+C789 la_data_in[81] vdd 0.63fF
+C790 la_oenb[80] vdd 0.63fF
+C791 la_data_out[80] vdd 0.63fF
+C792 la_data_in[80] vdd 0.63fF
+C793 la_oenb[79] vdd 0.63fF
+C794 la_data_out[79] vdd 0.63fF
+C795 la_data_in[79] vdd 0.63fF
+C796 la_oenb[78] vdd 0.63fF
+C797 la_data_out[78] vdd 0.63fF
+C798 la_data_in[78] vdd 0.63fF
+C799 la_oenb[77] vdd 0.63fF
+C800 la_data_out[77] vdd 0.63fF
+C801 la_data_in[77] vdd 0.63fF
+C802 la_oenb[76] vdd 0.63fF
+C803 la_data_out[76] vdd 0.63fF
+C804 la_data_in[76] vdd 0.63fF
+C805 la_oenb[75] vdd 0.63fF
+C806 la_data_out[75] vdd 0.63fF
+C807 la_data_in[75] vdd 0.63fF
+C808 la_oenb[74] vdd 0.63fF
+C809 la_data_out[74] vdd 0.63fF
+C810 la_data_in[74] vdd 0.63fF
+C811 la_oenb[73] vdd 0.63fF
+C812 la_data_out[73] vdd 0.63fF
+C813 la_data_in[73] vdd 0.63fF
+C814 la_oenb[72] vdd 0.63fF
+C815 la_data_out[72] vdd 0.63fF
+C816 la_data_in[72] vdd 0.63fF
+C817 la_oenb[71] vdd 0.63fF
+C818 la_data_out[71] vdd 0.63fF
+C819 la_data_in[71] vdd 0.63fF
+C820 la_oenb[70] vdd 0.63fF
+C821 la_data_out[70] vdd 0.63fF
+C822 la_data_in[70] vdd 0.63fF
+C823 la_oenb[69] vdd 0.63fF
+C824 la_data_out[69] vdd 0.63fF
+C825 la_data_in[69] vdd 0.63fF
+C826 la_oenb[68] vdd 0.63fF
+C827 la_data_out[68] vdd 0.63fF
+C828 la_data_in[68] vdd 0.63fF
+C829 la_oenb[67] vdd 0.63fF
+C830 la_data_out[67] vdd 0.63fF
+C831 la_data_in[67] vdd 0.63fF
+C832 la_oenb[66] vdd 0.63fF
+C833 la_data_out[66] vdd 0.63fF
+C834 la_data_in[66] vdd 0.63fF
+C835 la_oenb[65] vdd 0.63fF
+C836 la_data_out[65] vdd 0.63fF
+C837 la_data_in[65] vdd 0.63fF
+C838 la_oenb[64] vdd 0.63fF
+C839 la_data_out[64] vdd 0.63fF
+C840 la_data_in[64] vdd 0.63fF
+C841 la_oenb[63] vdd 0.63fF
+C842 la_data_out[63] vdd 0.63fF
+C843 la_data_in[63] vdd 0.63fF
+C844 la_oenb[62] vdd 0.63fF
+C845 la_data_out[62] vdd 0.63fF
+C846 la_data_in[62] vdd 0.63fF
+C847 la_oenb[61] vdd 0.63fF
+C848 la_data_out[61] vdd 0.63fF
+C849 la_data_in[61] vdd 0.63fF
+C850 la_oenb[60] vdd 0.63fF
+C851 la_data_out[60] vdd 0.63fF
+C852 la_data_in[60] vdd 0.63fF
+C853 la_oenb[59] vdd 0.63fF
+C854 la_data_out[59] vdd 0.63fF
+C855 la_data_in[59] vdd 0.63fF
+C856 la_oenb[58] vdd 0.63fF
+C857 la_data_out[58] vdd 0.63fF
+C858 la_data_in[58] vdd 0.63fF
+C859 la_oenb[57] vdd 0.63fF
+C860 la_data_out[57] vdd 0.63fF
+C861 la_data_in[57] vdd 0.63fF
+C862 la_oenb[56] vdd 0.63fF
+C863 la_data_out[56] vdd 0.63fF
+C864 la_data_in[56] vdd 0.63fF
+C865 la_oenb[55] vdd 0.63fF
+C866 la_data_out[55] vdd 0.63fF
+C867 la_data_in[55] vdd 0.63fF
+C868 la_oenb[54] vdd 0.63fF
+C869 la_data_out[54] vdd 0.63fF
+C870 la_data_in[54] vdd 0.63fF
+C871 la_oenb[53] vdd 0.63fF
+C872 la_data_out[53] vdd 0.63fF
+C873 la_data_in[53] vdd 0.63fF
+C874 la_oenb[52] vdd 0.63fF
+C875 la_data_out[52] vdd 0.63fF
+C876 la_data_in[52] vdd 0.63fF
+C877 la_oenb[51] vdd 0.63fF
+C878 la_data_out[51] vdd 0.63fF
+C879 la_data_in[51] vdd 0.63fF
+C880 la_oenb[50] vdd 0.63fF
+C881 la_data_out[50] vdd 0.63fF
+C882 la_data_in[50] vdd 0.63fF
+C883 la_oenb[49] vdd 0.63fF
+C884 la_data_out[49] vdd 0.63fF
+C885 la_data_in[49] vdd 0.63fF
+C886 la_oenb[48] vdd 0.63fF
+C887 la_data_out[48] vdd 0.63fF
+C888 la_data_in[48] vdd 0.63fF
+C889 la_oenb[47] vdd 0.63fF
+C890 la_data_out[47] vdd 0.63fF
+C891 la_data_in[47] vdd 0.63fF
+C892 la_oenb[46] vdd 0.63fF
+C893 la_data_out[46] vdd 0.63fF
+C894 la_data_in[46] vdd 0.63fF
+C895 la_oenb[45] vdd 0.63fF
+C896 la_data_out[45] vdd 0.63fF
+C897 la_data_in[45] vdd 0.63fF
+C898 la_oenb[44] vdd 0.63fF
+C899 la_data_out[44] vdd 0.63fF
+C900 la_data_in[44] vdd 0.63fF
+C901 la_oenb[43] vdd 0.63fF
+C902 la_data_out[43] vdd 0.63fF
+C903 la_data_in[43] vdd 0.63fF
+C904 la_oenb[42] vdd 0.63fF
+C905 la_data_out[42] vdd 0.63fF
+C906 la_data_in[42] vdd 0.63fF
+C907 la_oenb[41] vdd 0.63fF
+C908 la_data_out[41] vdd 0.63fF
+C909 la_data_in[41] vdd 0.63fF
+C910 la_oenb[40] vdd 0.63fF
+C911 la_data_out[40] vdd 0.63fF
+C912 la_data_in[40] vdd 0.63fF
+C913 la_oenb[39] vdd 0.63fF
+C914 la_data_out[39] vdd 0.63fF
+C915 la_data_in[39] vdd 0.63fF
+C916 la_oenb[38] vdd 0.63fF
+C917 la_data_out[38] vdd 0.63fF
+C918 la_data_in[38] vdd 0.63fF
+C919 la_oenb[37] vdd 0.63fF
+C920 la_data_out[37] vdd 0.63fF
+C921 la_data_in[37] vdd 0.63fF
+C922 la_oenb[36] vdd 0.63fF
+C923 la_data_out[36] vdd 0.63fF
+C924 la_data_in[36] vdd 0.63fF
+C925 la_oenb[35] vdd 0.63fF
+C926 la_data_out[35] vdd 0.63fF
+C927 la_data_in[35] vdd 0.63fF
+C928 la_oenb[34] vdd 0.63fF
+C929 la_data_out[34] vdd 0.63fF
+C930 la_data_in[34] vdd 0.63fF
+C931 la_oenb[33] vdd 0.63fF
+C932 la_data_out[33] vdd 0.63fF
+C933 la_data_in[33] vdd 0.63fF
+C934 la_oenb[32] vdd 0.63fF
+C935 la_data_out[32] vdd 0.63fF
+C936 la_data_in[32] vdd 0.63fF
+C937 la_oenb[31] vdd 0.63fF
+C938 la_data_out[31] vdd 0.63fF
+C939 la_data_in[31] vdd 0.63fF
+C940 la_oenb[30] vdd 0.63fF
+C941 la_data_out[30] vdd 0.63fF
+C942 la_data_in[30] vdd 0.63fF
+C943 la_oenb[29] vdd 0.63fF
+C944 la_data_out[29] vdd 0.63fF
+C945 la_data_in[29] vdd 0.63fF
+C946 la_oenb[28] vdd 0.63fF
+C947 la_data_out[28] vdd 0.63fF
+C948 la_data_in[28] vdd 0.63fF
+C949 la_oenb[27] vdd 0.63fF
+C950 la_data_out[27] vdd 0.63fF
+C951 la_data_in[27] vdd 0.63fF
+C952 la_oenb[26] vdd 0.63fF
+C953 la_data_out[26] vdd 0.63fF
+C954 la_data_in[26] vdd 0.63fF
+C955 la_oenb[25] vdd 0.63fF
+C956 la_data_out[25] vdd 0.63fF
+C957 la_data_in[25] vdd 0.63fF
+C958 la_oenb[24] vdd 0.63fF
+C959 la_data_out[24] vdd 0.63fF
+C960 la_data_in[24] vdd 0.63fF
+C961 la_oenb[23] vdd 0.63fF
+C962 la_data_out[23] vdd 0.63fF
+C963 la_data_in[23] vdd 0.63fF
+C964 la_oenb[22] vdd 0.63fF
+C965 la_data_out[22] vdd 0.63fF
+C966 la_data_in[22] vdd 0.63fF
+C967 la_oenb[21] vdd 0.63fF
+C968 la_data_out[21] vdd 0.63fF
+C969 la_data_in[21] vdd 0.63fF
+C970 la_oenb[20] vdd 0.63fF
+C971 la_data_out[20] vdd 0.63fF
+C972 la_data_in[20] vdd 0.63fF
+C973 la_oenb[19] vdd 0.63fF
+C974 la_data_out[19] vdd 0.63fF
+C975 la_data_in[19] vdd 0.63fF
+C976 la_oenb[18] vdd 0.63fF
+C977 la_data_out[18] vdd 0.63fF
+C978 la_data_in[18] vdd 0.63fF
+C979 la_oenb[17] vdd 0.63fF
+C980 la_data_out[17] vdd 0.63fF
+C981 la_data_in[17] vdd 0.63fF
+C982 la_oenb[16] vdd 0.63fF
+C983 la_data_out[16] vdd 0.63fF
+C984 la_data_in[16] vdd 0.63fF
+C985 la_oenb[15] vdd 0.63fF
+C986 la_data_out[15] vdd 0.63fF
+C987 la_data_in[15] vdd 0.63fF
+C988 la_oenb[14] vdd 0.63fF
+C989 la_data_out[14] vdd 0.63fF
+C990 la_data_in[14] vdd 0.63fF
+C991 la_oenb[13] vdd 0.63fF
+C992 la_data_out[13] vdd 0.63fF
+C993 la_data_in[13] vdd 0.63fF
+C994 la_oenb[12] vdd 0.63fF
+C995 la_data_out[12] vdd 0.63fF
+C996 la_data_in[12] vdd 0.63fF
+C997 la_oenb[11] vdd 0.63fF
+C998 la_data_out[11] vdd 0.63fF
+C999 la_data_in[11] vdd 0.63fF
+C1000 la_oenb[10] vdd 0.63fF
+C1001 la_data_out[10] vdd 0.63fF
+C1002 la_data_in[10] vdd 0.63fF
+C1003 la_oenb[9] vdd 0.63fF
+C1004 la_data_out[9] vdd 0.63fF
+C1005 la_data_in[9] vdd 0.63fF
+C1006 la_oenb[8] vdd 0.63fF
+C1007 la_data_out[8] vdd 0.63fF
+C1008 la_data_in[8] vdd 0.63fF
+C1009 la_oenb[7] vdd 0.63fF
+C1010 la_data_out[7] vdd 0.63fF
+C1011 la_data_in[7] vdd 0.63fF
+C1012 la_oenb[6] vdd 0.63fF
+C1013 la_data_out[6] vdd 0.63fF
+C1014 la_data_in[6] vdd 0.63fF
+C1015 la_oenb[5] vdd 0.63fF
+C1016 la_data_out[5] vdd 0.63fF
+C1017 la_data_in[5] vdd 0.63fF
+C1018 la_oenb[4] vdd 0.63fF
+C1019 la_data_out[4] vdd 0.63fF
+C1020 la_data_in[4] vdd 0.63fF
+C1021 la_oenb[3] vdd 0.63fF
+C1022 la_data_out[3] vdd 0.63fF
+C1023 la_data_in[3] vdd 0.63fF
+C1024 la_oenb[2] vdd 0.63fF
+C1025 la_data_out[2] vdd 0.63fF
+C1026 la_data_in[2] vdd 0.63fF
+C1027 la_oenb[1] vdd 0.63fF
+C1028 la_data_out[1] vdd 0.63fF
+C1029 la_data_in[1] vdd 0.63fF
+C1030 la_oenb[0] vdd 0.63fF
+C1031 la_data_out[0] vdd 0.63fF
+C1032 la_data_in[0] vdd 0.63fF
+C1033 wbs_dat_o[31] vdd 0.63fF
+C1034 wbs_dat_i[31] vdd 0.63fF
+C1035 wbs_adr_i[31] vdd 0.63fF
+C1036 wbs_dat_o[30] vdd 0.63fF
+C1037 wbs_dat_i[30] vdd 0.63fF
+C1038 wbs_adr_i[30] vdd 0.63fF
+C1039 wbs_dat_o[29] vdd 0.63fF
+C1040 wbs_dat_i[29] vdd 0.63fF
+C1041 wbs_adr_i[29] vdd 0.63fF
+C1042 wbs_dat_o[28] vdd 0.63fF
+C1043 wbs_dat_i[28] vdd 0.63fF
+C1044 wbs_adr_i[28] vdd 0.63fF
+C1045 wbs_dat_o[27] vdd 0.63fF
+C1046 wbs_dat_i[27] vdd 0.63fF
+C1047 wbs_adr_i[27] vdd 0.63fF
+C1048 wbs_dat_o[26] vdd 0.63fF
+C1049 wbs_dat_i[26] vdd 0.63fF
+C1050 wbs_adr_i[26] vdd 0.63fF
+C1051 wbs_dat_o[25] vdd 0.63fF
+C1052 wbs_dat_i[25] vdd 0.63fF
+C1053 wbs_adr_i[25] vdd 0.63fF
+C1054 wbs_dat_o[24] vdd 0.63fF
+C1055 wbs_dat_i[24] vdd 0.63fF
+C1056 wbs_adr_i[24] vdd 0.63fF
+C1057 wbs_dat_o[23] vdd 0.63fF
+C1058 wbs_dat_i[23] vdd 0.63fF
+C1059 wbs_adr_i[23] vdd 0.63fF
+C1060 wbs_dat_o[22] vdd 0.63fF
+C1061 wbs_dat_i[22] vdd 0.63fF
+C1062 wbs_adr_i[22] vdd 0.63fF
+C1063 wbs_dat_o[21] vdd 0.63fF
+C1064 wbs_dat_i[21] vdd 0.63fF
+C1065 wbs_adr_i[21] vdd 0.63fF
+C1066 wbs_dat_o[20] vdd 0.63fF
+C1067 wbs_dat_i[20] vdd 0.63fF
+C1068 wbs_adr_i[20] vdd 0.63fF
+C1069 wbs_dat_o[19] vdd 0.63fF
+C1070 wbs_dat_i[19] vdd 0.63fF
+C1071 wbs_adr_i[19] vdd 0.63fF
+C1072 wbs_dat_o[18] vdd 0.63fF
+C1073 wbs_dat_i[18] vdd 0.63fF
+C1074 wbs_adr_i[18] vdd 0.63fF
+C1075 wbs_dat_o[17] vdd 0.63fF
+C1076 wbs_dat_i[17] vdd 0.63fF
+C1077 wbs_adr_i[17] vdd 0.63fF
+C1078 wbs_dat_o[16] vdd 0.63fF
+C1079 wbs_dat_i[16] vdd 0.63fF
+C1080 wbs_adr_i[16] vdd 0.63fF
+C1081 wbs_dat_o[15] vdd 0.63fF
+C1082 wbs_dat_i[15] vdd 0.63fF
+C1083 wbs_adr_i[15] vdd 0.63fF
+C1084 wbs_dat_o[14] vdd 0.63fF
+C1085 wbs_dat_i[14] vdd 0.63fF
+C1086 wbs_adr_i[14] vdd 0.63fF
+C1087 wbs_dat_o[13] vdd 0.63fF
+C1088 wbs_dat_i[13] vdd 0.63fF
+C1089 wbs_adr_i[13] vdd 0.63fF
+C1090 wbs_dat_o[12] vdd 0.63fF
+C1091 wbs_dat_i[12] vdd 0.63fF
+C1092 wbs_adr_i[12] vdd 0.63fF
+C1093 wbs_dat_o[11] vdd 0.63fF
+C1094 wbs_dat_i[11] vdd 0.63fF
+C1095 wbs_adr_i[11] vdd 0.63fF
+C1096 wbs_dat_o[10] vdd 0.63fF
+C1097 wbs_dat_i[10] vdd 0.63fF
+C1098 wbs_adr_i[10] vdd 0.63fF
+C1099 wbs_dat_o[9] vdd 0.63fF
+C1100 wbs_dat_i[9] vdd 0.63fF
+C1101 wbs_adr_i[9] vdd 0.63fF
+C1102 wbs_dat_o[8] vdd 0.63fF
+C1103 wbs_dat_i[8] vdd 0.63fF
+C1104 wbs_adr_i[8] vdd 0.63fF
+C1105 wbs_dat_o[7] vdd 0.63fF
+C1106 wbs_dat_i[7] vdd 0.63fF
+C1107 wbs_adr_i[7] vdd 0.63fF
+C1108 wbs_dat_o[6] vdd 0.63fF
+C1109 wbs_dat_i[6] vdd 0.63fF
+C1110 wbs_adr_i[6] vdd 0.63fF
+C1111 wbs_dat_o[5] vdd 0.63fF
+C1112 wbs_dat_i[5] vdd 0.63fF
+C1113 wbs_adr_i[5] vdd 0.63fF
+C1114 wbs_dat_o[4] vdd 0.63fF
+C1115 wbs_dat_i[4] vdd 0.63fF
+C1116 wbs_adr_i[4] vdd 0.63fF
+C1117 wbs_sel_i[3] vdd 0.63fF
+C1118 wbs_dat_o[3] vdd 0.63fF
+C1119 wbs_dat_i[3] vdd 0.63fF
+C1120 wbs_adr_i[3] vdd 0.63fF
+C1121 wbs_sel_i[2] vdd 0.63fF
+C1122 wbs_dat_o[2] vdd 0.63fF
+C1123 wbs_dat_i[2] vdd 0.63fF
+C1124 wbs_adr_i[2] vdd 0.63fF
+C1125 wbs_sel_i[1] vdd 0.63fF
+C1126 wbs_dat_o[1] vdd 0.63fF
+C1127 wbs_dat_i[1] vdd 0.63fF
+C1128 wbs_adr_i[1] vdd 0.63fF
+C1129 wbs_sel_i[0] vdd 0.63fF
+C1130 wbs_dat_o[0] vdd 0.63fF
+C1131 wbs_dat_i[0] vdd 0.63fF
+C1132 wbs_adr_i[0] vdd 0.63fF
+C1133 wbs_we_i vdd 0.63fF
+C1134 wbs_stb_i vdd 0.63fF
+C1135 wbs_cyc_i vdd 0.63fF
+C1136 wbs_ack_o vdd 0.63fF
+C1137 wb_rst_i vdd 0.63fF
+C1138 wb_clk_i vdd 0.63fF
+C1139 divider_0/and_0/Z1 vdd 0.74fF
+C1140 divider_0/and_0/B vdd 2.25fF
+C1141 divider_0/and_0/A vdd 2.19fF
+C1142 divider_0/and_0/out1 vdd 2.93fF
+C1143 divider_0/tspc_2/Z4 vdd 0.86fF
+C1144 divider_0/Out vdd 1.60fF
+C1145 divider_0/tspc_2/Z3 vdd 2.26fF
+C1146 divider_0/tspc_2/Z2 vdd 1.46fF
+C1147 divider_0/tspc_2/Z1 vdd 0.99fF
+C1148 divider_0/nor_0/B vdd 6.33fF
+C1149 divider_0/tspc_2/a_630_n680# vdd 1.14fF **FLOATING
+C1150 divider_0/tspc_1/Z4 vdd 0.86fF
+C1151 divider_0/tspc_1/Q vdd 3.12fF
+C1152 divider_0/tspc_1/Z3 vdd 2.26fF
+C1153 divider_0/tspc_1/Z2 vdd 1.46fF
+C1154 divider_0/tspc_1/Z1 vdd 0.99fF
+C1155 divider_0/nor_1/B vdd 7.05fF
+C1156 divider_0/tspc_1/a_630_n680# vdd 1.15fF **FLOATING
+C1157 divider_0/tspc_0/Z4 vdd 0.86fF
+C1158 divider_0/tspc_0/Q vdd 3.14fF
+C1159 divider_0/tspc_0/Z3 vdd 2.26fF
+C1160 divider_0/tspc_0/Z2 vdd 1.46fF
+C1161 divider_0/tspc_0/Z1 vdd 0.99fF
+C1162 divider_0/nor_1/A vdd 7.04fF
+C1163 divider_0/tspc_0/a_630_n680# vdd 1.15fF **FLOATING
+C1164 divider_0/clk vdd 5.63fF
+C1165 divider_0/prescaler_0/Out vdd 4.59fF
+C1166 divider_0/prescaler_0/nand_1/z1 vdd 0.36fF
+C1167 divider_0/prescaler_0/tspc_2/D vdd 2.64fF
+C1168 divider_0/prescaler_0/tspc_0/Q vdd 3.64fF
+C1169 divider_0/prescaler_0/tspc_1/Q vdd 3.61fF
+C1170 divider_0/prescaler_0/nand_0/z1 vdd 0.36fF
+C1171 divider_0/prescaler_0/tspc_0/D vdd 3.12fF
+C1172 divider_0/and_0/OUT vdd 5.62fF
+C1173 divider_0/prescaler_0/tspc_2/Z4 vdd 0.86fF
+C1174 divider_0/prescaler_0/tspc_2/Z3 vdd 2.26fF
+C1175 divider_0/prescaler_0/tspc_2/Z2 vdd 1.46fF
+C1176 divider_0/prescaler_0/tspc_2/Z1 vdd 0.99fF
+C1177 divider_0/prescaler_0/tspc_2/a_630_n680# vdd 1.16fF **FLOATING
+C1178 divider_0/prescaler_0/tspc_2/a_740_n680# vdd 2.11fF **FLOATING
+C1179 divider_0/prescaler_0/tspc_1/Z4 vdd 0.86fF
+C1180 divider_0/prescaler_0/tspc_1/Z3 vdd 2.26fF
+C1181 divider_0/prescaler_0/tspc_1/Z2 vdd 1.48fF
+C1182 divider_0/prescaler_0/tspc_1/Z1 vdd 0.99fF
+C1183 divider_0/prescaler_0/tspc_1/a_630_n680# vdd 1.14fF **FLOATING
+C1184 divider_0/prescaler_0/m1_2700_2190# vdd 4.22fF **FLOATING
+C1185 divider_0/prescaler_0/tspc_0/Z4 vdd 0.86fF
+C1186 divider_0/prescaler_0/tspc_0/Z3 vdd 2.26fF
+C1187 divider_0/prescaler_0/tspc_0/Z2 vdd 1.46fF
+C1188 divider_0/prescaler_0/tspc_0/Z1 vdd 0.99fF
+C1189 divider_0/prescaler_0/tspc_0/a_630_n680# vdd 1.14fF **FLOATING
+C1190 divider_0/prescaler_0/tspc_0/a_740_n680# vdd 2.11fF **FLOATING
+C1191 divider_0/nor_1/Z1 vdd 1.34fF
+C1192 divider_0/nor_0/Z1 vdd 1.34fF
+C1193 divider_0/mc2 vdd 5.29fF
+C1194 divbuf_7/OUT vdd 363.82fF
+C1195 divbuf_7/OUT5 vdd 350.37fF
+C1196 divbuf_7/OUT4 vdd 133.72fF
+C1197 divbuf_7/OUT3 vdd 34.03fF
+C1198 divbuf_7/OUT2 vdd 8.71fF
+C1199 divbuf_7/IN vdd 0.89fF
+C1200 divbuf_7/a_492_n240# vdd 2.46fF **FLOATING
+C1201 divbuf_6/OUT vdd 363.82fF
+C1202 divbuf_6/OUT5 vdd 350.37fF
+C1203 divbuf_6/OUT4 vdd 133.72fF
+C1204 divbuf_6/OUT3 vdd 34.03fF
+C1205 divbuf_6/OUT2 vdd 8.71fF
+C1206 divbuf_6/IN vdd 0.89fF
+C1207 divbuf_6/a_492_n240# vdd 2.46fF **FLOATING
+C1208 divbuf_5/OUT vdd 363.82fF
+C1209 divbuf_5/OUT5 vdd 350.37fF
+C1210 divbuf_5/OUT4 vdd 133.72fF
+C1211 divbuf_5/OUT3 vdd 34.03fF
+C1212 divbuf_5/OUT2 vdd 8.71fF
+C1213 divbuf_5/IN vdd 0.89fF
+C1214 divbuf_5/a_492_n240# vdd 2.46fF **FLOATING
+C1215 divbuf_4/OUT vdd 363.82fF
+C1216 divbuf_4/OUT5 vdd 350.37fF
+C1217 divbuf_4/OUT4 vdd 133.72fF
+C1218 divbuf_4/OUT3 vdd 34.03fF
+C1219 divbuf_4/OUT2 vdd 8.71fF
+C1220 divbuf_4/IN vdd 0.89fF
+C1221 divbuf_4/a_492_n240# vdd 2.46fF **FLOATING
+C1222 divbuf_3/OUT vdd 363.82fF
+C1223 divbuf_3/OUT5 vdd 350.37fF
+C1224 divbuf_3/OUT4 vdd 133.72fF
+C1225 divbuf_3/OUT3 vdd 34.03fF
+C1226 divbuf_3/OUT2 vdd 8.71fF
+C1227 divbuf_3/IN vdd 0.89fF
+C1228 divbuf_3/a_492_n240# vdd 2.46fF **FLOATING
+C1229 divbuf_2/OUT vdd 363.82fF
+C1230 divbuf_2/OUT5 vdd 350.37fF
+C1231 divbuf_2/OUT4 vdd 133.72fF
+C1232 divbuf_2/OUT3 vdd 34.03fF
+C1233 divbuf_2/OUT2 vdd 8.71fF
+C1234 divbuf_2/IN vdd 0.89fF
+C1235 divbuf_2/a_492_n240# vdd 2.46fF **FLOATING
+C1236 divbuf_1/OUT vdd 363.82fF
+C1237 divbuf_1/OUT5 vdd 350.37fF
+C1238 divbuf_1/OUT4 vdd 133.72fF
+C1239 divbuf_1/OUT3 vdd 34.03fF
+C1240 divbuf_1/OUT2 vdd 8.71fF
+C1241 divbuf_1/IN vdd 0.89fF
+C1242 divbuf_1/a_492_n240# vdd 2.46fF **FLOATING
+C1243 divbuf_0/OUT vdd 363.82fF
+C1244 divbuf_0/OUT5 vdd 350.37fF
+C1245 divbuf_0/OUT4 vdd 133.72fF
+C1246 divbuf_0/OUT3 vdd 34.03fF
+C1247 divbuf_0/OUT2 vdd 8.71fF
+C1248 divbuf_0/IN vdd 0.89fF
+C1249 divbuf_0/a_492_n240# vdd 2.46fF **FLOATING
+C1250 ro_complete_0/cbank_2/v vdd 17.84fF
+C1251 ro_complete_0/cbank_2/switch_5/vin vdd 0.78fF
+C1252 ro_complete_0/cbank_2/switch_4/vin vdd 1.50fF
+C1253 ro_complete_0/cbank_2/switch_2/vin vdd 1.30fF
+C1254 ro_complete_0/cbank_2/switch_3/vin vdd 0.56fF
+C1255 ro_complete_0/cbank_2/switch_1/vin vdd 1.14fF
+C1256 ro_complete_0/cbank_2/switch_0/vin vdd 1.02fF
+C1257 ro_complete_0/cbank_1/v vdd 16.34fF
+C1258 ro_complete_0/cbank_1/switch_5/vin vdd 0.78fF
+C1259 ro_complete_0/a0 vdd 7.88fF
+C1260 ro_complete_0/cbank_1/switch_4/vin vdd 1.50fF
+C1261 ro_complete_0/a1 vdd 5.39fF
+C1262 ro_complete_0/cbank_1/switch_2/vin vdd 1.30fF
+C1263 ro_complete_0/a3 vdd 6.85fF
+C1264 ro_complete_0/cbank_1/switch_3/vin vdd 0.56fF
+C1265 ro_complete_0/a2 vdd 5.48fF
+C1266 ro_complete_0/cbank_1/switch_1/vin vdd 1.14fF
+C1267 ro_complete_0/a4 vdd 5.36fF
+C1268 ro_complete_0/cbank_1/switch_0/vin vdd 1.02fF
+C1269 ro_complete_0/a5 vdd 5.19fF
+C1270 ro_complete_0/cbank_0/v vdd 14.98fF
+C1271 ro_complete_0/cbank_0/switch_5/vin vdd 0.78fF
+C1272 ro_complete_0/cbank_0/switch_4/vin vdd 1.50fF
+C1273 ro_complete_0/cbank_0/switch_2/vin vdd 1.30fF
+C1274 ro_complete_0/cbank_0/switch_3/vin vdd 0.56fF
+C1275 ro_complete_0/cbank_0/switch_1/vin vdd 1.14fF
+C1276 ro_complete_0/cbank_0/switch_0/vin vdd 1.02fF
+C1277 ro_complete_0/ro_var_extend_0/vcont vdd 0.27fF
+C1278 filter_0/v vdd 85.69fF
+C1279 filter_0/a_4216_n5230# vdd 418.47fF **FLOATING
+C1280 filter_0/a_4216_n2998# vdd 1.03fF **FLOATING
+C1281 cp_0/down vdd 1.54fF
+C1282 cp_0/vbias vdd 2.41fF
+C1283 cp_0/out vdd 5.26fF
+C1284 cp_0/upbar vdd 1.50fF
+C1285 cp_0/a_7110_n2840# vdd 0.17fF **FLOATING
+C1286 cp_0/a_3060_n2840# vdd 1.71fF **FLOATING
+C1287 cp_0/a_7110_0# vdd 0.17fF **FLOATING
+C1288 cp_0/a_6370_0# vdd 0.40fF **FLOATING
+C1289 cp_0/a_3060_0# vdd 1.65fF **FLOATING
+C1290 cp_0/a_1710_0# vdd 5.76fF **FLOATING
+C1291 cp_0/a_1710_n2840# vdd 4.89fF **FLOATING
+C1292 cp_0/a_10_n50# vdd 2.96fF **FLOATING
+C1293 pd_0/and_pd_0/Z1 vdd 0.39fF
+C1294 pd_0/and_pd_0/Out1 vdd 2.22fF
+C1295 pd_0/tspc_r_1/z5 vdd 1.10fF
+C1296 pd_0/tspc_r_1/Z4 vdd 1.07fF
+C1297 pd_0/tspc_r_1/Qbar vdd 0.88fF
+C1298 pd_0/tspc_r_1/Z2 vdd 1.22fF
+C1299 pd_0/tspc_r_1/Z1 vdd 0.67fF
+C1300 pd_0/UP vdd 2.21fF
+C1301 pd_0/tspc_r_1/Qbar1 vdd 1.34fF
+C1302 pd_0/tspc_r_1/Z3 vdd 2.12fF
+C1303 pd_0/REF vdd 1.80fF
+C1304 pd_0/tspc_r_0/z5 vdd 1.10fF
+C1305 pd_0/tspc_r_0/Z4 vdd 1.07fF
+C1306 pd_0/R vdd 3.05fF
+C1307 pd_0/tspc_r_0/Qbar vdd 0.79fF
+C1308 pd_0/tspc_r_0/Z2 vdd 1.22fF
+C1309 pd_0/tspc_r_0/Z1 vdd 0.67fF
+C1310 pd_0/DOWN vdd 3.08fF
+C1311 pd_0/tspc_r_0/Qbar1 vdd 1.34fF
+C1312 pd_0/tspc_r_0/Z3 vdd 2.12fF
+C1313 pd_0/DIV vdd 1.82fF
 .ends