diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index dbfd9fe..1fd4ca0 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ
diff --git a/mag/cp_buffered.mag b/mag/cp_buffered.mag
new file mode 100644
index 0000000..f876789
--- /dev/null
+++ b/mag/cp_buffered.mag
@@ -0,0 +1,169 @@
+magic
+tech sky130A
+timestamp 1647806434
+<< locali >>
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+<< metal4 >>
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+rect -339 -776 386 -753
+rect 169 -2019 397 -2008
+rect 157 -2373 397 -2019
+rect 157 -2384 385 -2373
+use cp  cp_0
+timestamp 1640911461
+transform 1 0 415 0 1 1715
+box -415 -1715 4690 2035
+use tapered_buf  tapered_buf_0
+timestamp 1647784636
+transform 1 0 469 0 1 5051
+box -470 -910 43675 400
+use tapered_buf  tapered_buf_1
+timestamp 1647784636
+transform 1 0 447 0 1 -1140
+box -470 -910 43675 400
+use tapered_buf  tapered_buf_2
+timestamp 1647784636
+transform 1 0 447 0 1 -2688
+box -470 -910 43675 400
+<< labels >>
+rlabel space 5 5096 5 5096 1 up
+rlabel space 7 -1106 7 -1106 1 out
+rlabel space -11 -2638 -11 -2638 1 down
+rlabel metal4 -1257 -2167 -1257 -2167 1 gnd!
+rlabel metal5 311 -2207 311 -2207 1 vdd!
+<< end >>
diff --git a/mag/user_analog_project_wrapper.mag b/mag/user_analog_project_wrapper.mag
index da9b179..46acff1 100644
--- a/mag/user_analog_project_wrapper.mag
+++ b/mag/user_analog_project_wrapper.mag
@@ -1,26 +1,6 @@
 magic
 tech sky130A
-timestamp 1647804919
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 << via4 >>
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 rect 27924 170624 28106 170816
 rect 28218 170625 28400 170817
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 rect 244789 130459 244953 130625
 rect 244999 130457 245163 130623
-rect 21320 112673 21476 112825
-rect 21893 112672 22049 112824
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-rect 24694 45538 24818 45662
-rect 24978 45540 25102 45664
-rect 25207 45535 25331 45659
-rect 25464 45533 25588 45657
-rect 25709 45529 25833 45653
 << metal5 >>
 rect 82797 351150 85297 352400
 rect 87947 351150 90447 352400
@@ -9898,7 +8948,7 @@
 rect 159668 349191 161704 351150
 rect 164874 349155 166910 351150
 rect 10000 341000 279000 343000
-rect 28333 331370 29338 341000
+rect 28333 334662 29338 341000
 rect 100337 340994 103311 341000
 rect 140522 340966 144447 341000
 rect 156586 340685 160000 341000
@@ -9906,12 +8956,6 @@
 rect 156557 337000 160000 340685
 rect 156557 333969 159446 337000
 rect 156478 332036 159446 333969
-rect 28333 331218 28429 331370
-rect 28585 331369 29338 331370
-rect 28585 331218 29002 331369
-rect 28333 331217 29002 331218
-rect 29158 331217 29338 331369
-rect 28333 331175 29338 331217
 rect 156419 330649 159446 332036
 rect 157052 328716 159393 330649
 rect 157046 328349 159393 328716
@@ -9950,60 +8994,21 @@
 rect 275123 275847 275442 276989
 rect 9908 275136 275442 275847
 rect 9908 275109 272994 275136
-rect 9908 274976 260234 275109
-rect 9908 274941 256191 274976
+rect 9908 274978 260234 275109
+rect 9908 274941 17520 274978
+rect 29189 274976 260234 274978
 rect 9908 274937 14729 274941
-rect 17925 274937 256191 274941
-rect 22523 267082 24124 274937
+rect 29189 274937 256191 274976
+rect 13656 268363 14065 274937
 rect 157010 274691 159444 274937
 rect 156732 274199 159444 274691
 rect 156703 270788 159444 274199
 rect 156703 267483 159592 270788
-rect 22903 266651 23075 267082
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-rect 23582 266522 23603 266657
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-rect 23424 266499 23603 266522
+rect 229206 268940 231073 274937
 rect 156624 265550 159592 267483
 rect 156565 264154 159592 265550
 rect 156732 263700 159592 264154
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-rect 231052 265992 231073 266139
-rect 229206 263775 231073 265992
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 rect 156732 259137 159444 263700
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-rect 230325 263625 230645 263628
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-rect 231035 263624 231073 263771
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 rect 156673 258648 159444 259137
 rect 156673 257821 159440 258648
 rect 157052 256386 159440 257821
@@ -10017,7 +9022,8 @@
 rect 9000 243072 274000 245000
 rect 9000 243000 226843 243072
 rect 234785 243000 239793 243072
-rect 26157 241019 27614 243000
+rect 16926 232636 17233 243000
+rect 26157 242165 27614 243000
 rect 122960 242990 130971 243000
 rect 156655 241296 159623 243000
 rect 242462 242271 243000 243072
@@ -10031,29 +9037,9 @@
 rect 242462 241821 242651 241939
 rect 242786 241821 243000 241939
 rect 242462 241804 243000 241821
-rect 26157 241014 27403 241019
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 rect 156596 239900 159623 241296
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 rect 156763 239446 159623 239900
 rect 156763 234883 159475 239446
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-rect 26157 233383 27614 233785
 rect 156704 234394 159475 234883
 rect 156704 233567 159471 234394
 rect 157052 233402 159471 233567
@@ -10061,16 +9047,7 @@
 rect 156887 230093 159393 230638
 rect 156887 229679 159394 230093
 rect 156858 227000 159445 229679
-rect 10000 225511 275000 227000
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-rect 10000 225326 275000 225389
-rect 10000 225204 36610 225326
-rect 36729 225204 275000 225326
-rect 10000 225144 275000 225204
-rect 10000 225022 36608 225144
-rect 36727 225022 275000 225144
-rect 10000 225000 275000 225022
+rect 69559 225000 275000 227000
 rect 157052 224776 159393 225000
 rect 156867 223817 159393 224776
 rect 156838 221025 159425 223817
@@ -10085,36 +9062,11 @@
 rect 156848 194275 159393 196692
 rect 156848 193861 159401 194275
 rect 156848 193531 159452 193861
-rect 27342 187275 28458 187920
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-rect 27342 187141 27936 187145
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 rect 156865 187145 159452 193531
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 rect 156786 185212 159452 187145
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 rect 156727 184950 159452 185212
 rect 156727 183816 159393 184950
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-rect 27894 180039 27959 180169
-rect 28130 180039 28209 180169
-rect 28380 180039 28458 180169
-rect 27342 177000 28458 180039
+rect 27342 177000 28458 178904
 rect 156894 178799 159393 183816
 rect 156835 177000 159393 178799
 rect 12000 175016 277000 177000
@@ -10141,38 +9093,10 @@
 rect 157052 147977 160181 150733
 rect 157052 145259 159393 147977
 rect 157052 142503 160110 145259
-rect 232121 143586 234728 144087
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-rect 232121 143377 233504 143583
-rect 233720 143377 233803 143583
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-rect 234352 143583 234728 143586
-rect 234352 143380 234419 143583
-rect 234019 143377 234419 143380
-rect 234635 143377 234728 143583
 rect 157052 139147 159393 142503
-rect 232121 141204 234728 143377
-rect 232121 140998 233595 141204
-rect 233811 141201 234728 141204
-rect 233811 141198 234187 141201
-rect 233811 140998 233915 141198
-rect 232121 140992 233915 140998
-rect 234131 140995 234187 141198
-rect 234403 141198 234728 141201
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-rect 234131 140992 234462 140995
-rect 234678 140992 234728 141198
 rect 157052 136391 160252 139147
-rect 232121 138747 234728 140992
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-rect 234651 138541 234728 138747
-rect 234070 138538 234728 138541
 rect 157052 135000 159393 136391
-rect 232121 135000 234728 138538
+rect 232121 135000 234728 137469
 rect 11000 133000 276000 135000
 rect 21168 115242 22352 133000
 rect 157052 131451 159393 133000
@@ -10188,13 +9112,7 @@
 rect 157052 120197 159393 128188
 rect 157052 116893 159559 120197
 rect 157052 116868 159557 116893
-rect 21224 112825 22229 115242
-rect 21224 112673 21320 112825
-rect 21476 112824 22229 112825
-rect 21476 112673 21893 112824
-rect 21224 112672 21893 112673
-rect 22049 112672 22229 112824
-rect 21224 112630 22229 112672
+rect 21224 113980 22229 115242
 rect 157052 112245 159393 116868
 rect 157052 108941 159764 112245
 rect 157052 108916 159762 108941
@@ -10224,28 +9142,8 @@
 rect 156720 50746 159393 51797
 rect 157052 50000 159393 50746
 rect 11000 48000 176227 50000
-rect 22603 45664 25872 48000
+rect 22603 46554 25872 48000
 rect 157052 45727 159393 48000
-rect 22603 45662 24978 45664
-rect 22603 45659 24694 45662
-rect 22603 45655 24430 45659
-rect 22603 45531 24178 45655
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-rect 25102 45659 25872 45664
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-rect 24818 45538 25207 45540
-rect 24554 45535 25207 45538
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-rect 25588 45653 25872 45657
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-rect 24302 45531 25709 45533
-rect 22603 45529 25709 45531
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-rect 22603 44698 25872 45529
 rect 157036 45476 159393 45727
 rect 156491 43939 159705 45476
 rect 156432 43049 159705 43939
@@ -10266,50 +9164,50 @@
 rect -50 0 0 352000
 rect 292000 0 292050 352000
 rect -50 -50 292050 0
+use pll_full  pll_full_0
+timestamp 1647806646
+transform 1 0 24183 0 1 99593
+box -5794 -555 13278 10840
 use filter  filter_1
 timestamp 1640983258
 transform 1 0 38025 0 1 41313
 box -1800 -11005 6240 390
-use pll_full  pll_full_0
-timestamp 1647804907
-transform 1 0 24183 0 1 99593
-box -5794 -555 13278 10840
-use divider  divider_0
-timestamp 1647769399
-transform 1 0 246803 0 1 129340
-box -490 -235 4690 2150
 use pd  pd_5
-timestamp 1647804907
+timestamp 1647806551
 transform 1 0 38673 0 1 170517
 box -215 -855 1685 810
 use divider  divider_3
 timestamp 1647769399
 transform 1 0 31863 0 1 169542
 box -490 -235 4690 2150
-use pd  pd_4
-timestamp 1647804907
-transform 1 0 36668 0 1 222858
-box -215 -855 1685 810
+use divider  divider_0
+timestamp 1647769399
+transform 1 0 246803 0 1 129340
+box -490 -235 4690 2150
 use ro_complete  ro_complete_0
-timestamp 1647804907
+timestamp 1647806551
 transform 1 0 242309 0 1 239846
 box -348 -5690 4661 1440
 use divider  divider_1
 timestamp 1647769399
 transform 1 0 250269 0 1 235475
 box -490 -235 4690 2150
-use cp  cp_0
-timestamp 1640911461
-transform 1 0 21911 0 1 264642
-box -415 -1715 4690 2035
 use pll_full  pll_full_1
-timestamp 1647804907
+timestamp 1647806646
 transform 1 0 31292 0 1 318138
 box -5794 -555 13278 10840
 use ro_complete_buffered  ro_complete_buffered_0
-timestamp 1647804714
+timestamp 1647806646
 transform 1 0 237047 0 1 315756
 box -2962 -10858 43775 10271
+use pd_buffered  pd_buffered_0
+timestamp 1647806646
+transform 1 0 16753 0 1 228360
+box -947 -3144 44148 4358
+use cp_buffered  cp_buffered_0
+timestamp 1647806434
+transform 1 0 13561 0 1 262981
+box -1398 -3598 44144 5451
 << labels >>
 flabel metal3 s 291760 134615 292400 134671 0 FreeSans 560 0 0 0 gpio_analog[0]
 port 0 nsew signal bidirectional
diff --git a/netgen/user_analog_project_wrapper.spice b/netgen/user_analog_project_wrapper.spice
index 95a13aa..dea611d 100644
--- a/netgen/user_analog_project_wrapper.spice
+++ b/netgen/user_analog_project_wrapper.spice
@@ -106,1761 +106,1884 @@
 + wbs_dat_o[30] wbs_dat_o[31] wbs_dat_o[3] wbs_dat_o[4] wbs_dat_o[5] wbs_dat_o[6]
 + wbs_dat_o[7] wbs_dat_o[8] wbs_dat_o[9] wbs_sel_i[0] wbs_sel_i[1] wbs_sel_i[2] wbs_sel_i[3]
 + wbs_stb_i wbs_we_i
-C0 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_580_0# 0.35fF
-C1 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
-C2 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C3 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C4 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C5 pd_1/tspc_r_0/Z2 pd_1/R 0.21fF
-C6 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
-C7 pd_0/DIV pd_0/tspc_r_1/Z1 0.17fF
-C8 pd_0/tspc_r_1/Qbar1 pd_0/DOWN 0.11fF
-C9 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF
-C10 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C11 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/vco 1.46fF
-C12 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C13 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C14 io_clamp_low[2] io_analog[6] 0.53fF
-C15 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/div 0.02fF
-C16 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/div 0.04fF
-C17 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF
-C18 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/vco 0.29fF
-C19 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF
-C20 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF
-C21 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF
-C22 ro_complete_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_3/a_n10_230# 0.02fF
-C23 ro_complete_buffered_0/tapered_buf_3/a_160_230# ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.17fF
-C24 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
-C25 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C26 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C27 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/ro_complete_0/a3 26.29fF
-C28 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_0/a_630_n680# 0.01fF
-C29 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C30 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_2/D 0.16fF
-C31 pll_full_1/ro_complete_0/cbank_1/switch_2/vin pll_full_1/vco 1.46fF
-C32 ro_complete_buffered_0/tapered_buf_1/a_n10_230# ro_complete_buffered_0/tapered_buf_1/a_160_230# 0.09fF
-C33 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
-C34 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF
-C35 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF
-C36 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
-C37 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C38 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF
-C39 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C40 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/vco 1.27fF
-C41 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF
-C42 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/a_630_n680# 0.01fF
-C43 pll_full_1/divider_0/nor_0/Z1 pll_full_1/divider_0/nor_1/B 0.18fF
-C44 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
-C45 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF
-C46 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF
-C47 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF
-C48 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C49 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C50 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_1650_0# 2.89fF
-C51 ro_complete_buffered_0/tapered_buf_1/a_160_230# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.17fF
-C52 pll_full_1/pd_0/tspc_r_1/Qbar pll_full_1/pd_0/DOWN 0.21fF
-C53 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF
-C54 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF
-C55 pd_1/tspc_r_1/Qbar1 pd_1/DOWN 0.11fF
-C56 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF
-C57 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
-C58 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF
-C59 ro_complete_buffered_0/tapered_buf_2/a_580_0# ro_complete_buffered_0/tapered_buf_2/a_160_n140# 0.35fF
-C60 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF
-C61 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF
-C62 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF
-C63 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF
-C64 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF
-C65 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF
-C66 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF
-C67 divider_1/and_0/B divider_1/and_0/Z1 0.07fF
-C68 ro_complete_buffered_0/tapered_buf_4/a_580_0# ro_complete_buffered_0/tapered_buf_4/a_1650_0# 1.27fF
-C69 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_1/Z3 0.16fF
-C70 pll_full_1/ro_complete_0/cbank_2/switch_2/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
-C71 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF
-C72 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF
-C73 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF
-C74 pll_full_1/divider_0/prescaler_0/tspc_2/Q pll_full_1/divider_0/prescaler_0/nand_1/z1 0.01fF
-C75 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/vco 0.11fF
-C76 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF
-C77 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
-C78 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
-C79 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
-C80 pll_full_1/pd_0/tspc_r_1/Z2 pll_full_1/pd_0/tspc_r_1/Z1 0.71fF
-C81 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF
-C82 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/Z2 0.36fF
-C83 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C84 pd_0/tspc_r_0/Z3 pd_0/R 0.29fF
-C85 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF
-C86 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/tspc_0/Q 0.15fF
-C87 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
-C88 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
-C89 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C90 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
-C91 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/a1 0.14fF
-C92 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF
-C93 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF
-C94 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF
-C95 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C96 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF
-C97 pll_full_1/divider_0/nor_0/Z1 pll_full_1/divider_0/and_0/B 0.78fF
-C98 pll_full_1/divider_0/tspc_2/Z3 pll_full_1/divider_0/tspc_2/Z4 0.65fF
-C99 pll_full_1/pd_0/DOWN pll_full_1/pd_0/and_pd_0/Out1 0.12fF
-C100 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C101 divider_2/nor_1/B divider_2/tspc_0/Q 0.22fF
-C102 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF
-C103 pd_1/tspc_r_0/z5 pd_1/tspc_r_1/z5 0.02fF
-C104 pll_full_1/pd_0/tspc_r_0/z5 pll_full_1/ref 0.04fF
-C105 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF
-C106 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/vco 0.11fF
-C107 filter_0/v filter_0/a_4216_n2998# 0.36fF
-C108 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF
-C109 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
-C110 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
-C111 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF
-C112 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF
-C113 divider_0/and_0/A divider_0/and_0/B 0.18fF
-C114 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
-C115 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C116 pll_full_1/ro_complete_0/a5 pll_full_1/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C117 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF
-C118 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF
-C119 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF
-C120 ro_complete_buffered_0/tapered_buf_5/a_n10_n140# ro_complete_buffered_0/tapered_buf_5/in 0.04fF
-C121 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF
-C122 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C123 ro_complete_buffered_0/tapered_buf_0/a_160_n140# ro_complete_buffered_0/tapered_buf_0/a_580_0# 0.35fF
-C124 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF
-C125 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C126 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF
-C127 pd_1/tspc_r_1/Qbar pd_1/DOWN 0.21fF
-C128 pd_1/R pd_1/tspc_r_1/Qbar1 0.01fF
-C129 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF
-C130 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C131 divider_1/tspc_1/Z3 divider_1/tspc_1/a_630_n680# 0.05fF
-C132 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF
-C133 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF
-C134 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C135 pll_full_1/ro_complete_0/a1 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
-C136 ro_complete_buffered_0/tapered_buf_6/a_4670_0# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 29.21fF
-C137 ro_complete_buffered_0/tapered_buf_6/a_n10_230# ro_complete_buffered_0/tapered_buf_6/a_160_230# 0.09fF
-C138 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF
-C139 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/DOWN 0.07fF
-C140 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF
-C141 ro_complete_buffered_0/tapered_buf_1/a_1650_0# ro_complete_buffered_0/tapered_buf_1/a_4670_0# 4.78fF
-C142 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C143 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
-C144 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF
-C145 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C146 divider_2/mc2 divider_2/nor_0/B 0.15fF
-C147 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF
-C148 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF
-C149 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF
-C150 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
-C151 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/vco 0.01fF
-C152 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C153 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.09fF
-C154 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF
-C155 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z4 0.12fF
-C156 divider_2/tspc_0/Z3 divider_2/nor_1/A 0.38fF
-C157 ro_complete_buffered_0/tapered_buf_7/a_580_0# ro_complete_buffered_0/tapered_buf_7/a_1650_0# 1.27fF
-C158 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/R 0.27fF
-C159 divider_2/nor_0/B divider_2/and_0/B 0.29fF
-C160 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/and_0/B 0.01fF
-C161 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
-C162 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C163 pd_1/tspc_r_0/Z1 pd_1/REF 0.17fF
-C164 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
-C165 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
-C166 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
-C167 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF
-C168 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C169 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF
-C170 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF
-C171 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF
-C172 pll_full_1/filter_0/a_4216_n5230# pll_full_1/vco 1.58fF
-C173 pll_full_0/divider_0/nor_0/B pll_full_0/div 0.27fF
-C174 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF
-C175 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.05fF
-C176 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_580_0# 0.84fF
-C177 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C178 pll_full_1/ro_complete_0/cbank_0/switch_4/vin pll_full_1/ro_complete_0/a0 0.13fF
-C179 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF
-C180 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/nand_0/z1 0.07fF
-C181 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C182 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF
-C183 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF
-C184 divider_1/nor_1/B divider_1/tspc_1/a_630_n680# 0.35fF
-C185 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C186 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C187 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C188 cp_0/a_1710_n2840# cp_0/upbar 0.29fF
-C189 pd_0/DOWN pd_0/UP 0.46fF
-C190 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
-C191 pll_full_1/pd_0/and_pd_0/Out1 pll_full_1/pd_0/UP 0.33fF
-C192 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF
-C193 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF
-C194 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C195 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C196 divider_1/tspc_0/Z2 divider_1/nor_1/A 0.23fF
-C197 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
-C198 divider_1/mc2 divider_1/and_0/B 0.20fF
-C199 ro_complete_buffered_0/tapered_buf_2/a_n10_n140# ro_complete_buffered_0/tapered_buf_2/in 0.04fF
-C200 ro_complete_buffered_0/tapered_buf_2/a_160_230# ro_complete_buffered_0/tapered_buf_2/a_580_0# 0.02fF
-C201 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
-C202 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/Z4 0.12fF
-C203 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C204 divider_1/nor_1/B divider_1/mc2 0.06fF
-C205 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_0/Q 0.14fF
-C206 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/vco 0.01fF
-C207 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF
-C208 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF
-C209 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF
-C210 divider_0/mc2 divider_0/and_0/out1 0.06fF
-C211 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_4670_0# 29.21fF
-C212 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z2 0.14fF
-C213 pd_0/REF pd_0/tspc_r_0/Qbar1 0.12fF
-C214 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C215 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C216 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/DOWN 0.03fF
-C217 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
-C218 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
-C219 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF
-C220 divider_2/tspc_0/Z2 divider_2/prescaler_0/Out 0.11fF
-C221 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF
-C222 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C223 ro_complete_buffered_0/tapered_buf_4/a_1650_0# ro_complete_buffered_0/tapered_buf_4/a_4670_0# 4.78fF
-C224 pll_full_1/ro_complete_0/cbank_2/switch_4/vin pll_full_1/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C225 pll_full_1/divider_0/and_0/OUT pll_full_1/div 0.01fF
-C226 pll_full_1/divider_0/prescaler_0/tspc_0/D pll_full_1/divider_0/prescaler_0/nand_1/z1 0.21fF
-C227 divider_2/nor_0/B divider_2/Out 0.22fF
-C228 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF
-C229 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
-C230 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C231 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/UP 0.06fF
-C232 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C233 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/nor_1/B 1.21fF
-C234 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
-C235 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
-C236 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF
-C237 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C238 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C239 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
-C240 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF
-C241 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF
-C242 divider_2/nor_1/A divider_2/tspc_0/Z4 0.21fF
-C243 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF
-C244 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF
-C245 pll_full_1/ro_complete_0/cbank_1/switch_1/vin pll_full_1/vco 1.46fF
-C246 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/a_n10_230# 0.02fF
-C247 ro_complete_buffered_0/tapered_buf_0/a_160_230# ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.17fF
-C248 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
-C249 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C250 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
-C251 pd_0/tspc_r_0/Qbar pd_0/UP 0.21fF
-C252 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Z2 0.25fF
-C253 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF
-C254 pll_full_0/divider_0/prescaler_0/Out pll_full_0/vco 0.51fF
-C255 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
-C256 divider_1/tspc_0/Q divider_1/tspc_1/Z4 0.15fF
-C257 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF
-C258 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF
-C259 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF
-C260 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF
-C261 pll_full_1/ro_complete_0/cbank_2/switch_1/vin pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C262 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF
-C263 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C264 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C265 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF
-C266 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C267 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
-C268 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/vco 0.12fF
-C269 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF
-C270 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/tapered_buf_2/a_160_n140# 0.22fF
-C271 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
-C272 ro_complete_0/a2 ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C273 divider_2/tspc_0/Q divider_2/tspc_1/a_630_n680# 0.01fF
-C274 divider_1/and_0/out1 divider_1/and_0/B 0.18fF
-C275 ro_complete_buffered_0/tapered_buf_6/a_n10_230# ro_complete_buffered_0/tapered_buf_6/a_n10_n140# 0.01fF
-C276 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
-C277 ro_complete_buffered_0/tapered_buf_1/a_580_0# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.35fF
-C278 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z3 0.09fF
-C279 pll_full_1/pd_0/DOWN pll_full_1/pd_0/tspc_r_0/Qbar 0.02fF
-C280 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF
-C281 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/pd_0/R 0.30fF
-C282 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF
-C283 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
-C284 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
-C285 divider_1/mc2 divider_1/nor_1/A 0.04fF
-C286 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C287 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF
-C288 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF
-C289 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C290 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Z1 0.09fF
-C291 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF
-C292 divider_2/prescaler_0/Out divider_2/clk 0.51fF
-C293 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_1/a_630_n680# 0.05fF
-C294 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/nor_1/B 0.03fF
-C295 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C296 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C297 ro_complete_buffered_0/tapered_buf_7/a_1650_0# ro_complete_buffered_0/tapered_buf_7/a_4670_0# 4.78fF
-C298 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_160_230# 0.17fF
-C299 io_clamp_low[2] io_clamp_high[2] 0.53fF
-C300 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C301 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C302 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
-C303 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C304 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF
-C305 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z1 0.06fF
-C306 pd_0/tspc_r_0/Qbar pd_0/and_pd_0/Out1 0.05fF
-C307 pd_0/tspc_r_1/Z3 pd_0/R 0.27fF
-C308 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
-C309 io_clamp_high[1] io_analog[5] 0.53fF
-C310 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Z1 0.09fF
-C311 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF
-C312 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF
-C313 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
-C314 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
-C315 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF
-C316 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C317 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF
-C318 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF
-C319 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C320 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 0.22fF
-C321 ro_complete_buffered_0/tapered_buf_5/a_580_0# ro_complete_buffered_0/tapered_buf_5/a_160_230# 0.02fF
-C322 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/ro_complete_0/a2 26.29fF
-C323 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/and_0/OUT 0.06fF
-C324 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C325 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.11fF
-C326 pll_full_1/ro_complete_0/cbank_1/switch_4/vin pll_full_1/vco 1.46fF
-C327 pll_full_1/divider_0/and_0/out1 pll_full_1/divider_0/and_0/A 0.01fF
-C328 pll_full_1/divider_0/tspc_0/Z3 pll_full_1/divider_0/tspc_0/Q 0.05fF
-C329 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
-C330 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C331 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF
-C332 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
-C333 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C334 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C335 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C336 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/vco 0.01fF
-C337 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C338 pll_full_1/ro_complete_0/a5 pll_full_1/ro_complete_0/cbank_2/v 0.08fF
-C339 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C340 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF
-C341 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF
-C342 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/vco 0.01fF
-C343 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/ro_complete_0/a4 26.29fF
-C344 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C345 divider_1/tspc_0/Z1 divider_1/nor_1/A 0.03fF
-C346 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C347 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF
-C348 pd_1/DIV pd_1/tspc_r_1/Z4 0.02fF
-C349 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/vco 1.36fF
-C350 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
-C351 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C352 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF
-C353 pll_full_1/ro_complete_0/cbank_2/switch_4/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
-C354 divider_2/tspc_0/Z1 divider_2/nor_1/A 0.03fF
-C355 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF
-C356 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
-C357 pll_full_1/pd_0/tspc_r_0/Z4 pll_full_1/ref 0.02fF
-C358 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
-C359 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C360 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C361 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF
-C362 divider_2/mc2 divider_2/and_0/B 0.20fF
-C363 divider_1/mc2 divider_1/and_0/OUT 0.05fF
-C364 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF
-C365 pll_full_1/pd_0/tspc_r_0/Qbar pll_full_1/pd_0/UP 0.21fF
-C366 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
-C367 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF
-C368 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF
-C369 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF
-C370 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF
-C371 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_1/Z4 0.36fF
-C372 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_1/Q 0.05fF
-C373 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/tspc_r_1/Qbar 0.01fF
-C374 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF
-C375 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF
-C376 divider_0/mc2 divider_0/nor_1/A 0.04fF
-C377 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C378 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C379 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
-C380 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.05fF
-C381 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_580_0# 0.84fF
-C382 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C383 divider_2/nor_1/B divider_2/nor_0/Z1 0.18fF
-C384 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF
-C385 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C386 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C387 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
-C388 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/vco 1.46fF
-C389 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
-C390 ro_complete_buffered_0/tapered_buf_2/a_n10_230# ro_complete_buffered_0/tapered_buf_2/a_n10_n140# 0.01fF
-C391 divider_1/nor_1/B divider_1/tspc_0/a_630_n680# 0.01fF
-C392 ro_complete_buffered_0/tapered_buf_3/a_1650_0# ro_complete_buffered_0/tapered_buf_3/a_580_0# 1.27fF
-C393 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C394 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
-C395 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C396 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF
-C397 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF
-C398 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF
-C399 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF
-C400 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF
-C401 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF
-C402 divider_0/mc2 divider_0/nor_0/B 0.15fF
-C403 ro_complete_buffered_0/tapered_buf_1/a_n10_n140# ro_complete_buffered_0/tapered_buf_1/in 0.04fF
-C404 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C405 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C406 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF
-C407 divider_1/prescaler_0/Out divider_1/tspc_0/Z2 0.11fF
-C408 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C409 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C410 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF
-C411 ro_complete_0/a2 ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C412 pll_full_1/ro_complete_0/cbank_0/v pll_full_1/ro_complete_0/cbank_2/v 0.04fF
-C413 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF
-C414 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/tspc_0/Q 0.01fF
-C415 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF
-C416 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C417 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C418 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF
-C419 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C420 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF
-C421 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
-C422 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C423 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
-C424 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
-C425 pd_1/DOWN pd_1/and_pd_0/Z1 0.07fF
-C426 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
-C427 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/vco 0.11fF
-C428 pll_full_1/ro_complete_0/cbank_1/switch_3/vin pll_full_1/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C429 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/nor_1/B 0.38fF
-C430 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/Z1 0.00fF
-C431 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C432 pll_full_1/ro_complete_0/a2 pll_full_1/vco 0.11fF
-C433 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_n10_n140# 0.05fF
-C434 ro_complete_buffered_0/tapered_buf_7/a_580_0# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 0.84fF
-C435 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/tspc_2/Z3 0.05fF
-C436 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z1 0.03fF
-C437 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
-C438 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF
-C439 pd_0/DOWN pd_0/R 0.36fF
-C440 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
-C441 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
-C442 pd_0/DIV pd_0/tspc_r_1/z5 0.04fF
-C443 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C444 io_clamp_low[0] io_analog[4] 0.53fF
-C445 divider_2/nor_1/B divider_2/and_0/A 0.26fF
-C446 pd_1/and_pd_0/Z1 pd_1/UP 0.06fF
-C447 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF
-C448 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF
-C449 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF
-C450 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
-C451 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C452 divider_0/prescaler_0/Out divider_0/tspc_0/a_630_n680# 0.01fF
-C453 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF
-C454 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/in 0.19fF
-C455 ro_complete_buffered_0/tapered_buf_5/a_1650_0# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 2.89fF
-C456 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C457 pll_full_1/ro_complete_0/cbank_1/switch_0/vin pll_full_1/vco 1.58fF
-C458 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar1 0.11fF
-C459 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF
-C460 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C461 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C462 pd_1/R pd_1/REF 0.61fF
-C463 pd_1/tspc_r_0/z5 pd_1/UP 0.03fF
-C464 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C465 divider_2/mc2 divider_2/nor_1/A 0.04fF
-C466 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF
-C467 divider_1/tspc_0/Z3 divider_1/nor_1/A 0.38fF
-C468 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C469 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.02fF
-C470 divider_2/tspc_0/Q divider_2/tspc_0/Z3 0.05fF
-C471 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF
-C472 divider_1/nor_0/B divider_1/and_0/B 0.29fF
-C473 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/Z3 0.65fF
-C474 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/prescaler_0/tspc_2/D 0.03fF
-C475 divider_2/nor_1/A divider_2/and_0/B 0.08fF
-C476 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF
-C477 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF
-C478 divider_1/nor_1/B divider_1/nor_0/B 0.47fF
-C479 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C480 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.22fF
-C481 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
-C482 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C483 pd_0/REF pd_0/tspc_r_0/Z2 0.19fF
-C484 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
-C485 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
-C486 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C487 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/div 0.17fF
-C488 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF
-C489 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
-C490 pd_1/R pd_1/and_pd_0/Z1 0.02fF
-C491 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/z5 0.11fF
-C492 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF
-C493 divider_0/nor_1/A divider_0/tspc_0/Z1 0.03fF
-C494 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
-C495 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF
-C496 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF
-C497 divider_2/tspc_0/a_630_n680# divider_2/nor_1/A 0.35fF
-C498 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C499 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C500 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 0.22fF
-C501 ro_complete_buffered_0/tapered_buf_4/a_580_0# ro_complete_buffered_0/tapered_buf_4/a_160_230# 0.02fF
-C502 pll_full_1/ro_complete_0/cbank_2/switch_0/vin pll_full_1/ro_complete_0/cbank_2/v 1.45fF
-C503 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF
-C504 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF
-C505 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
-C506 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C507 pd_0/tspc_r_0/Qbar pd_0/R 0.03fF
-C508 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
-C509 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
-C510 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
-C511 pd_1/and_pd_0/Out1 pd_1/and_pd_0/Z1 0.18fF
-C512 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF
-C513 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF
-C514 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF
-C515 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF
-C516 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF
-C517 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C518 pll_full_1/ro_complete_0/cbank_0/switch_2/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
-C519 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C520 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF
-C521 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C522 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/Z2 0.36fF
-C523 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF
-C524 pll_full_1/div pll_full_1/vco 2.26fF
-C525 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/pd_0/tspc_r_1/Z2 0.14fF
-C526 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_6/in 0.10fF
-C527 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
-C528 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF
-C529 pll_full_0/pd_0/R pll_full_0/div 0.51fF
-C530 pd_0/tspc_r_0/z5 pd_0/UP 0.03fF
-C531 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
-C532 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C533 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
-C534 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C535 ro_complete_buffered_0/tapered_buf_2/a_n10_230# ro_complete_buffered_0/tapered_buf_2/in 0.02fF
-C536 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF
-C537 divider_1/nor_0/B divider_1/Out 0.22fF
-C538 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF
-C539 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF
-C540 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Q 0.55fF
-C541 pll_full_1/ro_complete_0/cbank_1/switch_5/vin pll_full_1/vco 1.46fF
-C542 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF
-C543 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF
-C544 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z4 0.12fF
-C545 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C546 pd_1/tspc_r_0/Z3 pd_1/UP 0.03fF
-C547 pd_0/and_pd_0/Z1 pd_0/UP 0.06fF
-C548 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_0/Q 0.14fF
-C549 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/vco 0.01fF
-C550 divider_2/mc2 divider_2/and_0/OUT 0.05fF
-C551 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
-C552 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
-C553 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C554 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
-C555 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
-C556 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF
-C557 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF
-C558 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF
-C559 divider_1/nor_1/A divider_1/tspc_0/Z4 0.21fF
-C560 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF
-C561 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF
-C562 divider_2/and_0/OUT divider_2/and_0/B 0.01fF
-C563 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z1 0.01fF
-C564 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_0/Q 0.22fF
-C565 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
-C566 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C567 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
-C568 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C569 pd_1/tspc_r_0/Qbar pd_1/and_pd_0/Z1 0.02fF
-C570 pll_full_0/divider_0/and_0/OUT pll_full_0/div 0.01fF
-C571 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
-C572 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
-C573 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
-C574 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF
-C575 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# ro_complete_buffered_0/tapered_buf_3/in 0.04fF
-C576 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C577 divider_2/tspc_1/Z2 divider_2/tspc_1/a_630_n680# 0.01fF
-C578 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C579 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C580 pll_full_1/divider_0/nor_1/Z1 pll_full_1/divider_0/and_0/A 0.80fF
-C581 pll_full_1/ro_complete_0/cbank_2/switch_5/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
-C582 ro_complete_buffered_0/tapered_buf_7/a_4670_0# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 29.21fF
-C583 ro_complete_buffered_0/tapered_buf_7/a_n10_230# ro_complete_buffered_0/tapered_buf_7/a_160_230# 0.09fF
-C584 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/tspc_2/Z4 0.12fF
-C585 pll_full_1/divider_0/tspc_2/Z1 pll_full_1/divider_0/tspc_2/Z2 1.07fF
-C586 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z3 0.38fF
-C587 io_clamp_low[1] io_clamp_high[1] 0.53fF
-C588 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF
-C589 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
-C590 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C591 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C592 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C593 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C594 pd_1/tspc_r_0/Z3 pd_1/R 0.29fF
-C595 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
-C596 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF
-C597 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/vco 1.46fF
-C598 pll_full_1/pd_0/tspc_r_1/Z2 pll_full_1/div 0.19fF
-C599 divider_1/tspc_0/Q divider_1/tspc_1/a_630_n680# 0.01fF
-C600 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF
-C601 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF
-C602 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
-C603 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C604 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF
-C605 divider_1/nor_1/B divider_1/nor_0/Z1 0.18fF
-C606 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/tspc_1/Z4 0.12fF
-C607 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C608 divider_1/nor_1/B divider_1/tspc_1/Q 0.51fF
-C609 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C610 pll_full_1/divider_0/and_0/out1 pll_full_1/divider_0/and_0/Z1 0.36fF
-C611 ro_complete_buffered_0/tapered_buf_0/a_1650_0# ro_complete_buffered_0/tapered_buf_0/a_580_0# 1.27fF
-C612 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C613 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_6/in 1.27fF
-C614 pll_full_1/pd_0/tspc_r_0/Z4 pll_full_1/pd_0/tspc_r_0/Z2 0.14fF
-C615 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C616 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF
-C617 pd_1/tspc_r_1/Z1 pd_1/DIV 0.17fF
-C618 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
-C619 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/ref 0.12fF
-C620 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C621 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF
-C622 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C623 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C624 divider_2/tspc_0/Q divider_2/tspc_1/Z1 0.01fF
-C625 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF
-C626 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
-C627 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF
-C628 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/prescaler_0/nand_0/z1 0.01fF
-C629 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/vco 0.11fF
-C630 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/pd_0/tspc_r_0/Z4 0.02fF
-C631 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF
-C632 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF
-C633 divider_0/mc2 divider_0/and_0/B 0.20fF
-C634 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C635 ro_complete_buffered_0/tapered_buf_6/a_n10_n140# ro_complete_buffered_0/tapered_buf_6/in 0.04fF
-C636 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
-C637 pd_1/DOWN pd_1/tspc_r_1/z5 0.03fF
-C638 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF
-C639 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF
-C640 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
-C641 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C642 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/in 0.19fF
-C643 ro_complete_buffered_0/tapered_buf_4/a_1650_0# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 2.89fF
-C644 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C645 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/div 0.03fF
-C646 pll_full_1/divider_0/and_0/OUT pll_full_1/vco 0.06fF
-C647 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C648 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_630_n680# 0.12fF
-C649 cp_0/out cp_0/a_1710_n2840# 0.61fF
-C650 pd_1/tspc_r_0/Z4 pd_1/REF 0.02fF
-C651 pd_0/DIV pd_0/tspc_r_1/Qbar1 0.12fF
-C652 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF
-C653 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
-C654 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C655 pll_full_1/pd_0/DOWN pll_full_1/pd_0/UP 4.58fF
-C656 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/div 0.12fF
-C657 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
-C658 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/nor_1/B 0.03fF
-C659 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
-C660 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
-C661 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/UP 0.03fF
-C662 pll_full_0/ref pll_full_0/pd_0/DOWN 1.48fF
-C663 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF
-C664 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF
-C665 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF
-C666 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF
-C667 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_4670_0# 29.21fF
-C668 ro_complete_buffered_0/tapered_buf_3/a_160_230# ro_complete_buffered_0/tapered_buf_3/a_n10_230# 0.09fF
-C669 pll_full_1/ro_complete_0/cbank_0/switch_4/vin pll_full_1/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C670 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/vco 0.64fF
-C671 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
-C672 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF
-C673 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF
-C674 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF
-C675 divider_1/nor_1/B divider_1/tspc_1/Z3 0.38fF
-C676 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C677 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C678 cp_0/vbias cp_0/a_10_n50# 0.19fF
-C679 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/z5 0.11fF
-C680 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF
-C681 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
-C682 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
-C683 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
-C684 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
-C685 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
-C686 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/vco 1.46fF
-C687 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF
-C688 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Q 0.05fF
-C689 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF
-C690 pll_full_1/ro_complete_0/cbank_2/switch_1/vin pll_full_1/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C691 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
-C692 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_740_n680# 0.08fF
-C693 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.15fF
-C694 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/and_0/A 0.01fF
-C695 ro_complete_buffered_0/tapered_buf_1/in gnd 0.04fF
-C696 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C697 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/z5 0.04fF
-C698 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C699 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF
-C700 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C701 pd_1/DIV pd_1/tspc_r_1/Qbar1 0.12fF
-C702 divider_1/prescaler_0/Out divider_1/tspc_0/Z3 0.45fF
-C703 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
-C704 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF
-C705 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
-C706 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/vco 0.01fF
-C707 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF
-C708 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF
-C709 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
-C710 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z4 0.21fF
-C711 ro_complete_buffered_0/tapered_buf_6/a_210_n610# ro_complete_buffered_0/tapered_buf_6/out 26.29fF
-C712 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z3 0.45fF
-C713 pll_full_1/divider_0/tspc_0/a_630_n680# pll_full_1/divider_0/tspc_0/Q 0.04fF
-C714 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/and_0/A 0.26fF
-C715 divider_1/nor_1/B divider_1/and_0/B 0.31fF
-C716 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF
-C717 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
-C718 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C719 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
-C720 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C721 cp_0/a_1710_0# cp_0/a_1710_n2840# 0.83fF
-C722 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
-C723 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C724 cp_0/upbar cp_0/down 0.02fF
-C725 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF
-C726 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
-C727 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
-C728 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF
-C729 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C730 pll_full_1/ro_complete_0/cbank_1/switch_3/vin pll_full_1/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C731 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_1/Z4 0.02fF
-C732 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C733 ro_complete_buffered_0/tapered_buf_7/a_n10_230# ro_complete_buffered_0/tapered_buf_7/a_n10_n140# 0.01fF
-C734 pll_full_1/divider_0/tspc_2/Z2 pll_full_1/divider_0/tspc_2/Z3 0.16fF
-C735 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z4 0.22fF
-C736 divider_2/and_0/out1 divider_2/and_0/A 0.01fF
-C737 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF
-C738 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
-C739 pd_0/tspc_r_0/Qbar1 pd_0/UP 0.11fF
-C740 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF
-C741 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF
-C742 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
-C743 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
-C744 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF
-C745 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C746 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
-C747 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Z4 0.20fF
-C748 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
-C749 ro_complete_buffered_0/tapered_buf_5/a_n10_230# ro_complete_buffered_0/tapered_buf_5/in 0.02fF
-C750 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_1/Z4 0.21fF
-C751 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C752 pll_full_1/ro_complete_0/a0 pll_full_1/vco 0.11fF
-C753 pll_full_1/divider_0/and_0/A pll_full_1/divider_0/and_0/B 0.18fF
-C754 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
-C755 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z3 0.25fF
-C756 pll_full_1/pd_0/tspc_r_0/z5 pll_full_1/pd_0/UP 0.03fF
-C757 divider_0/nor_1/B divider_0/and_0/A 0.26fF
-C758 ro_complete_buffered_0/tapered_buf_2/a_160_230# ro_complete_buffered_0/tapered_buf_2/a_160_n140# 0.17fF
-C759 divider_2/tspc_0/Q divider_2/tspc_1/Z3 0.45fF
-C760 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
-C761 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 0.22fF
-C762 ro_complete_buffered_0/tapered_buf_6/a_580_0# ro_complete_buffered_0/tapered_buf_6/a_160_230# 0.02fF
-C763 pll_full_1/divider_0/prescaler_0/tspc_2/D pll_full_1/divider_0/prescaler_0/nand_0/z1 0.24fF
-C764 divider_0/prescaler_0/Out divider_0/nor_1/A 0.15fF
-C765 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C766 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
-C767 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
-C768 pd_1/tspc_r_0/Z4 pd_1/tspc_r_0/Z3 0.20fF
-C769 pd_0/REF pd_0/tspc_r_0/Z4 0.02fF
-C770 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF
-C771 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.01fF
-C772 divider_1/prescaler_0/Out divider_1/tspc_0/Z4 0.12fF
-C773 divider_0/nor_1/A divider_0/and_0/B 0.08fF
-C774 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
-C775 pll_full_0/cp_0/a_1710_0# pll_full_0/pd_0/DOWN 0.04fF
-C776 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF
-C777 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C778 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/UP 0.03fF
-C779 pll_full_1/divider_0/prescaler_0/tspc_2/D pll_full_1/vco 0.26fF
-C780 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# ro_complete_buffered_0/tapered_buf_0/in 0.04fF
-C781 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C782 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
-C783 pd_0/tspc_r_1/Z3 pd_0/DOWN 0.03fF
-C784 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/nor_1/B 0.38fF
-C785 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF
-C786 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
-C787 pll_full_0/ro_complete_0/a2 pll_full_0/vco 0.11fF
-C788 pll_full_1/ref pll_full_1/pd_0/R 0.61fF
-C789 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF
-C790 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF
-C791 divider_1/tspc_0/Q divider_1/tspc_0/Z3 0.05fF
-C792 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF
-C793 divider_0/nor_0/B divider_0/and_0/B 0.29fF
-C794 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# ro_complete_buffered_0/tapered_buf_3/a_n10_230# 0.01fF
-C795 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C796 pll_full_1/ro_complete_0/a5 pll_full_1/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C797 pll_full_1/ro_complete_0/cbank_0/switch_4/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
-C798 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF
-C799 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF
-C800 divider_1/nor_1/A divider_1/and_0/B 0.08fF
-C801 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF
-C802 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF
-C803 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_580_0# 0.35fF
-C804 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/Z3 0.45fF
-C805 pll_full_1/ro_complete_0/a3 pll_full_1/vco 0.11fF
-C806 divider_1/nor_1/B divider_1/nor_1/A 1.21fF
-C807 divider_0/mc2 divider_0/and_0/OUT 0.05fF
-C808 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Q 0.04fF
-C809 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF
-C810 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/div 0.65fF
-C811 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
-C812 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF
-C813 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
-C814 pd_0/R pd_0/and_pd_0/Z1 0.02fF
-C815 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
-C816 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/vco 1.58fF
-C817 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF
-C818 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
-C819 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C820 divider_2/tspc_0/Q divider_2/tspc_0/a_630_n680# 0.04fF
-C821 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF
-C822 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/z5 0.03fF
-C823 divider_1/nor_1/B divider_1/nor_1/Z1 0.06fF
-C824 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.05fF
-C825 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF
-C826 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C827 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF
-C828 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C829 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.35fF
-C830 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
-C831 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF
-C832 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF
-C833 pd_1/tspc_r_1/Z3 pd_1/DOWN 0.03fF
-C834 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF
-C835 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
-C836 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C837 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF
-C838 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_1/Z3 0.06fF
-C839 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/Z2 0.11fF
-C840 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C841 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/div 0.65fF
-C842 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF
-C843 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF
-C844 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z4 0.15fF
-C845 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/div 0.02fF
-C846 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF
-C847 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
-C848 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
-C849 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C850 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/Z1 0.00fF
-C851 pd_0/REF pd_0/R 0.61fF
-C852 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF
-C853 divider_0/nor_0/B divider_0/Out 0.22fF
-C854 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
-C855 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C856 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/a_630_n680# 0.12fF
-C857 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF
-C858 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF
-C859 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF
-C860 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/pd_0/tspc_r_1/z5 0.04fF
-C861 pll_full_1/divider_0/tspc_2/Z2 pll_full_1/divider_0/tspc_2/Z4 0.36fF
-C862 pll_full_1/divider_0/tspc_2/Z3 pll_full_1/div 0.05fF
-C863 io_clamp_low[0] io_clamp_high[0] 0.53fF
-C864 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C865 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C866 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_4670_0# 29.21fF
-C867 ro_complete_buffered_0/tapered_buf_0/a_160_230# ro_complete_buffered_0/tapered_buf_0/a_n10_230# 0.09fF
-C868 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF
-C869 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C870 pd_1/tspc_r_0/Qbar1 pd_1/REF 0.12fF
-C871 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
-C872 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF
-C873 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
-C874 pll_full_0/div pll_full_0/vco 2.26fF
-C875 ro_complete_buffered_0/tapered_buf_3/a_1650_0# ro_complete_buffered_0/tapered_buf_3/a_4670_0# 4.78fF
-C876 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C877 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C878 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C879 divider_2/tspc_0/Z2 divider_2/nor_1/A 0.23fF
-C880 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF
-C881 divider_1/and_0/OUT divider_1/and_0/B 0.01fF
-C882 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C883 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/DOWN 0.11fF
-C884 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF
-C885 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.29fF
-C886 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF
-C887 pd_1/R pd_1/tspc_r_1/Z3 0.27fF
-C888 pd_1/tspc_r_1/Qbar pd_1/tspc_r_1/Qbar1 0.01fF
-C889 pll_full_1/pd_0/and_pd_0/Out1 pll_full_1/pd_0/R 0.33fF
-C890 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/pd_0/tspc_r_0/Qbar 0.01fF
-C891 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Q 0.55fF
-C892 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/vco 1.46fF
-C893 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF
-C894 divider_1/tspc_1/Z2 divider_1/tspc_1/a_630_n680# 0.01fF
-C895 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C896 pll_full_1/ro_complete_0/cbank_2/switch_1/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
-C897 divider_2/tspc_0/Q divider_2/nor_1/A 0.55fF
-C898 ro_complete_buffered_0/tapered_buf_6/a_1650_0# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 2.89fF
-C899 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_2/Z4 0.02fF
-C900 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C901 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 pll_full_1/vco 0.45fF
-C902 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF
-C903 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF
-C904 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Qbar1 0.20fF
-C905 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
-C906 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF
-C907 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
-C908 ro_complete_buffered_0/tapered_buf_6/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
-C909 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/R 0.27fF
-C910 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF
-C911 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF
-C912 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Q 0.22fF
-C913 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
-C914 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
-C915 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
-C916 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C917 ro_complete_buffered_0/tapered_buf_4/a_n10_230# ro_complete_buffered_0/tapered_buf_4/in 0.02fF
-C918 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.03fF
-C919 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF
-C920 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF
-C921 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/UP 0.11fF
-C922 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C923 pd_0/DIV pd_0/tspc_r_1/Z2 0.19fF
-C924 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
-C925 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/R 0.02fF
-C926 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Z4 0.20fF
-C927 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
-C928 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF
-C929 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C930 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C931 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C932 io_clamp_high[2] io_analog[6] 0.53fF
-C933 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF
-C934 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF
-C935 pll_full_1/pd_0/tspc_r_1/z5 pll_full_1/div 0.04fF
-C936 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF
-C937 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF
-C938 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF
-C939 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF
-C940 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF
-C941 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.22fF
-C942 ro_complete_buffered_0/tapered_buf_3/a_160_230# ro_complete_buffered_0/tapered_buf_3/a_580_0# 0.02fF
-C943 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
-C944 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
-C945 ro_complete_buffered_0/tapered_buf_5/a_580_0# ro_complete_buffered_0/tapered_buf_5/a_1650_0# 1.27fF
-C946 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/UP 0.03fF
-C947 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF
-C948 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C949 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF
-C950 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
-C951 pd_1/tspc_r_1/Z2 pd_1/R 0.21fF
-C952 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF
-C953 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
-C954 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
-C955 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
-C956 divider_1/mc2 divider_1/and_0/A 0.16fF
-C957 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF
-C958 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF
-C959 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_0/Q 0.01fF
-C960 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.11fF
-C961 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF
-C962 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF
-C963 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/in 0.19fF
-C964 pd_0/REF pd_0/tspc_r_0/Z3 0.65fF
-C965 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
-C966 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C967 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
-C968 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/vco 0.11fF
-C969 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
-C970 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF
-C971 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
-C972 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF
-C973 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF
-C974 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/a4 0.12fF
-C975 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C976 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_1/A 0.01fF
-C977 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF
-C978 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/vco 0.45fF
-C979 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF
-C980 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF
-C981 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF
-C982 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
-C983 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C984 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C985 pd_1/tspc_r_0/Z3 pd_1/tspc_r_0/Qbar1 0.38fF
-C986 pd_0/tspc_r_0/Qbar pd_0/DOWN 0.02fF
-C987 pd_0/tspc_r_0/Qbar1 pd_0/R 0.30fF
-C988 pll_full_1/pd_0/DOWN pll_full_1/cp_0/a_1710_0# 0.04fF
-C989 pll_full_0/filter_0/a_4216_n5230# pll_full_0/vco 1.58fF
-C990 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/Z3 0.65fF
-C991 pd_1/DOWN pd_1/UP 0.46fF
-C992 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/div 0.03fF
-C993 pll_full_0/divider_0/and_0/OUT pll_full_0/vco 0.06fF
-C994 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
-C995 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF
-C996 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
-C997 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C998 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C999 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C1000 pll_full_1/ro_complete_0/cbank_1/switch_1/vin pll_full_1/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1001 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF
-C1002 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF
-C1003 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1004 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C1005 pll_full_1/ro_complete_0/a4 pll_full_1/vco 0.01fF
-C1006 ro_complete_buffered_0/tapered_buf_7/a_n10_n140# ro_complete_buffered_0/tapered_buf_7/in 0.04fF
-C1007 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF
-C1008 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# ro_complete_buffered_0/tapered_buf_0/a_n10_230# 0.01fF
-C1009 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1010 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C1011 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/vco 0.64fF
-C1012 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF
-C1013 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
-C1014 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
-C1015 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/nor_1/A 0.15fF
-C1016 pll_full_1/ro_complete_0/cbank_0/switch_5/vin pll_full_1/ro_complete_0/a0 0.09fF
-C1017 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.30fF
-C1018 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF
-C1019 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1020 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1021 pll_full_1/divider_0/and_0/B pll_full_1/divider_0/and_0/Z1 0.07fF
-C1022 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1023 pll_full_1/pd_0/tspc_r_0/Z4 pll_full_1/pd_0/tspc_r_0/z5 0.04fF
-C1024 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C1025 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1026 pd_1/R pd_1/DOWN 0.36fF
-C1027 pll_full_1/pd_0/tspc_r_0/Z2 pll_full_1/pd_0/R 0.21fF
-C1028 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
-C1029 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF
-C1030 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
-C1031 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/DOWN 0.03fF
-C1032 divider_1/and_0/out1 divider_1/and_0/A 0.01fF
-C1033 divider_2/and_0/OUT divider_2/clk 0.04fF
-C1034 pll_full_1/divider_0/tspc_0/Z1 pll_full_1/divider_0/tspc_0/Z3 0.06fF
-C1035 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 pll_full_1/vco 0.12fF
-C1036 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF
-C1037 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z4 0.21fF
-C1038 pd_1/R pd_1/UP 0.45fF
-C1039 pd_1/DOWN pd_1/and_pd_0/Out1 0.12fF
-C1040 pd_1/tspc_r_1/Z4 pd_1/tspc_r_1/z5 0.04fF
-C1041 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF
-C1042 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.04fF
-C1043 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF
-C1044 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
-C1045 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/a3 0.13fF
-C1046 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF
-C1047 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF
-C1048 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF
-C1049 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_1/a_630_n680# 0.01fF
-C1050 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1051 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1052 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/nor_0/B 0.35fF
-C1053 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/vco 0.60fF
-C1054 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
-C1055 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C1056 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1057 pd_1/tspc_r_0/Z2 pd_1/REF 0.19fF
-C1058 pd_0/DIV pd_0/R 0.51fF
-C1059 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF
-C1060 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
-C1061 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF
-C1062 pd_1/and_pd_0/Out1 pd_1/UP 0.33fF
-C1063 io_clamp_low[1] io_analog[5] 0.53fF
-C1064 pll_full_1/pd_0/tspc_r_0/Qbar pll_full_1/pd_0/R 0.03fF
-C1065 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF
-C1066 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF
-C1067 ro_complete_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.19fF
-C1068 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1069 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF
-C1070 ro_complete_buffered_0/tapered_buf_5/a_1650_0# ro_complete_buffered_0/tapered_buf_5/a_4670_0# 4.78fF
-C1071 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_160_230# 0.17fF
-C1072 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/UP 0.21fF
-C1073 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF
-C1074 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF
-C1075 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF
-C1076 pll_full_1/divider_0/tspc_0/Z1 pll_full_1/divider_0/tspc_0/Z2 1.07fF
-C1077 pll_full_1/ro_complete_0/a1 pll_full_1/vco 0.11fF
-C1078 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
-C1079 ro_complete_buffered_0/tapered_buf_0/a_1650_0# ro_complete_buffered_0/tapered_buf_0/a_4670_0# 4.78fF
-C1080 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1081 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/div 0.12fF
-C1082 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1083 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
-C1084 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF
-C1085 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1086 pll_full_0/ro_complete_0/a0 pll_full_0/vco 0.11fF
-C1087 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z3 0.65fF
-C1088 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF
-C1089 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
-C1090 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1091 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF
-C1092 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_0/Q 0.45fF
-C1093 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF
-C1094 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF
-C1095 gnd ro_complete_buffered_0/tapered_buf_1/a_580_0# 5.71fF
-C1096 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
-C1097 divider_1/prescaler_0/Out divider_1/nor_1/A 0.15fF
-C1098 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF
-C1099 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
-C1100 pd_1/DOWN pd_1/tspc_r_0/Qbar 0.02fF
-C1101 pd_1/R pd_1/and_pd_0/Out1 0.33fF
-C1102 pll_full_1/cp_0/down pll_full_1/cp_0/a_1710_0# 0.32fF
-C1103 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
-C1104 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C1105 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF
-C1106 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/and_0/OUT 0.06fF
-C1107 pll_full_1/pd_0/R pll_full_1/div 0.51fF
-C1108 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF
-C1109 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/ref 0.17fF
-C1110 divider_1/nor_1/B divider_1/tspc_0/Q 0.22fF
-C1111 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF
-C1112 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF
-C1113 pll_full_1/divider_0/tspc_0/Z2 pll_full_1/divider_0/tspc_0/Z3 0.16fF
-C1114 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 pll_full_1/vco 0.12fF
-C1115 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF
-C1116 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
-C1117 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C1118 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1119 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
-C1120 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
-C1121 divider_2/mc2 divider_2/and_0/A 0.16fF
-C1122 divider_2/nor_1/B divider_2/nor_0/B 0.47fF
-C1123 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
-C1124 pd_1/tspc_r_0/Qbar pd_1/UP 0.21fF
-C1125 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/vco 0.26fF
-C1126 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF
-C1127 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
-C1128 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
-C1129 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1130 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_1/Z4 0.00fF
-C1131 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF
-C1132 divider_2/and_0/A divider_2/and_0/B 0.18fF
-C1133 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
-C1134 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
-C1135 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.22fF
-C1136 ro_complete_buffered_0/tapered_buf_0/a_160_230# ro_complete_buffered_0/tapered_buf_0/a_580_0# 0.02fF
-C1137 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
-C1138 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1139 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
-C1140 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF
-C1141 pll_full_0/ro_complete_0/a3 pll_full_0/vco 0.11fF
-C1142 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
-C1143 divider_2/prescaler_0/Out divider_2/tspc_0/Z3 0.45fF
-C1144 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF
-C1145 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF
-C1146 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF
-C1147 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF
-C1148 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1149 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
-C1150 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1151 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/vco 0.14fF
-C1152 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF
-C1153 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF
-C1154 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF
-C1155 ro_complete_buffered_0/tapered_buf_1/a_160_230# ro_complete_buffered_0/tapered_buf_1/a_580_0# 0.02fF
-C1156 pll_full_1/pd_0/tspc_r_1/z5 pll_full_1/pd_0/DOWN 0.03fF
-C1157 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
-C1158 pd_1/R pd_1/tspc_r_0/Qbar 0.03fF
-C1159 pd_0/and_pd_0/Out1 pd_0/UP 0.33fF
-C1160 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Qbar1 0.38fF
-C1161 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
-C1162 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF
-C1163 ro_complete_buffered_0/tapered_buf_2/a_n10_n140# ro_complete_buffered_0/tapered_buf_2/a_160_n140# 0.05fF
-C1164 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1165 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/R 0.03fF
-C1166 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF
-C1167 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1168 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_1/Z2 0.15fF
-C1169 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/a_630_n680# 0.01fF
-C1170 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/a_630_n680# 0.01fF
-C1171 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF
-C1172 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
-C1173 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
-C1174 pd_1/tspc_r_0/Z2 pd_1/tspc_r_0/Z3 0.25fF
-C1175 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
-C1176 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF
-C1177 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF
-C1178 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1179 pd_1/tspc_r_0/Qbar pd_1/and_pd_0/Out1 0.05fF
-C1180 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF
-C1181 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C1182 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
-C1183 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF
-C1184 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF
-C1185 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1186 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
-C1187 divider_2/tspc_1/Z2 divider_2/nor_1/A 0.15fF
-C1188 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF
-C1189 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/nor_1/B 0.30fF
-C1190 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 0.22fF
-C1191 ro_complete_buffered_0/tapered_buf_7/a_580_0# ro_complete_buffered_0/tapered_buf_7/a_160_230# 0.02fF
-C1192 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/and_0/Z1 0.04fF
-C1193 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/tspc_2/Z2 0.01fF
-C1194 pll_full_1/divider_0/prescaler_0/tspc_2/Q pll_full_1/vco 0.05fF
-C1195 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
-C1196 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1197 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.21fF
-C1198 pd_0/tspc_r_1/Qbar1 pd_0/R 0.01fF
-C1199 pd_0/DIV pd_0/tspc_r_1/Z4 0.02fF
-C1200 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
-C1201 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z2 0.16fF
-C1202 filter_0/a_4216_n5230# filter_0/v 0.91fF
-C1203 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF
-C1204 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/div 0.05fF
-C1205 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF
-C1206 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1207 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF
-C1208 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1209 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_n10_n140# 0.05fF
-C1210 ro_complete_buffered_0/tapered_buf_5/a_580_0# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 0.84fF
-C1211 ro_complete_buffered_0/tapered_buf_5/a_210_n610# ro_complete_buffered_0/ro_complete_0/a0 26.29fF
-C1212 pll_full_1/divider_0/and_0/out1 pll_full_1/divider_0/and_0/B 0.18fF
-C1213 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF
-C1214 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1215 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
-C1216 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
-C1217 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
-C1218 cp_0/a_1710_0# cp_0/down 0.32fF
-C1219 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
-C1220 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
-C1221 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF
-C1222 divider_2/prescaler_0/Out divider_2/tspc_0/Z4 0.12fF
-C1223 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
-C1224 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1225 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF
-C1226 divider_2/nor_1/A divider_2/and_0/A 0.01fF
-C1227 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_580_0# 0.35fF
-C1228 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/nor_0/B 0.00fF
-C1229 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1230 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF
-C1231 gnd ro_complete_buffered_0/tapered_buf_1/a_1650_0# 20.70fF
-C1232 ro_complete_buffered_0/tapered_buf_6/a_n10_230# ro_complete_buffered_0/tapered_buf_6/in 0.02fF
-C1233 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1234 cp_0/a_1710_0# cp_0/out 0.84fF
-C1235 pd_0/REF pd_0/tspc_r_0/Z1 0.17fF
-C1236 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
-C1237 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Z4 0.20fF
-C1238 pd_1/DIV pd_1/tspc_r_1/z5 0.04fF
-C1239 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/pd_0/UP 0.11fF
-C1240 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF
-C1241 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
-C1242 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/vco 0.45fF
-C1243 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF
-C1244 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF
-C1245 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1246 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1247 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/a4 0.09fF
-C1248 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/a5 0.09fF
-C1249 pll_full_1/pd_0/tspc_r_1/Z1 pll_full_1/div 0.17fF
-C1250 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF
-C1251 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_160_230# 0.17fF
-C1252 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z1 0.03fF
-C1253 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1254 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1255 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF
-C1256 divider_2/tspc_2/Z3 divider_2/Out 0.05fF
-C1257 divider_0/mc2 divider_0/nor_1/B 0.06fF
-C1258 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
-C1259 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/a_210_n610# 26.29fF
-C1260 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
-C1261 pll_full_1/pd_0/tspc_r_1/z5 pll_full_1/pd_0/tspc_r_0/z5 0.02fF
-C1262 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
-C1263 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
-C1264 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
-C1265 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
-C1266 pll_full_1/pd_0/tspc_r_0/z5 pll_full_1/pd_0/tspc_r_0/Qbar1 0.20fF
-C1267 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
-C1268 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF
-C1269 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1270 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/Out 0.05fF
-C1271 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF
-C1272 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF
-C1273 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
-C1274 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF
-C1275 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_1/Z4 0.65fF
-C1276 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1277 pll_full_1/ro_complete_0/a5 pll_full_1/vco 0.15fF
-C1278 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C1279 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.19fF
-C1280 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
-C1281 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
-C1282 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
-C1283 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
-C1284 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF
-C1285 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
-C1286 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1287 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1288 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Z2 0.25fF
-C1289 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF
-C1290 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF
-C1291 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF
-C1292 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
-C1293 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF
-C1294 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF
-C1295 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF
-C1296 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z3 0.38fF
-C1297 ro_complete_buffered_0/tapered_buf_1/a_210_n610# gnd 212.43fF
-C1298 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF
-C1299 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
-C1300 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF
-C1301 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_0/a_630_n680# 0.04fF
-C1302 pd_1/tspc_r_1/Z2 pd_1/tspc_r_1/Z4 0.14fF
-C1303 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_0/Q 0.01fF
-C1304 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
-C1305 ro_complete_buffered_0/tapered_buf_2/in ro_complete_buffered_0/tapered_buf_2/a_160_n140# 0.19fF
-C1306 ro_complete_buffered_0/tapered_buf_2/a_580_0# ro_complete_buffered_0/tapered_buf_2/a_1650_0# 1.27fF
-C1307 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1308 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF
-C1309 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF
-C1310 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
-C1311 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1312 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1313 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF
-C1314 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF
-C1315 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF
-C1316 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/nor_0/B 0.22fF
-C1317 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1318 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/vco 0.01fF
-C1319 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF
-C1320 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
-C1321 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF
-C1322 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
-C1323 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
-C1324 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/m1_2700_2190# 0.08fF
-C1325 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/vco 0.45fF
-C1326 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
-C1327 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF
-C1328 ro_complete_buffered_0/tapered_buf_4/a_n10_n140# ro_complete_buffered_0/tapered_buf_4/in 0.04fF
-C1329 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z2 0.23fF
-C1330 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1331 pll_full_1/ro_complete_0/cbank_1/switch_3/vin pll_full_1/vco 1.46fF
-C1332 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF
-C1333 divider_2/mc2 divider_2/nor_1/B 0.06fF
-C1334 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/in 0.19fF
-C1335 ro_complete_buffered_0/tapered_buf_7/a_1650_0# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 2.89fF
-C1336 ro_complete_buffered_0/tapered_buf_4/a_210_n610# ro_complete_buffered_0/ro_complete_0/a1 26.29fF
-C1337 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/div 0.04fF
-C1338 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z2 0.40fF
-C1339 pll_full_1/divider_0/prescaler_0/tspc_0/D pll_full_1/vco 0.29fF
-C1340 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/and_pd_0/Out1 0.18fF
-C1341 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
-C1342 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1343 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF
-C1344 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
-C1345 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
-C1346 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
-C1347 pd_0/tspc_r_0/Qbar pd_0/and_pd_0/Z1 0.02fF
-C1348 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
-C1349 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
-C1350 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
-C1351 pll_full_1/pd_0/DOWN pll_full_1/pd_0/R 0.36fF
-C1352 pll_full_1/pd_0/tspc_r_0/Z2 pll_full_1/ref 0.19fF
-C1353 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
-C1354 pll_full_0/ro_complete_0/a4 pll_full_0/vco 0.01fF
-C1355 io_clamp_high[0] io_analog[4] 0.53fF
-C1356 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Qbar1 0.38fF
-C1357 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/R 0.29fF
-C1358 pll_full_0/ref pll_full_0/pd_0/R 0.61fF
-C1359 divider_2/nor_1/B divider_2/and_0/B 0.31fF
-C1360 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
-C1361 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
-C1362 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
-C1363 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z3 0.20fF
-C1364 divider_1/and_0/OUT divider_1/clk 0.04fF
-C1365 ro_complete_buffered_0/tapered_buf_5/a_4670_0# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 29.21fF
-C1366 ro_complete_buffered_0/tapered_buf_5/a_n10_230# ro_complete_buffered_0/tapered_buf_5/a_160_230# 0.09fF
-C1367 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/tspc_1/Q 0.04fF
-C1368 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1369 pll_full_1/ro_complete_0/cbank_0/v pll_full_1/vco 1.27fF
-C1370 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF
-C1371 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF
-C1372 ro_complete_buffered_0/tapered_buf_1/a_n10_230# ro_complete_buffered_0/tapered_buf_1/a_n10_n140# 0.01fF
-C1373 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_1/A 0.15fF
-C1374 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF
-C1375 divider_2/nor_1/B divider_2/nor_1/Z1 0.06fF
-C1376 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_6/in 1.43fF
-C1377 pd_0/R pd_0/UP 0.45fF
-C1378 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.01fF
-C1379 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF
-C1380 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
-C1381 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF
-C1382 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
-C1383 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
-C1384 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF
-C1385 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF
-C1386 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/tapered_buf_2/a_580_0# 0.84fF
-C1387 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF
-C1388 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
-C1389 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF
-C1390 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF
-C1391 ro_complete_buffered_0/tapered_buf_6/a_580_0# ro_complete_buffered_0/tapered_buf_6/a_1650_0# 1.27fF
-C1392 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/nor_0/B 0.47fF
-C1393 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF
-C1394 divider_0/mc2 divider_0/and_0/A 0.16fF
-C1395 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1396 gnd ro_complete_buffered_0/tapered_buf_1/a_4670_0# 82.48fF
-C1397 ro_complete_buffered_0/tapered_buf_1/a_n10_n140# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.05fF
-C1398 pd_1/tspc_r_0/Z1 pd_1/tspc_r_0/Z2 0.71fF
-C1399 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
-C1400 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/div 0.19fF
-C1401 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
-C1402 pd_1/tspc_r_1/Qbar1 pd_1/tspc_r_1/z5 0.20fF
-C1403 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
-C1404 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF
-C1405 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/vco 0.12fF
-C1406 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
-C1407 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF
-C1408 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF
-C1409 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1410 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
-C1411 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_n10_n140# 0.05fF
-C1412 ro_complete_buffered_0/tapered_buf_4/a_580_0# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 0.84fF
-C1413 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF
-C1414 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/and_0/out1 0.31fF
-C1415 pll_full_1/divider_0/tspc_1/Z4 pll_full_1/divider_0/tspc_0/Q 0.15fF
-C1416 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
-C1417 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
-C1418 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF
-C1419 pd_0/DIV pd_0/tspc_r_1/Z3 0.65fF
-C1420 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
-C1421 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
-C1422 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
-C1423 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
-C1424 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
-C1425 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
-C1426 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
-C1427 pll_full_1/ref pll_full_1/pd_0/tspc_r_0/Z1 0.17fF
-C1428 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF
-C1429 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/vco 0.60fF
-C1430 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF
-C1431 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_1650_0# 2.89fF
-C1432 pll_full_1/ro_complete_0/cbank_1/switch_1/vin pll_full_1/ro_complete_0/cbank_1/switch_0/vin 0.19fF
-C1433 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/nor_1/B 0.35fF
-C1434 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/vco 0.11fF
-C1435 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF
-C1436 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF
-C1437 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF
-C1438 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF
-C1439 divider_1/nor_1/B divider_1/tspc_1/Z2 0.30fF
-C1440 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF
-C1441 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
-C1442 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/and_0/B 0.29fF
-C1443 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
-C1444 divider_2/and_0/B divider_2/and_0/Z1 0.07fF
-C1445 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
-C1446 pd_0/R pd_0/and_pd_0/Out1 0.33fF
-C1447 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF
-C1448 pll_full_0/ro_complete_0/a1 pll_full_0/vco 0.11fF
-C1449 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
-C1450 divider_1/mc2 divider_1/and_0/out1 0.06fF
-C1451 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF
-C1452 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF
-C1453 pll_full_1/pd_0/UP pll_full_1/pd_0/R 0.46fF
-C1454 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF
-C1455 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF
-C1456 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
-C1457 pll_full_1/divider_0/nor_1/Z1 pll_full_1/divider_0/nor_1/B 0.06fF
-C1458 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF
-C1459 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/and_0/OUT 0.05fF
-C1460 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF
-C1461 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF
-C1462 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF
-C1463 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
-C1464 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
-C1465 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/div 0.04fF
-C1466 pd_1/DIV pd_1/tspc_r_1/Z3 0.65fF
-C1467 pd_1/tspc_r_0/Qbar1 pd_1/UP 0.11fF
-C1468 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_0/Q 0.45fF
-C1469 divider_2/nor_1/B divider_2/nor_1/A 1.21fF
-C1470 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF
-C1471 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF
-C1472 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Qbar1 0.20fF
-C1473 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF
-C1474 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF
-C1475 divider_1/and_0/A divider_1/and_0/B 0.18fF
-C1476 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF
-C1477 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
-C1478 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z2 0.14fF
-C1479 pll_full_1/divider_0/tspc_0/a_630_n680# pll_full_1/divider_0/tspc_0/Z3 0.05fF
-C1480 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/divider_0/prescaler_0/tspc_0/D 0.32fF
-C1481 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/vco 0.01fF
-C1482 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF
-C1483 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF
-C1484 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF
-C1485 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF
-C1486 divider_1/nor_1/B divider_1/and_0/A 0.26fF
-C1487 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1488 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
-C1489 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
-C1490 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
-C1491 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
-C1492 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/a_630_n680# 0.12fF
-C1493 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
-C1494 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF
-C1495 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/vco 0.12fF
-C1496 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
-C1497 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
-C1498 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
-C1499 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
-C1500 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
-C1501 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_740_n680# 0.21fF
-C1502 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF
-C1503 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF
-C1504 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/tspc_r_1/z5 0.20fF
-C1505 divider_2/tspc_1/Z3 divider_2/tspc_1/a_630_n680# 0.05fF
-C1506 divider_2/tspc_0/Z3 divider_2/tspc_0/Z4 0.65fF
-C1507 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF
-C1508 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
-C1509 pll_full_1/divider_0/nor_1/Z1 pll_full_1/divider_0/and_0/B 0.18fF
-C1510 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.00fF
-C1511 pll_full_1/divider_0/nor_0/B pll_full_1/div 0.27fF
-C1512 pll_full_1/divider_0/tspc_2/Z1 pll_full_1/divider_0/tspc_2/Z3 0.06fF
-C1513 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/UP 0.33fF
-C1514 divider_0/prescaler_0/Out divider_0/clk 0.51fF
-C1515 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
-C1516 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1517 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
-C1518 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
-C1519 cp_0/a_1710_0# cp_0/a_10_n50# 0.04fF
-C1520 pd_1/tspc_r_0/Qbar1 pd_1/R 0.30fF
-C1521 pd_0/tspc_r_1/Z2 pd_0/R 0.21fF
-C1522 pd_0/DOWN pd_0/tspc_r_1/z5 0.03fF
-C1523 pd_0/tspc_r_0/Z3 pd_0/UP 0.03fF
-C1524 pll_full_1/pd_0/and_pd_0/Out1 pll_full_1/pd_0/tspc_r_0/Qbar 0.05fF
-C1525 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF
-C1526 divider_1/prescaler_0/Out divider_1/clk 0.51fF
-C1527 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
-C1528 divider_2/prescaler_0/Out divider_2/tspc_0/a_630_n680# 0.01fF
-C1529 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF
-C1530 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF
-C1531 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_2/switch_0/vin 0.12fF
-C1532 ro_complete_buffered_0/tapered_buf_5/a_n10_230# ro_complete_buffered_0/tapered_buf_5/a_n10_n140# 0.01fF
-C1533 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_1/Q 0.51fF
-C1534 pll_full_1/divider_0/tspc_0/a_630_n680# pll_full_1/divider_0/tspc_0/Z2 0.01fF
-C1535 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1536 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1537 divider_1/nor_1/B divider_1/tspc_1/Z4 0.21fF
-C1538 ro_complete_buffered_0/tapered_buf_1/a_n10_230# ro_complete_buffered_0/tapered_buf_1/in 0.02fF
-C1539 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/UP 0.06fF
-C1540 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
-C1541 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
-C1542 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1543 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
-C1544 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF
-C1545 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF
-C1546 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF
-C1547 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
-C1548 pd_1/tspc_r_1/Z2 pd_1/DIV 0.19fF
-C1549 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z3 0.09fF
-C1550 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
-C1551 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/vco 0.14fF
-C1552 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/tapered_buf_2/a_1650_0# 2.89fF
-C1553 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF
-C1554 divider_1/tspc_1/Z2 divider_1/nor_1/A 0.15fF
-C1555 divider_1/tspc_0/Z2 divider_1/tspc_0/Z4 0.36fF
-C1556 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF
-C1557 divider_2/tspc_0/Q divider_2/tspc_1/Z2 0.14fF
-C1558 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF
-C1559 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.11fF
-C1560 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
-C1561 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF
-C1562 ro_complete_buffered_0/tapered_buf_6/a_1650_0# ro_complete_buffered_0/tapered_buf_6/a_4670_0# 4.78fF
-C1563 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_160_230# 0.17fF
-C1564 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_2/Z2 0.20fF
-C1565 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
-C1566 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.04fF
-C1567 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF
-C1568 ro_complete_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.19fF
-C1569 gnd ro_complete_buffered_0/ro_complete_0/a4 87.74fF
-C1570 ro_complete_buffered_0/tapered_buf_1/a_580_0# ro_complete_buffered_0/tapered_buf_1/a_1650_0# 1.27fF
-C1571 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1572 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
-C1573 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
-C1574 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
-C1575 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/tspc_r_0/Qbar 0.02fF
-C1576 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z2 0.15fF
-C1577 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
-C1578 divider_0/nor_1/A divider_0/and_0/A 0.01fF
-C1579 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
-C1580 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF
-C1581 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
-C1582 ro_complete_buffered_0/tapered_buf_4/a_4670_0# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 29.21fF
-C1583 ro_complete_buffered_0/tapered_buf_4/a_n10_230# ro_complete_buffered_0/tapered_buf_4/a_160_230# 0.09fF
-C1584 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
-C1585 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
-C1586 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.06fF
-C1587 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/nor_1/B 1.21fF
-C1588 pll_full_1/divider_0/nor_0/Z1 pll_full_1/divider_0/nor_0/B 0.06fF
-C1589 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
-C1590 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
-C1591 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
-C1592 pd_1/tspc_r_0/z5 pd_1/REF 0.04fF
-C1593 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
-C1594 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/B 0.30fF
-C1595 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF
-C1596 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF
-C1597 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/vco 0.05fF
-C1598 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_1/switch_2/vin 0.09fF
-C1599 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF
-C1600 divider_1/nor_1/A divider_1/and_0/A 0.01fF
-C1601 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF
-C1602 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF
-C1603 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF
-C1604 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/and_0/OUT 0.14fF
-C1605 pll_full_1/divider_0/prescaler_0/Out pll_full_1/vco 0.51fF
-C1606 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF
-C1607 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
-C1608 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
-C1609 pd_1/tspc_r_1/Z1 pd_1/tspc_r_1/Z2 0.71fF
-C1610 pd_1/tspc_r_0/Qbar1 pd_1/tspc_r_0/Qbar 0.01fF
-C1611 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF
-C1612 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF
-C1613 ro_complete_buffered_0/tapered_buf_3/a_160_n140# ro_complete_buffered_0/tapered_buf_3/a_580_0# 0.35fF
-C1614 pll_full_1/ro_complete_0/cbank_1/switch_4/vin pll_full_1/ro_complete_0/cbank_1/switch_5/vin 0.20fF
-C1615 pll_full_1/cp_0/upbar pll_full_1/cp_0/down 0.02fF
-C1616 divider_2/prescaler_0/Out divider_2/nor_1/A 0.15fF
-C1617 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF
-C1618 divider_1/tspc_2/Z3 divider_1/Out 0.05fF
-C1619 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF
-C1620 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF
-C1621 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/and_0/B 0.08fF
-C1622 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1623 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.09fF
-C1624 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 pll_full_1/vco 0.12fF
-C1625 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_580_0# 0.84fF
-C1626 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
-C1627 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF
-C1628 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
-C1629 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF
-C1630 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
-C1631 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF
-C1632 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
-C1633 pd_1/tspc_r_1/Z3 pd_1/tspc_r_1/Qbar1 0.38fF
-C1634 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF
-C1635 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
-C1636 divider_1/nor_1/A divider_1/tspc_1/Z4 0.02fF
-C1637 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF
-C1638 ro_complete_buffered_0/tapered_buf_2/a_1650_0# ro_complete_buffered_0/tapered_buf_2/a_4670_0# 4.78fF
-C1639 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
-C1640 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_580_0# 0.35fF
-C1641 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_1/Z2 1.07fF
-C1642 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF
-C1643 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF
-C1644 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF
-C1645 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF
-C1646 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF
-C1647 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF
-C1648 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF
-C1649 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF
-C1650 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/and_0/B 0.31fF
-C1651 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/divider_0/prescaler_0/nand_1/z1 0.22fF
-C1652 pll_full_1/divider_0/prescaler_0/tspc_2/Q pll_full_1/divider_0/prescaler_0/tspc_0/D 0.04fF
-C1653 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
-C1654 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF
-C1655 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF
-C1656 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1657 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
-C1658 pll_full_1/pd_0/tspc_r_1/Z2 pll_full_1/pd_0/R 0.21fF
-C1659 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z1 0.03fF
-C1660 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
-C1661 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1662 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF
-C1663 divider_2/mc2 divider_2/and_0/out1 0.06fF
-C1664 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF
-C1665 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
-C1666 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
-C1667 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
-C1668 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF
-C1669 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF
-C1670 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF
-C1671 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
-C1672 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/a1 0.14fF
-C1673 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
-C1674 pll_full_1/ro_complete_0/cbank_0/switch_2/vin pll_full_1/ro_complete_0/a3 0.09fF
-C1675 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
-C1676 ro_complete_buffered_0/tapered_buf_7/a_n10_230# ro_complete_buffered_0/tapered_buf_7/in 0.02fF
-C1677 divider_2/and_0/out1 divider_2/and_0/B 0.18fF
-C1678 pll_full_1/divider_0/tspc_2/Z1 pll_full_1/divider_0/tspc_2/Z4 0.00fF
-C1679 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF
-C1680 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF
-C1681 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_1650_0# 2.89fF
-C1682 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
-C1683 pd_1/tspc_r_0/Z4 pd_1/tspc_r_1/Z4 0.02fF
-C1684 pd_1/tspc_r_0/Z3 pd_1/REF 0.65fF
-C1685 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
-C1686 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF
-C1687 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
-C1688 pll_full_0/ro_complete_0/a5 pll_full_0/vco 0.15fF
-C1689 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF
-C1690 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF
-C1691 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
-C1692 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF
-C1693 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
-C1694 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
-C1695 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF
-C1696 divider_1/mc2 divider_1/nor_0/B 0.15fF
-C1697 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
-C1698 ro_complete_buffered_0/tapered_buf_2/a_n10_230# ro_complete_buffered_0/tapered_buf_2/a_160_230# 0.09fF
-C1699 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/z5 0.11fF
-C1700 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF
-C1701 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
-C1702 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
-C1703 pll_full_1/ro_complete_0/cbank_0/switch_5/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
-C1704 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.12fF
-C1705 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 1.07fF
-C1706 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_1/vco 0.01fF
-C1707 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF
-C1708 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF
-C1709 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
-C1710 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
-C1711 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/m1_2700_2190# 0.19fF
-C1712 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
-C1713 pd_1/R pd_1/DIV 0.51fF
-C1714 pll_full_1/pd_0/tspc_r_0/Z2 pll_full_1/pd_0/tspc_r_0/Z1 0.71fF
-C1715 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF
-C1716 divider_0/nor_1/B divider_0/and_0/B 0.31fF
-C1717 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
-C1718 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF
-C1719 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/tapered_buf_2/a_4670_0# 29.21fF
-C1720 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF
-C1721 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.28fF
-C1722 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_n10_n140# 0.05fF
-C1723 ro_complete_buffered_0/tapered_buf_6/a_580_0# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 0.84fF
-C1724 pll_full_1/ro_complete_0/cbank_2/v pll_full_1/vco 1.36fF
-C1725 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF
-C1726 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF
-C1727 gnd ro_complete_buffered_0/tapered_buf_1/a_160_n140# 1.34fF
-C1728 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/R 0.01fF
-C1729 pd_1/tspc_r_0/z5 pd_1/tspc_r_0/Z3 0.11fF
-C1730 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
-C1731 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
-C1732 pd_0/REF pd_0/tspc_r_0/z5 0.04fF
-C1733 pll_full_1/pd_0/DOWN pll_full_1/ref 1.48fF
-C1734 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
-C1735 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
-C1736 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF
-C1737 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
-C1738 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/ref 0.65fF
-C1739 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF
-C1740 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
-C1741 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/vco 0.01fF
-C1742 divider_0/and_0/OUT divider_0/clk 0.04fF
-C1743 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF
-C1744 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF
-C1745 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF
-C1746 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
-C1747 divider_2/tspc_0/Z1 divider_2/tspc_0/Z4 0.00fF
-C1748 ro_complete_buffered_0/tapered_buf_4/a_n10_230# ro_complete_buffered_0/tapered_buf_4/a_n10_n140# 0.01fF
-C1749 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/a_630_n680# 0.35fF
-C1750 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.91fF
-C1751 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C0 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Qbar1 0.38fF
+C1 pll_full_0/ref pll_full_0/pd_0/R 0.61fF
+C2 divider_2/nor_1/B divider_2/and_0/B 0.31fF
+C3 divider_0/and_0/out1 divider_0/and_0/A 0.01fF
+C4 divider_0/tspc_0/Z1 divider_0/tspc_0/Z2 1.07fF
+C5 ro_complete_0/a2 ro_complete_0/cbank_2/v 0.05fF
+C6 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C7 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/Z3 0.20fF
+C8 divider_1/and_0/OUT divider_1/clk 0.04fF
+C9 divider_2/prescaler_0/tspc_2/Z4 divider_2/prescaler_0/tspc_2/D 0.11fF
+C10 divider_2/prescaler_0/m1_2700_2190# divider_2/clk 0.01fF
+C11 ro_complete_buffered_0/tapered_buf_5/a_4670_0# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 29.21fF
+C12 ro_complete_buffered_0/tapered_buf_5/a_n10_230# ro_complete_buffered_0/tapered_buf_5/a_160_230# 0.09fF
+C13 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/tspc_1/Q 0.04fF
+C14 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C15 pll_full_1/ro_complete_0/cbank_0/v pll_full_1/vco 1.27fF
+C16 ro_complete_buffered_0/tapered_buf_1/a_n10_230# ro_complete_buffered_0/tapered_buf_1/a_n10_n140# 0.01fF
+C17 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/clk 0.01fF
+C18 divider_2/nor_1/B divider_2/nor_1/Z1 0.06fF
+C19 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin ro_complete_buffered_0/tapered_buf_6/in 1.43fF
+C20 pd_buffered_0/tapered_buf_0/a_160_n140# pd_buffered_0/tapered_buf_0/a_580_0# 0.35fF
+C21 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/nor_1/A 0.15fF
+C22 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/a0 0.09fF
+C23 divider_2/nor_1/B divider_2/tspc_0/a_630_n680# 0.01fF
+C24 divider_2/mc2 divider_2/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C25 divider_0/nor_1/A divider_0/prescaler_0/tspc_1/Q 0.03fF
+C26 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/clk 0.01fF
+C27 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C28 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C29 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C30 pd_0/and_pd_0/Out1 pd_0/UP 0.33fF
+C31 pll_full_0/divider_0/and_0/B pll_full_0/divider_0/and_0/Z1 0.07fF
+C32 divider_1/tspc_1/Z2 divider_1/tspc_1/Z3 0.16fF
+C33 divider_1/prescaler_0/m1_2700_2190# divider_1/and_0/OUT 0.14fF
+C34 ro_complete_0/cbank_0/v ro_complete_0/cbank_2/v 0.04fF
+C35 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z3 0.16fF
+C36 divider_2/prescaler_0/tspc_0/Z4 divider_2/clk 0.12fF
+C37 divider_2/prescaler_0/tspc_2/Z3 divider_2/clk 0.45fF
+C38 divider_1/nor_1/B divider_1/nor_0/Z1 0.18fF
+C39 ro_complete_buffered_0/tapered_buf_6/a_580_0# ro_complete_buffered_0/tapered_buf_6/a_1650_0# 1.27fF
+C40 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/nor_0/B 0.47fF
+C41 divider_1/nor_1/B divider_1/tspc_1/Q 0.51fF
+C42 divider_0/mc2 divider_0/and_0/A 0.16fF
+C43 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C44 ro_complete_buffered_0/tapered_buf_1/a_n10_n140# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.05fF
+C45 gnd ro_complete_buffered_0/tapered_buf_1/a_4670_0# 82.48fF
+C46 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C47 cp_buffered_0/cp_0/down cp_buffered_0/cp_0/a_1710_0# 0.32fF
+C48 pll_full_0/pd_0/tspc_r_1/Z2 pll_full_0/div 0.19fF
+C49 divider_0/nor_1/A divider_0/tspc_0/Z2 0.23fF
+C50 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z3 0.06fF
+C51 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 pll_full_0/vco 0.12fF
+C52 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_1/Z4 0.02fF
+C53 divider_1/nor_1/A divider_1/prescaler_0/tspc_1/Q 0.03fF
+C54 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/D 0.15fF
+C55 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C56 ro_complete_buffered_0/tapered_buf_4/a_580_0# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 0.84fF
+C57 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_n10_n140# 0.05fF
+C58 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Z4 0.65fF
+C59 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z4 0.12fF
+C60 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/and_0/out1 0.31fF
+C61 pll_full_1/divider_0/tspc_1/Z4 pll_full_1/divider_0/tspc_0/Q 0.15fF
+C62 cp_buffered_0/tapered_buf_2/a_210_n610# cp_buffered_0/cp_0/down 26.29fF
+C63 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/z5 0.03fF
+C64 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/R 0.21fF
+C65 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/UP 0.03fF
+C66 io_clamp_low[2] io_clamp_high[2] 0.53fF
+C67 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a3 0.13fF
+C68 divider_1/nor_1/B divider_1/tspc_2/Z2 0.20fF
+C69 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C70 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C71 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Q 0.04fF
+C72 divider_0/tspc_1/Z2 divider_0/tspc_1/Z3 0.16fF
+C73 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C74 divider_0/nor_1/B divider_0/nor_1/A 1.21fF
+C75 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/a_630_n680# 0.01fF
+C76 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C77 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.05fF
+C78 io_clamp_high[1] io_analog[5] 0.53fF
+C79 pd_0/tspc_r_1/Qbar1 pd_0/R 0.01fF
+C80 pd_0/DIV pd_0/tspc_r_1/Z4 0.02fF
+C81 pd_0/DOWN pd_0/tspc_r_1/Qbar 0.21fF
+C82 pll_full_1/ref pll_full_1/pd_0/tspc_r_0/Z1 0.17fF
+C83 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/nor_0/B 0.35fF
+C84 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/vco 0.60fF
+C85 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_1650_0# 2.89fF
+C86 ro_complete_buffered_0/tapered_buf_2/a_160_230# ro_complete_buffered_0/tapered_buf_2/a_580_0# 0.02fF
+C87 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/v 1.30fF
+C88 pll_full_1/ro_complete_0/cbank_1/switch_1/vin pll_full_1/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C89 divider_1/tspc_1/Q divider_1/tspc_2/Z3 0.45fF
+C90 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/nor_1/B 0.35fF
+C91 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/vco 0.11fF
+C92 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Q 0.04fF
+C93 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z4 0.00fF
+C94 divider_2/prescaler_0/tspc_1/Z3 divider_2/prescaler_0/tspc_1/Q 0.21fF
+C95 divider_2/prescaler_0/tspc_1/Z2 divider_2/clk 0.11fF
+C96 pd_buffered_0/tapered_buf_3/a_n10_n140# pd_buffered_0/tapered_buf_3/in 0.04fF
+C97 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/pd_0/tspc_r_1/Z2 0.71fF
+C98 divider_2/and_0/B divider_2/and_0/Z1 0.07fF
+C99 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z3 0.65fF
+C100 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/and_0/B 0.29fF
+C101 pd_buffered_0/tapered_buf_0/a_210_n610# pd_buffered_0/tapered_buf_0/a_160_n140# 0.22fF
+C102 pd_buffered_0/tapered_buf_0/a_160_230# pd_buffered_0/tapered_buf_0/a_580_0# 0.02fF
+C103 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C104 divider_0/nor_1/B divider_0/nor_0/B 0.47fF
+C105 cp_buffered_0/tapered_buf_1/a_n10_n140# cp_buffered_0/tapered_buf_1/in 0.04fF
+C106 pll_full_0/divider_0/tspc_0/Z1 pll_full_0/divider_0/tspc_0/Z2 1.07fF
+C107 pll_full_0/ro_complete_0/a1 pll_full_0/vco 0.11fF
+C108 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/UP 0.03fF
+C109 divider_1/mc2 divider_1/and_0/out1 0.06fF
+C110 divider_1/tspc_0/Z2 divider_1/tspc_0/Z3 0.16fF
+C111 divider_1/prescaler_0/tspc_1/Z2 divider_1/and_0/OUT 0.06fF
+C112 pll_full_1/pd_0/UP pll_full_1/pd_0/R 0.46fF
+C113 ro_complete_0/a0 ro_complete_0/cbank_1/v 0.05fF
+C114 pll_full_1/divider_0/nor_1/Z1 pll_full_1/divider_0/nor_1/B 0.06fF
+C115 divider_1/tspc_2/Z2 divider_1/tspc_2/Z3 0.16fF
+C116 divider_1/nor_0/B divider_1/tspc_2/Z4 0.22fF
+C117 divider_0/tspc_0/Q divider_0/tspc_0/a_630_n680# 0.04fF
+C118 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/and_0/OUT 0.05fF
+C119 divider_2/prescaler_0/tspc_1/Z4 divider_2/clk 0.12fF
+C120 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/Qbar 0.01fF
+C121 divider_1/nor_1/B divider_1/tspc_1/Z3 0.38fF
+C122 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z2 0.36fF
+C123 pd_0/REF pd_0/tspc_r_0/Z4 0.02fF
+C124 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C125 pll_full_0/pd_0/tspc_r_1/z5 pll_full_0/div 0.04fF
+C126 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z2 0.01fF
+C127 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
+C128 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/z5 0.11fF
+C129 divider_2/nor_1/B divider_2/nor_1/A 1.21fF
+C130 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z3 0.11fF
+C131 cp_buffered_0/tapered_buf_0/a_4670_0# cp_buffered_0/tapered_buf_0/a_210_n610# 29.21fF
+C132 cp_buffered_0/tapered_buf_0/a_n10_230# cp_buffered_0/tapered_buf_0/a_160_230# 0.09fF
+C133 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_0/Q 0.45fF
+C134 divider_1/tspc_1/Z3 divider_1/tspc_1/Z4 0.65fF
+C135 ro_complete_0/a2 ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C136 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a4 0.09fF
+C137 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a5 0.09fF
+C138 ro_complete_0/cbank_2/switch_0/vin ro_complete_0/cbank_2/v 1.45fF
+C139 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
+C140 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Qbar1 0.20fF
+C141 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z4 0.08fF
+C142 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/D 0.05fF
+C143 divider_1/and_0/A divider_1/and_0/B 0.18fF
+C144 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z2 0.14fF
+C145 pll_full_1/divider_0/tspc_0/a_630_n680# pll_full_1/divider_0/tspc_0/Z3 0.05fF
+C146 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/divider_0/prescaler_0/tspc_0/D 0.32fF
+C147 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/vco 0.01fF
+C148 pll_full_0/pd_0/DOWN pll_full_0/pd_0/UP 4.58fF
+C149 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Z2 0.21fF
+C150 divider_2/tspc_2/a_630_n680# divider_2/nor_0/B 0.35fF
+C151 divider_2/prescaler_0/tspc_1/Q divider_2/clk 0.60fF
+C152 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C153 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C154 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C155 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a3 3.17fF
+C156 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C157 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
+C158 divider_0/nor_1/B divider_0/tspc_1/Z3 0.38fF
+C159 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/a_630_n680# 0.12fF
+C160 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Qbar1 0.38fF
+C161 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z3 0.05fF
+C162 divider_0/nor_0/B divider_0/tspc_2/Z1 0.03fF
+C163 pll_full_0/divider_0/tspc_0/Z2 pll_full_0/divider_0/tspc_0/Z3 0.16fF
+C164 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/vco 0.12fF
+C165 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C166 divider_1/prescaler_0/tspc_2/D divider_1/prescaler_0/nand_0/z1 0.24fF
+C167 divider_1/prescaler_0/tspc_0/a_630_n680# divider_1/clk 0.01fF
+C168 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/cbank_0/v 1.30fF
+C169 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C170 pll_full_1/divider_0/nor_1/Z1 pll_full_1/divider_0/and_0/B 0.18fF
+C171 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C172 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/tspc_r_1/z5 0.20fF
+C173 divider_2/tspc_1/Z3 divider_2/tspc_1/a_630_n680# 0.05fF
+C174 divider_2/tspc_0/Z3 divider_2/tspc_0/Z4 0.65fF
+C175 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Q 0.38fF
+C176 cp_buffered_0/tapered_buf_2/a_4670_0# cp_buffered_0/tapered_buf_2/a_210_n610# 29.21fF
+C177 pll_full_1/divider_0/tspc_2/Z1 pll_full_1/divider_0/tspc_2/Z3 0.06fF
+C178 pll_full_1/divider_0/nor_0/B pll_full_1/div 0.27fF
+C179 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/UP 0.33fF
+C180 pd_0/REF pd_0/tspc_r_0/Qbar1 0.12fF
+C181 pd_buffered_0/tapered_buf_0/a_n10_230# pd_buffered_0/tapered_buf_0/a_n10_n140# 0.01fF
+C182 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C183 divider_1/nor_1/B divider_1/and_0/B 0.31fF
+C184 divider_0/prescaler_0/Out divider_0/clk 0.51fF
+C185 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C186 pll_full_1/pd_0/and_pd_0/Out1 pll_full_1/pd_0/tspc_r_0/Qbar 0.05fF
+C187 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z4 0.00fF
+C188 divider_0/prescaler_0/m1_2700_2190# divider_0/nor_1/A 0.01fF
+C189 divider_0/tspc_1/Z1 divider_0/tspc_1/Z4 0.00fF
+C190 pd_0/DOWN pd_0/and_pd_0/Z1 0.07fF
+C191 divider_1/prescaler_0/Out divider_1/clk 0.51fF
+C192 divider_2/prescaler_0/Out divider_2/tspc_0/a_630_n680# 0.01fF
+C193 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_1/Q 0.21fF
+C194 divider_1/prescaler_0/tspc_2/D divider_1/clk 0.26fF
+C195 ro_complete_0/a3 ro_complete_0/cbank_1/v 0.05fF
+C196 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C197 ro_complete_buffered_0/tapered_buf_5/a_n10_230# ro_complete_buffered_0/tapered_buf_5/a_n10_n140# 0.01fF
+C198 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_1/Q 0.51fF
+C199 pll_full_1/divider_0/tspc_0/a_630_n680# pll_full_1/divider_0/tspc_0/Z2 0.01fF
+C200 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C201 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C202 ro_complete_buffered_0/tapered_buf_1/a_n10_230# ro_complete_buffered_0/tapered_buf_1/in 0.02fF
+C203 pll_full_0/pd_0/and_pd_0/Z1 pll_full_0/pd_0/UP 0.06fF
+C204 cp_buffered_0/tapered_buf_2/a_160_n140# cp_buffered_0/tapered_buf_2/a_580_0# 0.35fF
+C205 pd_buffered_0/tapered_buf_0/a_580_0# pd_buffered_0/tapered_buf_0/a_1650_0# 1.27fF
+C206 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C207 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C208 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.08fF
+C209 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C210 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C211 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/vco 0.14fF
+C212 divider_1/prescaler_0/Out divider_1/prescaler_0/m1_2700_2190# 0.11fF
+C213 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/clk 0.14fF
+C214 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/D 0.03fF
+C215 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/clk 0.01fF
+C216 ro_complete_buffered_0/tapered_buf_2/a_4670_0# ro_complete_buffered_0/tapered_buf_2/a_1650_0# 4.78fF
+C217 pll_full_0/pd_0/tspc_r_0/Z4 pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C218 divider_1/tspc_1/Z2 divider_1/nor_1/A 0.15fF
+C219 divider_1/tspc_0/Z2 divider_1/tspc_0/Z4 0.36fF
+C220 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_2/D 0.16fF
+C221 divider_2/tspc_0/Q divider_2/tspc_1/Z2 0.14fF
+C222 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Z4 0.36fF
+C223 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C224 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
+C225 ro_complete_buffered_0/tapered_buf_6/a_1650_0# ro_complete_buffered_0/tapered_buf_6/a_4670_0# 4.78fF
+C226 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_160_230# 0.17fF
+C227 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_2/Z2 0.20fF
+C228 divider_2/prescaler_0/tspc_2/Z4 divider_2/clk 0.12fF
+C229 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/D 0.03fF
+C230 ro_complete_buffered_0/tapered_buf_1/in ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.19fF
+C231 gnd ro_complete_buffered_0/ro_complete_0/a4 87.74fF
+C232 ro_complete_buffered_0/tapered_buf_1/a_580_0# ro_complete_buffered_0/tapered_buf_1/a_1650_0# 1.27fF
+C233 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C234 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C235 pd_0/REF pd_0/R 0.61fF
+C236 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/a_1710_0# 0.83fF
+C237 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/tspc_r_0/Qbar 0.02fF
+C238 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z2 0.15fF
+C239 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C240 divider_0/nor_1/Z1 divider_0/and_0/B 0.18fF
+C241 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C242 pd_0/tspc_r_0/Qbar1 pd_0/UP 0.11fF
+C243 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/a_630_n680# 0.01fF
+C244 divider_0/nor_1/A divider_0/and_0/A 0.01fF
+C245 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/v 1.30fF
+C246 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/D 0.05fF
+C247 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
+C248 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C249 ro_complete_buffered_0/tapered_buf_4/a_4670_0# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 29.21fF
+C250 ro_complete_buffered_0/tapered_buf_4/a_n10_230# ro_complete_buffered_0/tapered_buf_4/a_160_230# 0.09fF
+C251 ro_complete_0/cbank_2/switch_5/vin ro_complete_0/cbank_2/v 1.30fF
+C252 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C253 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/nor_1/B 1.21fF
+C254 pll_full_1/divider_0/nor_0/Z1 pll_full_1/divider_0/nor_0/B 0.06fF
+C255 cp_buffered_0/tapered_buf_2/a_n10_230# cp_buffered_0/tapered_buf_2/a_160_230# 0.09fF
+C256 pd_buffered_0/tapered_buf_1/a_580_0# pd_buffered_0/tapered_buf_1/a_160_n140# 0.35fF
+C257 pd_buffered_0/pd_0/tspc_r_1/Z2 pd_buffered_0/pd_0/tspc_r_1/Z4 0.14fF
+C258 pd_0/tspc_r_0/Z1 pd_0/tspc_r_0/Z2 0.71fF
+C259 cp_buffered_0/cp_0/down cp_buffered_0/cp_0/out 0.79fF
+C260 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/nor_1/B 0.30fF
+C261 divider_0/nor_1/B divider_0/tspc_1/Q 0.51fF
+C262 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C263 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C264 pd_0/tspc_r_0/Qbar pd_0/and_pd_0/Z1 0.02fF
+C265 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/z5 0.11fF
+C266 io_clamp_low[0] io_analog[4] 0.53fF
+C267 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/Z1 0.04fF
+C268 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z2 0.01fF
+C269 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/vco 0.05fF
+C270 divider_1/tspc_1/Q divider_1/tspc_2/Z4 0.15fF
+C271 divider_1/nor_1/A divider_1/and_0/A 0.01fF
+C272 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C273 pll_full_0/pd_0/DOWN pll_full_0/pd_0/R 0.36fF
+C274 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Z4 0.65fF
+C275 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_0/D 0.09fF
+C276 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/and_0/OUT 0.14fF
+C277 pll_full_1/divider_0/prescaler_0/Out pll_full_1/vco 0.51fF
+C278 pd_buffered_0/tapered_buf_0/a_210_n610# pd_buffered_0/tapered_buf_0/a_1650_0# 2.89fF
+C279 pd_buffered_0/tapered_buf_0/a_n10_230# pd_buffered_0/pd_0/UP 0.02fF
+C280 cp_buffered_0/tapered_buf_1/a_210_n610# cp_buffered_0/cp_0/out 26.29fF
+C281 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z2 0.19fF
+C282 divider_0/nor_1/A divider_0/tspc_1/Z4 0.02fF
+C283 divider_0/nor_1/B divider_0/tspc_2/Z2 0.20fF
+C284 pd_0/R pd_0/UP 0.45fF
+C285 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/B 0.18fF
+C286 divider_1/nor_1/Z1 divider_1/and_0/A 0.80fF
+C287 ro_complete_buffered_0/tapered_buf_3/a_160_n140# ro_complete_buffered_0/tapered_buf_3/a_580_0# 0.35fF
+C288 pll_full_1/cp_0/upbar pll_full_1/cp_0/down 0.02fF
+C289 divider_2/prescaler_0/Out divider_2/nor_1/A 0.15fF
+C290 divider_1/tspc_2/Z2 divider_1/tspc_2/Z4 0.36fF
+C291 divider_1/tspc_2/Z3 divider_1/Out 0.05fF
+C292 pll_full_1/ro_complete_0/cbank_1/switch_4/vin pll_full_1/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C293 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Out1 0.33fF
+C294 divider_2/tspc_1/Q divider_2/tspc_2/a_630_n680# 0.01fF
+C295 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/and_0/B 0.08fF
+C296 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C297 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.09fF
+C298 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 pll_full_1/vco 0.12fF
+C299 cp_buffered_0/tapered_buf_2/a_4670_0# cp_buffered_0/tapered_buf_2/a_1650_0# 4.78fF
+C300 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z4 0.20fF
+C301 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C302 pd_buffered_0/pd_0/tspc_r_0/Z1 pd_buffered_0/pd_0/tspc_r_0/Z2 0.71fF
+C303 divider_1/nor_1/B divider_1/nor_1/A 1.21fF
+C304 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_580_0# 0.84fF
+C305 divider_1/tspc_0/Z1 divider_1/tspc_0/Z3 0.06fF
+C306 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
+C307 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z3 0.05fF
+C308 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.04fF
+C309 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C310 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z4 0.28fF
+C311 divider_0/tspc_1/Q divider_0/tspc_2/Z1 0.01fF
+C312 cp_buffered_0/tapered_buf_0/a_n10_230# cp_buffered_0/tapered_buf_0/a_n10_n140# 0.01fF
+C313 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_0/B 0.00fF
+C314 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C315 divider_1/nor_1/A divider_1/tspc_1/Z4 0.02fF
+C316 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z3 0.06fF
+C317 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_580_0# 0.35fF
+C318 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/tspc_r_0/Qbar1 0.01fF
+C319 divider_2/tspc_0/Q divider_2/tspc_1/Z4 0.15fF
+C320 divider_2/tspc_0/Z1 divider_2/tspc_0/Z3 0.06fF
+C321 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z3 0.05fF
+C322 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_1/Z2 1.07fF
+C323 pd_buffered_0/tapered_buf_2/a_n10_230# pd_buffered_0/tapered_buf_2/in 0.02fF
+C324 pll_full_0/pd_0/R pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C325 divider_2/and_0/OUT divider_2/and_0/Z1 0.04fF
+C326 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z2 0.01fF
+C327 divider_2/prescaler_0/tspc_2/Q divider_2/clk 0.05fF
+C328 divider_1/nor_1/B divider_1/nor_1/Z1 0.06fF
+C329 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/and_0/B 0.31fF
+C330 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/divider_0/prescaler_0/nand_1/z1 0.22fF
+C331 pll_full_1/divider_0/prescaler_0/tspc_2/Q pll_full_1/divider_0/prescaler_0/tspc_0/D 0.04fF
+C332 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C333 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z1 0.17fF
+C334 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/DOWN 0.11fF
+C335 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Q 0.91fF
+C336 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C337 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C338 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/a4 0.09fF
+C339 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a5 0.09fF
+C340 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Z4 0.01fF
+C341 pll_full_1/pd_0/tspc_r_1/Z2 pll_full_1/pd_0/R 0.21fF
+C342 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z1 0.03fF
+C343 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C344 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C345 divider_2/mc2 divider_2/and_0/out1 0.06fF
+C346 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Q 0.91fF
+C347 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z4 0.12fF
+C348 divider_0/tspc_2/Z1 divider_0/tspc_2/Z2 1.07fF
+C349 divider_0/nor_0/B divider_0/tspc_2/Z3 0.38fF
+C350 pd_0/DIV pd_0/tspc_r_1/Z3 0.65fF
+C351 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C352 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/a1 0.14fF
+C353 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
+C354 pll_full_1/ro_complete_0/cbank_0/switch_2/vin pll_full_1/ro_complete_0/a3 0.09fF
+C355 divider_1/tspc_1/a_630_n680# divider_1/nor_0/B 0.00fF
+C356 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/Q 0.04fF
+C357 divider_1/prescaler_0/tspc_1/Z3 divider_1/clk 0.45fF
+C358 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C359 cp_buffered_0/tapered_buf_2/a_n10_230# cp_buffered_0/tapered_buf_2/a_n10_n140# 0.01fF
+C360 pd_buffered_0/tapered_buf_3/a_160_n140# pd_buffered_0/tapered_buf_3/a_210_n610# 0.22fF
+C361 pd_buffered_0/tapered_buf_3/a_580_0# pd_buffered_0/tapered_buf_3/a_160_230# 0.02fF
+C362 divider_2/and_0/out1 divider_2/and_0/B 0.18fF
+C363 ro_complete_buffered_0/tapered_buf_7/a_n10_230# ro_complete_buffered_0/tapered_buf_7/in 0.02fF
+C364 pll_full_1/divider_0/tspc_2/Z1 pll_full_1/divider_0/tspc_2/Z4 0.00fF
+C365 divider_0/prescaler_0/Out divider_0/tspc_0/Z2 0.11fF
+C366 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_1650_0# 2.89fF
+C367 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.09fF
+C368 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/Out 0.05fF
+C369 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_1/Q 0.15fF
+C370 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/clk 0.01fF
+C371 divider_0/tspc_1/Z3 divider_0/tspc_1/Z4 0.65fF
+C372 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/Q 0.20fF
+C373 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C374 cp_buffered_0/tapered_buf_1/a_160_n140# cp_buffered_0/tapered_buf_1/a_210_n610# 0.22fF
+C375 cp_buffered_0/tapered_buf_1/a_580_0# cp_buffered_0/tapered_buf_1/a_160_230# 0.02fF
+C376 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Z4 0.65fF
+C377 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C378 pll_full_0/ro_complete_0/a5 pll_full_0/vco 0.15fF
+C379 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Z3 0.65fF
+C380 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z3 0.33fF
+C381 divider_1/mc2 divider_1/nor_0/B 0.15fF
+C382 divider_0/and_0/out1 divider_0/and_0/Z1 0.36fF
+C383 pd_0/R pd_0/and_pd_0/Out1 0.33fF
+C384 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C385 pll_full_1/ro_complete_0/cbank_0/switch_5/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
+C386 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/z5 0.11fF
+C387 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z1 0.06fF
+C388 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/Q 0.05fF
+C389 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/clk 0.01fF
+C390 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C391 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C392 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_1/vco 0.01fF
+C393 pd_buffered_0/tapered_buf_0/a_1650_0# pd_buffered_0/tapered_buf_0/a_4670_0# 4.78fF
+C394 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/m1_2700_2190# 0.19fF
+C395 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
+C396 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C397 divider_0/nor_1/B divider_0/and_0/B 0.31fF
+C398 divider_0/and_0/OUT divider_0/prescaler_0/nand_0/z1 0.01fF
+C399 pll_full_1/pd_0/tspc_r_0/Z2 pll_full_1/pd_0/tspc_r_0/Z1 0.71fF
+C400 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z3 0.38fF
+C401 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/nand_0/z1 0.07fF
+C402 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C403 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C404 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C405 ro_complete_buffered_0/tapered_buf_6/a_580_0# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 0.84fF
+C406 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_n10_n140# 0.05fF
+C407 pd_buffered_0/tapered_buf_2/a_160_n140# pd_buffered_0/tapered_buf_2/a_580_0# 0.35fF
+C408 pll_full_1/ro_complete_0/cbank_2/v pll_full_1/vco 1.36fF
+C409 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/R 0.29fF
+C410 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/R 0.01fF
+C411 divider_0/tspc_0/Q divider_0/tspc_1/Z1 0.01fF
+C412 gnd ro_complete_buffered_0/tapered_buf_1/a_160_n140# 1.34fF
+C413 divider_1/tspc_0/Z1 divider_1/tspc_0/Z4 0.00fF
+C414 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.45fF
+C415 pll_full_1/pd_0/DOWN pll_full_1/ref 1.48fF
+C416 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C417 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C418 divider_0/and_0/OUT divider_0/clk 0.04fF
+C419 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/nor_0/B 0.22fF
+C420 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C421 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/vco 0.01fF
+C422 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/Out 0.05fF
+C423 divider_1/prescaler_0/tspc_2/Z4 divider_1/prescaler_0/tspc_2/D 0.11fF
+C424 divider_1/prescaler_0/m1_2700_2190# divider_1/clk 0.01fF
+C425 ro_complete_buffered_0/tapered_buf_4/a_n10_230# ro_complete_buffered_0/tapered_buf_4/a_n10_n140# 0.01fF
+C426 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/a_630_n680# 0.35fF
+C427 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C428 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C429 divider_2/tspc_0/Z1 divider_2/tspc_0/Z4 0.00fF
+C430 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_580_0# 0.35fF
+C431 io_clamp_low[1] io_clamp_high[1] 0.53fF
+C432 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C433 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.12fF
+C434 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C435 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C436 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/out 0.61fF
+C437 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z2 0.23fF
+C438 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C439 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/vco 1.46fF
+C440 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C441 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C442 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z3 0.16fF
+C443 pd_0/DOWN pd_0/tspc_r_1/z5 0.03fF
+C444 pd_0/tspc_r_1/Z2 pd_0/R 0.21fF
+C445 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/div 0.02fF
+C446 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/div 0.04fF
+C447 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z2 0.40fF
+C448 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/vco 0.29fF
+C449 pll_full_0/cp_0/a_1710_0# pll_full_0/cp_0/down 0.32fF
+C450 divider_1/prescaler_0/tspc_2/Z3 divider_1/clk 0.45fF
+C451 ro_complete_buffered_0/tapered_buf_3/a_160_230# ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.17fF
+C452 ro_complete_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_3/a_n10_230# 0.02fF
+C453 ro_complete_0/a4 ro_complete_0/cbank_1/v 0.05fF
+C454 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C455 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C456 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_0/a_630_n680# 0.01fF
+C457 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C458 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_2/D 0.16fF
+C459 pll_full_1/ro_complete_0/cbank_1/switch_2/vin pll_full_1/vco 1.46fF
+C460 ro_complete_buffered_0/tapered_buf_1/a_n10_230# ro_complete_buffered_0/tapered_buf_1/a_160_230# 0.09fF
+C461 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C462 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z2 0.01fF
+C463 divider_0/tspc_0/Z3 divider_0/tspc_0/Z2 0.16fF
+C464 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/clk 0.14fF
+C465 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
+C466 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/z5 0.11fF
+C467 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Z4 0.20fF
+C468 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Q 0.04fF
+C469 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.33fF
+C470 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/vco 1.27fF
+C471 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Z4 0.65fF
+C472 divider_2/prescaler_0/tspc_1/Z2 divider_2/prescaler_0/tspc_1/a_630_n680# 0.01fF
+C473 pll_full_1/divider_0/nor_0/Z1 pll_full_1/divider_0/nor_1/B 0.18fF
+C474 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
+C475 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C476 divider_2/tspc_1/Q divider_2/nor_0/B 0.22fF
+C477 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_2/Q 0.19fF
+C478 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/clk 0.01fF
+C479 divider_0/prescaler_0/Out divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C480 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_1650_0# 2.89fF
+C481 ro_complete_buffered_0/tapered_buf_1/a_160_230# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.17fF
+C482 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/tspc_r_0/z5 0.20fF
+C483 pll_full_1/pd_0/tspc_r_1/Qbar pll_full_1/pd_0/DOWN 0.21fF
+C484 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z3 0.05fF
+C485 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Z4 0.12fF
+C486 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/nor_0/B 0.47fF
+C487 divider_0/tspc_1/Q divider_0/tspc_2/Z3 0.45fF
+C488 divider_0/tspc_0/Z4 divider_0/tspc_0/Z2 0.36fF
+C489 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Q 0.04fF
+C490 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z4 0.00fF
+C491 divider_1/prescaler_0/tspc_1/Z3 divider_1/prescaler_0/tspc_1/Q 0.21fF
+C492 divider_1/prescaler_0/tspc_1/Z2 divider_1/clk 0.11fF
+C493 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z3 0.05fF
+C494 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Z4 0.12fF
+C495 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/Z2 1.07fF
+C496 divider_1/and_0/B divider_1/and_0/Z1 0.07fF
+C497 ro_complete_buffered_0/tapered_buf_4/a_580_0# ro_complete_buffered_0/tapered_buf_4/a_1650_0# 1.27fF
+C498 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_1/Z3 0.16fF
+C499 pll_full_1/ro_complete_0/cbank_2/switch_2/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
+C500 pll_full_1/divider_0/prescaler_0/tspc_2/Q pll_full_1/divider_0/prescaler_0/nand_1/z1 0.01fF
+C501 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/vco 0.11fF
+C502 divider_2/tspc_2/a_630_n680# divider_2/Out 0.04fF
+C503 divider_2/nor_0/B divider_2/tspc_2/Z2 0.40fF
+C504 divider_2/prescaler_0/tspc_0/D divider_2/clk 0.29fF
+C505 divider_0/tspc_0/Q divider_0/nor_1/A 0.55fF
+C506 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/clk 0.01fF
+C507 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/D 0.09fF
+C508 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/a1 3.18fF
+C509 pd_buffered_0/tapered_buf_1/a_160_230# pd_buffered_0/tapered_buf_1/a_160_n140# 0.17fF
+C510 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/tspc_r_1/z5 0.02fF
+C511 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z2 0.25fF
+C512 pll_full_1/pd_0/tspc_r_1/Z2 pll_full_1/pd_0/tspc_r_1/Z1 0.71fF
+C513 divider_1/prescaler_0/tspc_1/a_630_n680# divider_1/prescaler_0/tspc_1/Q 0.04fF
+C514 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/Z2 0.36fF
+C515 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C516 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Qbar1 0.38fF
+C517 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/out1 0.31fF
+C518 pll_full_0/divider_0/tspc_1/Z4 pll_full_0/divider_0/tspc_0/Q 0.15fF
+C519 divider_0/tspc_2/Z2 divider_0/tspc_2/Z3 0.16fF
+C520 divider_0/nor_0/B divider_0/tspc_2/Z4 0.22fF
+C521 divider_1/prescaler_0/tspc_1/Z4 divider_1/clk 0.12fF
+C522 ro_complete_0/a5 ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C523 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/cbank_0/v 1.30fF
+C524 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/a1 0.14fF
+C525 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z3 0.33fF
+C526 divider_2/prescaler_0/tspc_1/a_630_n680# divider_2/prescaler_0/tspc_1/Q 0.04fF
+C527 divider_0/prescaler_0/tspc_0/Z2 divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C528 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/Out 0.05fF
+C529 pll_full_1/divider_0/nor_0/Z1 pll_full_1/divider_0/and_0/B 0.78fF
+C530 pd_buffered_0/tapered_buf_3/a_160_n140# pd_buffered_0/tapered_buf_3/in 0.19fF
+C531 pd_buffered_0/tapered_buf_3/a_1650_0# pd_buffered_0/tapered_buf_3/a_210_n610# 2.89fF
+C532 pll_full_1/divider_0/tspc_2/Z3 pll_full_1/divider_0/tspc_2/Z4 0.65fF
+C533 pd_0/REF pd_0/tspc_r_0/Z1 0.17fF
+C534 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/UP 1.06fF
+C535 pll_full_1/pd_0/DOWN pll_full_1/pd_0/and_pd_0/Out1 0.12fF
+C536 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C537 cp_buffered_0/tapered_buf_1/a_160_n140# cp_buffered_0/tapered_buf_1/in 0.19fF
+C538 cp_buffered_0/tapered_buf_1/a_1650_0# cp_buffered_0/tapered_buf_1/a_210_n610# 2.89fF
+C539 pll_full_1/pd_0/tspc_r_0/z5 pll_full_1/ref 0.04fF
+C540 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/nor_1/B 0.35fF
+C541 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/vco 0.11fF
+C542 divider_2/nor_1/B divider_2/tspc_0/Q 0.22fF
+C543 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Q 0.04fF
+C544 filter_0/a_4216_n2998# filter_0/v 0.36fF
+C545 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/and_0/B 0.29fF
+C546 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z2 0.25fF
+C547 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C548 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Z4 0.08fF
+C549 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/D 0.03fF
+C550 divider_0/and_0/A divider_0/and_0/B 0.18fF
+C551 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/D 0.11fF
+C552 divider_1/tspc_2/a_630_n680# divider_1/nor_0/B 0.35fF
+C553 divider_1/prescaler_0/tspc_1/Q divider_1/clk 0.60fF
+C554 ro_complete_0/a1 ro_complete_0/cbank_1/v 0.05fF
+C555 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C556 pll_full_1/ro_complete_0/a5 pll_full_1/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C557 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/Z2 0.14fF
+C558 ro_complete_buffered_0/tapered_buf_5/a_n10_n140# ro_complete_buffered_0/tapered_buf_5/in 0.04fF
+C559 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C560 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.12fF
+C561 ro_complete_buffered_0/tapered_buf_0/a_160_n140# ro_complete_buffered_0/tapered_buf_0/a_580_0# 0.35fF
+C562 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/nor_1/B 0.06fF
+C563 pd_0/tspc_r_0/Qbar1 pd_0/R 0.30fF
+C564 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/and_0/OUT 0.05fF
+C565 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/z5 0.04fF
+C566 divider_0/prescaler_0/tspc_2/D divider_0/prescaler_0/nand_0/z1 0.24fF
+C567 divider_1/tspc_1/Z3 divider_1/tspc_1/a_630_n680# 0.05fF
+C568 divider_1/tspc_0/Z3 divider_1/tspc_0/Z4 0.65fF
+C569 divider_1/prescaler_0/m1_2700_2190# divider_1/prescaler_0/tspc_1/Q 0.38fF
+C570 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C571 pll_full_1/ro_complete_0/a1 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
+C572 pd_buffered_0/tapered_buf_2/a_580_0# pd_buffered_0/tapered_buf_2/a_1650_0# 1.27fF
+C573 divider_2/and_0/OUT divider_2/and_0/out1 0.31fF
+C574 ro_complete_buffered_0/tapered_buf_6/a_4670_0# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 29.21fF
+C575 ro_complete_buffered_0/tapered_buf_6/a_n10_230# ro_complete_buffered_0/tapered_buf_6/a_160_230# 0.09fF
+C576 divider_0/tspc_0/Q divider_0/tspc_1/Z3 0.45fF
+C577 ro_complete_buffered_0/tapered_buf_1/a_1650_0# ro_complete_buffered_0/tapered_buf_1/a_4670_0# 4.78fF
+C578 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C579 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/DOWN 0.07fF
+C580 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Z4 0.12fF
+C581 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C582 ro_complete_buffered_0/tapered_buf_2/a_160_n140# ro_complete_buffered_0/tapered_buf_2/in 0.19fF
+C583 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z2 0.14fF
+C584 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z3 0.05fF
+C585 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.32fF
+C586 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/vco 0.01fF
+C587 divider_2/mc2 divider_2/nor_0/B 0.15fF
+C588 divider_0/prescaler_0/tspc_2/D divider_0/clk 0.26fF
+C589 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/v 1.30fF
+C590 divider_2/tspc_1/Z1 divider_2/tspc_1/Z3 0.06fF
+C591 divider_2/tspc_0/a_630_n680# divider_2/tspc_0/Z4 0.12fF
+C592 divider_2/tspc_0/Z3 divider_2/nor_1/A 0.38fF
+C593 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C594 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.09fF
+C595 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/R 0.27fF
+C596 divider_2/nor_0/B divider_2/and_0/B 0.29fF
+C597 ro_complete_buffered_0/tapered_buf_7/a_580_0# ro_complete_buffered_0/tapered_buf_7/a_1650_0# 1.27fF
+C598 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/and_0/B 0.01fF
+C599 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Q 0.15fF
+C600 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C601 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Out1 0.12fF
+C602 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/UP 0.21fF
+C603 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Z4 0.02fF
+C604 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/B 0.18fF
+C605 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.00fF
+C606 pd_0/tspc_r_1/Z2 pd_0/tspc_r_1/Z4 0.14fF
+C607 pll_full_1/filter_0/a_4216_n5230# pll_full_1/vco 1.58fF
+C608 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z3 0.06fF
+C609 pll_full_0/divider_0/nor_0/B pll_full_0/div 0.27fF
+C610 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/z5 0.11fF
+C611 divider_1/tspc_0/Q divider_1/tspc_1/Z2 0.14fF
+C612 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Z4 0.36fF
+C613 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_580_0# 0.84fF
+C614 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.05fF
+C615 ro_complete_0/a3 ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C616 pll_full_1/ro_complete_0/cbank_0/switch_4/vin pll_full_1/ro_complete_0/a0 0.13fF
+C617 divider_1/prescaler_0/tspc_2/Z4 divider_1/clk 0.12fF
+C618 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/pd_0/tspc_r_1/z5 0.04fF
+C619 divider_2/prescaler_0/tspc_2/Z2 divider_2/and_0/OUT 0.05fF
+C620 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/nand_0/z1 0.07fF
+C621 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C622 cp_buffered_0/tapered_buf_2/a_n10_n140# cp_buffered_0/tapered_buf_2/in 0.04fF
+C623 pd_buffered_0/tapered_buf_3/a_210_n610# pd_buffered_0/pd_0/REF 26.29fF
+C624 pd_buffered_0/tapered_buf_2/a_210_n610# pd_buffered_0/pd_0/DIV 26.29fF
+C625 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C626 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C627 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C628 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/D 0.05fF
+C629 pll_full_1/pd_0/and_pd_0/Out1 pll_full_1/pd_0/UP 0.33fF
+C630 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Q 0.51fF
+C631 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Z2 0.01fF
+C632 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.05fF
+C633 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.08fF
+C634 divider_1/tspc_0/Z2 divider_1/nor_1/A 0.23fF
+C635 divider_1/prescaler_0/tspc_1/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
+C636 divider_1/mc2 divider_1/and_0/B 0.20fF
+C637 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/v 1.30fF
+C638 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/Z4 0.12fF
+C639 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C640 divider_2/tspc_1/Q divider_2/tspc_2/Z2 0.14fF
+C641 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/tspc_0/D 0.32fF
+C642 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/clk 0.01fF
+C643 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_0/Q 0.14fF
+C644 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/vco 0.01fF
+C645 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV 0.51fF
+C646 pd_buffered_0/tapered_buf_1/a_160_230# pd_buffered_0/tapered_buf_1/a_580_0# 0.02fF
+C647 divider_0/mc2 divider_0/and_0/out1 0.06fF
+C648 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_4670_0# 29.21fF
+C649 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.11fF
+C650 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C651 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/DOWN 0.03fF
+C652 divider_0/tspc_1/Q divider_0/tspc_2/Z4 0.15fF
+C653 divider_0/prescaler_0/tspc_1/Z3 divider_0/clk 0.45fF
+C654 ro_complete_buffered_0/tapered_buf_2/a_160_n140# ro_complete_buffered_0/tapered_buf_2/a_210_n610# 0.22fF
+C655 cp_buffered_0/tapered_buf_0/a_n10_n140# cp_buffered_0/tapered_buf_0/in 0.04fF
+C656 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z2 0.20fF
+C657 divider_2/tspc_0/Z2 divider_2/prescaler_0/Out 0.11fF
+C658 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Z4 0.65fF
+C659 ro_complete_buffered_0/tapered_buf_4/a_1650_0# ro_complete_buffered_0/tapered_buf_4/a_4670_0# 4.78fF
+C660 pll_full_1/ro_complete_0/cbank_2/switch_4/vin pll_full_1/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C661 divider_2/tspc_2/Z1 divider_2/tspc_2/Z3 0.06fF
+C662 divider_2/nor_0/B divider_2/Out 0.22fF
+C663 divider_0/nor_0/Z1 divider_0/nor_0/B 0.06fF
+C664 pll_full_1/divider_0/and_0/OUT pll_full_1/div 0.01fF
+C665 pll_full_1/divider_0/prescaler_0/tspc_0/D pll_full_1/divider_0/prescaler_0/nand_1/z1 0.21fF
+C666 cp_buffered_0/tapered_buf_2/a_210_n610# cp_buffered_0/tapered_buf_2/a_580_0# 0.84fF
+C667 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/and_pd_0/Out1 0.05fF
+C668 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/Qbar 0.01fF
+C669 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/R 0.27fF
+C670 divider_0/tspc_0/a_630_n680# divider_0/nor_1/A 0.35fF
+C671 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C672 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/UP 0.06fF
+C673 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C674 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/nor_1/B 1.21fF
+C675 divider_0/tspc_2/Z2 divider_0/tspc_2/Z4 0.36fF
+C676 divider_0/tspc_2/Z3 divider_0/Out 0.05fF
+C677 pd_0/tspc_r_0/Z4 pd_0/tspc_r_1/Z4 0.02fF
+C678 pd_0/DIV pd_0/tspc_r_1/Z1 0.17fF
+C679 pd_0/tspc_r_1/Qbar1 pd_0/DOWN 0.11fF
+C680 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C681 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C682 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
+C683 divider_1/tspc_1/Q divider_1/tspc_2/a_630_n680# 0.01fF
+C684 pll_full_1/ro_complete_0/cbank_1/switch_1/vin pll_full_1/vco 1.46fF
+C685 divider_2/tspc_1/Z2 divider_2/tspc_1/Z4 0.36fF
+C686 divider_2/tspc_1/Z3 divider_2/tspc_1/Q 0.05fF
+C687 divider_2/nor_1/A divider_2/tspc_0/Z4 0.21fF
+C688 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z3 0.05fF
+C689 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Z4 0.08fF
+C690 divider_1/nor_1/B divider_1/tspc_0/Q 0.22fF
+C691 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C692 ro_complete_buffered_0/tapered_buf_0/a_160_230# ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.17fF
+C693 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/a_n10_230# 0.02fF
+C694 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
+C695 divider_0/prescaler_0/m1_2700_2190# divider_0/and_0/OUT 0.14fF
+C696 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/and_0/OUT 0.14fF
+C697 pll_full_0/divider_0/prescaler_0/Out pll_full_0/vco 0.51fF
+C698 divider_1/tspc_0/Q divider_1/tspc_1/Z4 0.15fF
+C699 ro_complete_buffered_0/tapered_buf_2/a_1650_0# ro_complete_buffered_0/tapered_buf_2/a_580_0# 1.27fF
+C700 pll_full_1/ro_complete_0/cbank_2/switch_1/vin pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C701 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z3 0.11fF
+C702 divider_1/and_0/OUT divider_1/and_0/Z1 0.04fF
+C703 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z2 0.01fF
+C704 divider_1/prescaler_0/tspc_2/Q divider_1/clk 0.05fF
+C705 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C706 pll_full_0/pd_0/tspc_r_1/Qbar pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF
+C707 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C708 divider_0/and_0/OUT divider_0/prescaler_0/tspc_2/Q 0.04fF
+C709 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/B 0.08fF
+C710 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.20fF
+C711 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.09fF
+C712 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/vco 0.12fF
+C713 ro_complete_0/a2 ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C714 divider_2/tspc_0/Q divider_2/tspc_1/a_630_n680# 0.01fF
+C715 divider_1/and_0/out1 divider_1/and_0/B 0.18fF
+C716 ro_complete_buffered_0/tapered_buf_6/a_n10_230# ro_complete_buffered_0/tapered_buf_6/a_n10_n140# 0.01fF
+C717 pd_buffered_0/tapered_buf_2/a_1650_0# pd_buffered_0/tapered_buf_2/a_4670_0# 4.78fF
+C718 pd_buffered_0/tapered_buf_2/a_160_n140# pd_buffered_0/tapered_buf_2/a_160_230# 0.17fF
+C719 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z2 0.71fF
+C720 ro_complete_buffered_0/tapered_buf_1/a_580_0# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.35fF
+C721 cp_buffered_0/cp_0/down cp_buffered_0/cp_0/upbar 0.02fF
+C722 pll_full_1/pd_0/DOWN pll_full_1/pd_0/tspc_r_0/Qbar 0.02fF
+C723 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z2 1.07fF
+C724 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Qbar1 0.38fF
+C725 divider_1/mc2 divider_1/nor_1/A 0.04fF
+C726 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/pd_0/R 0.30fF
+C727 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/B 0.31fF
+C728 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.22fF
+C729 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/tspc_0/D 0.04fF
+C730 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z1 0.00fF
+C731 divider_1/prescaler_0/tspc_2/Z3 divider_1/prescaler_0/tspc_2/Q 0.05fF
+C732 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C733 pll_full_1/ro_complete_0/a4 pll_full_1/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C734 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_1/a_630_n680# 0.05fF
+C735 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/nor_1/B 0.03fF
+C736 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C737 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C738 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Z1 0.09fF
+C739 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_1/z5 0.02fF
+C740 divider_2/prescaler_0/Out divider_2/clk 0.51fF
+C741 ro_complete_buffered_0/tapered_buf_7/a_1650_0# ro_complete_buffered_0/tapered_buf_7/a_4670_0# 4.78fF
+C742 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_160_230# 0.17fF
+C743 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C744 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C745 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_1/a_160_n140# 0.19fF
+C746 io_clamp_low[0] io_clamp_high[0] 0.53fF
+C747 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
+C748 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C749 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/a3 0.09fF
+C750 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z1 0.06fF
+C751 divider_1/prescaler_0/tspc_0/Z2 divider_1/and_0/OUT 0.06fF
+C752 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z4 0.00fF
+C753 divider_2/prescaler_0/Out divider_2/prescaler_0/m1_2700_2190# 0.11fF
+C754 ro_complete_0/a5 ro_complete_0/cbank_1/v 0.10fF
+C755 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/a0 0.09fF
+C756 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C757 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C758 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 0.22fF
+C759 ro_complete_buffered_0/tapered_buf_5/a_580_0# ro_complete_buffered_0/tapered_buf_5/a_160_230# 0.02fF
+C760 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/ro_complete_0/a2 26.29fF
+C761 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/and_0/OUT 0.06fF
+C762 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C763 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.11fF
+C764 pll_full_1/ro_complete_0/cbank_1/switch_4/vin pll_full_1/vco 1.46fF
+C765 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/Q 0.20fF
+C766 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/D 0.09fF
+C767 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/Out 0.04fF
+C768 pll_full_1/divider_0/and_0/out1 pll_full_1/divider_0/and_0/A 0.01fF
+C769 pll_full_1/divider_0/tspc_0/Z3 pll_full_1/divider_0/tspc_0/Q 0.05fF
+C770 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
+C771 cp_buffered_0/tapered_buf_2/a_1650_0# cp_buffered_0/tapered_buf_2/a_580_0# 1.27fF
+C772 pll_full_0/ro_complete_0/cbank_0/switch_5/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C773 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.12fF
+C774 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 1.07fF
+C775 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/vco 0.01fF
+C776 divider_1/prescaler_0/tspc_0/Z1 divider_1/prescaler_0/tspc_0/Z2 1.07fF
+C777 divider_0/prescaler_0/tspc_2/Z4 divider_0/prescaler_0/tspc_2/D 0.11fF
+C778 divider_0/prescaler_0/tspc_1/Z3 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C779 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C780 pll_full_1/ro_complete_0/a5 pll_full_1/ro_complete_0/cbank_2/v 0.08fF
+C781 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C782 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/vco 0.01fF
+C783 divider_2/prescaler_0/tspc_1/Q divider_2/prescaler_0/nand_1/z1 0.22fF
+C784 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/tspc_0/D 0.04fF
+C785 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/ro_complete_0/a4 26.29fF
+C786 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C787 pd_buffered_0/tapered_buf_1/a_210_n610# pd_buffered_0/tapered_buf_1/a_1650_0# 2.89fF
+C788 divider_1/tspc_0/Z1 divider_1/nor_1/A 0.03fF
+C789 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C790 pll_full_0/ro_complete_0/cbank_2/v pll_full_0/vco 1.36fF
+C791 divider_0/prescaler_0/tspc_2/Z3 divider_0/clk 0.45fF
+C792 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C793 divider_2/tspc_0/Z1 divider_2/nor_1/A 0.03fF
+C794 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z3 0.05fF
+C795 pll_full_1/ro_complete_0/cbank_2/switch_4/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
+C796 divider_2/tspc_2/Z1 divider_2/tspc_2/Z4 0.00fF
+C797 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a3 2.04fF
+C798 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R 0.36fF
+C799 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z4 0.20fF
+C800 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C801 pd_buffered_0/pd_0/tspc_r_1/Z1 pd_buffered_0/pd_0/tspc_r_1/Z2 0.71fF
+C802 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z2 0.25fF
+C803 pll_full_1/pd_0/tspc_r_0/Z4 pll_full_1/ref 0.02fF
+C804 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/a_630_n680# 0.35fF
+C805 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.91fF
+C806 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C807 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_0/B 0.06fF
+C808 pd_0/tspc_r_0/z5 pd_0/tspc_r_1/z5 0.02fF
+C809 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z2 0.25fF
+C810 io_clamp_high[2] io_analog[6] 0.53fF
+C811 pll_full_1/pd_0/tspc_r_0/Qbar pll_full_1/pd_0/UP 0.21fF
+C812 divider_2/mc2 divider_2/and_0/B 0.20fF
+C813 divider_1/mc2 divider_1/and_0/OUT 0.05fF
+C814 divider_1/nor_0/Z1 divider_1/nor_0/B 0.06fF
+C815 ro_complete_0/a2 ro_complete_0/cbank_1/v 0.05fF
+C816 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z2 0.19fF
+C817 divider_1/tspc_1/Q divider_1/nor_0/B 0.22fF
+C818 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_2/Q 0.19fF
+C819 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/clk 0.01fF
+C820 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/tspc_r_1/Qbar 0.01fF
+C821 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z4 0.12fF
+C822 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z2 1.07fF
+C823 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_1/Z4 0.36fF
+C824 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_1/Q 0.05fF
+C825 pd_buffered_0/tapered_buf_3/a_n10_230# pd_buffered_0/tapered_buf_3/in 0.02fF
+C826 divider_0/mc2 divider_0/nor_1/A 0.04fF
+C827 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/a0 3.46fF
+C828 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_580_0# 0.84fF
+C829 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.05fF
+C830 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C831 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C832 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C833 divider_2/nor_1/B divider_2/nor_0/Z1 0.18fF
+C834 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_2/D 0.16fF
+C835 cp_buffered_0/tapered_buf_1/a_n10_230# cp_buffered_0/tapered_buf_1/in 0.02fF
+C836 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/a_630_n680# 0.01fF
+C837 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C838 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_2/D 0.16fF
+C839 pll_full_0/ro_complete_0/cbank_1/switch_2/vin pll_full_0/vco 1.46fF
+C840 ro_complete_buffered_0/tapered_buf_2/a_4670_0# ro_complete_buffered_0/tapered_buf_2/a_210_n610# 29.21fF
+C841 pd_0/DOWN pd_0/UP 0.46fF
+C842 divider_0/and_0/B divider_0/and_0/Z1 0.07fF
+C843 ro_complete_buffered_0/tapered_buf_3/a_1650_0# ro_complete_buffered_0/tapered_buf_3/a_580_0# 1.27fF
+C844 ro_complete_0/a0 ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C845 ro_complete_0/cbank_0/v ro_complete_0/cbank_1/v 1.27fF
+C846 divider_2/nor_1/Z1 divider_2/and_0/B 0.18fF
+C847 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z4 0.28fF
+C848 divider_1/tspc_2/a_630_n680# divider_1/Out 0.04fF
+C849 divider_1/nor_0/B divider_1/tspc_2/Z2 0.40fF
+C850 divider_1/prescaler_0/tspc_0/D divider_1/clk 0.29fF
+C851 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C852 divider_0/tspc_0/Z3 divider_0/tspc_0/Q 0.05fF
+C853 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z1 0.09fF
+C854 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z2 0.19fF
+C855 divider_0/mc2 divider_0/nor_0/B 0.15fF
+C856 ro_complete_buffered_0/tapered_buf_1/a_n10_n140# ro_complete_buffered_0/tapered_buf_1/in 0.04fF
+C857 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C858 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C859 divider_2/nor_1/B divider_2/tspc_1/Z2 0.30fF
+C860 divider_1/prescaler_0/Out divider_1/tspc_0/Z2 0.11fF
+C861 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/a_630_n680# 0.05fF
+C862 cp_buffered_0/tapered_buf_0/a_160_n140# cp_buffered_0/tapered_buf_0/a_210_n610# 0.22fF
+C863 cp_buffered_0/tapered_buf_0/a_580_0# cp_buffered_0/tapered_buf_0/a_160_230# 0.02fF
+C864 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C865 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z3 0.33fF
+C866 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Q 0.91fF
+C867 pll_full_1/ro_complete_0/cbank_0/v pll_full_1/ro_complete_0/cbank_2/v 0.04fF
+C868 pd_buffered_0/tapered_buf_2/a_580_0# pd_buffered_0/tapered_buf_2/a_210_n610# 0.84fF
+C869 pd_buffered_0/tapered_buf_2/a_160_n140# pd_buffered_0/tapered_buf_2/a_n10_n140# 0.05fF
+C870 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/pd_0/tspc_r_1/z5 0.20fF
+C871 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/tspc_0/Q 0.01fF
+C872 cp_buffered_0/tapered_buf_2/a_210_n610# cp_buffered_0/tapered_buf_2/a_160_n140# 0.22fF
+C873 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/R 0.03fF
+C874 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C875 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/Out 0.05fF
+C876 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z2 0.01fF
+C877 cp_buffered_0/cp_0/a_1710_n2840# cp_buffered_0/cp_0/upbar 0.29fF
+C878 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z3 0.16fF
+C879 pll_full_0/ro_complete_0/cbank_2/switch_2/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C880 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C881 divider_0/tspc_2/a_630_n680# divider_0/nor_0/B 0.35fF
+C882 divider_0/prescaler_0/tspc_1/Q divider_0/clk 0.60fF
+C883 filter_0/a_4216_n5230# filter_0/v 0.91fF
+C884 pll_full_0/divider_0/prescaler_0/tspc_2/Q pll_full_0/divider_0/prescaler_0/nand_1/z1 0.01fF
+C885 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/vco 0.11fF
+C886 pll_full_1/ro_complete_0/cbank_1/switch_3/vin pll_full_1/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C887 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/nor_1/B 0.38fF
+C888 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/Z1 0.00fF
+C889 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C890 pll_full_1/ro_complete_0/a2 pll_full_1/vco 0.11fF
+C891 pd_buffered_0/tapered_buf_3/a_160_n140# pd_buffered_0/tapered_buf_3/a_580_0# 0.35fF
+C892 divider_0/nor_0/Z1 divider_0/and_0/B 0.78fF
+C893 ro_complete_buffered_0/tapered_buf_7/a_580_0# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 0.84fF
+C894 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_n10_n140# 0.05fF
+C895 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/tspc_2/Z3 0.05fF
+C896 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z1 0.03fF
+C897 pd_buffered_0/pd_0/tspc_r_0/z5 pd_buffered_0/pd_0/UP 0.03fF
+C898 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/a1 0.14fF
+C899 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/Z3 0.33fF
+C900 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C901 cp_buffered_0/tapered_buf_1/a_160_n140# cp_buffered_0/tapered_buf_1/a_580_0# 0.35fF
+C902 divider_2/nor_1/B divider_2/and_0/A 0.26fF
+C903 pd_0/DOWN pd_0/and_pd_0/Out1 0.12fF
+C904 pd_0/tspc_r_0/Qbar pd_0/UP 0.21fF
+C905 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/divider_0/tspc_2/Z4 0.65fF
+C906 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C907 divider_2/tspc_0/Z2 divider_2/tspc_0/Z3 0.16fF
+C908 divider_1/and_0/OUT divider_1/and_0/out1 0.31fF
+C909 divider_0/prescaler_0/Out divider_0/tspc_0/a_630_n680# 0.01fF
+C910 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/a_740_n680# 0.08fF
+C911 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/in 0.19fF
+C912 ro_complete_buffered_0/tapered_buf_5/a_1650_0# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 2.89fF
+C913 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar1 0.11fF
+C914 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Q 0.04fF
+C915 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C916 pll_full_1/ro_complete_0/cbank_1/switch_0/vin pll_full_1/vco 1.58fF
+C917 pd_buffered_0/tapered_buf_0/a_210_n610# pd_buffered_0/tapered_buf_0/out 26.29fF
+C918 pd_buffered_0/tapered_buf_1/a_160_n140# pd_buffered_0/tapered_buf_1/a_n10_n140# 0.05fF
+C919 pd_buffered_0/pd_0/and_pd_0/Z1 pd_buffered_0/pd_0/UP 0.06fF
+C920 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C921 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C922 divider_2/mc2 divider_2/nor_1/A 0.04fF
+C923 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C924 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/R 0.29fF
+C925 divider_1/tspc_1/Z1 divider_1/tspc_1/Z3 0.06fF
+C926 divider_1/tspc_0/Z3 divider_1/nor_1/A 0.38fF
+C927 ro_complete_buffered_0/tapered_buf_2/a_n10_230# ro_complete_buffered_0/tapered_buf_2/in 0.02fF
+C928 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/DOWN 0.02fF
+C929 divider_2/tspc_0/Q divider_2/tspc_0/Z3 0.05fF
+C930 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z3 0.06fF
+C931 divider_1/nor_0/B divider_1/and_0/B 0.29fF
+C932 divider_2/nor_1/A divider_2/and_0/B 0.08fF
+C933 divider_2/prescaler_0/tspc_2/Q divider_2/prescaler_0/nand_1/z1 0.01fF
+C934 divider_2/prescaler_0/tspc_2/Z2 divider_2/clk 0.11fF
+C935 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/Z3 0.65fF
+C936 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/prescaler_0/tspc_2/D 0.03fF
+C937 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C938 ro_complete_buffered_0/tapered_buf_1/a_210_n610# ro_complete_buffered_0/tapered_buf_1/a_160_n140# 0.22fF
+C939 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a4 0.12fF
+C940 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C941 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.08fF
+C942 pll_full_0/ro_complete_0/a1 pll_full_0/ro_complete_0/cbank_2/v 0.05fF
+C943 pll_full_0/pd_0/tspc_r_1/Z1 pll_full_0/div 0.17fF
+C944 divider_1/tspc_0/a_630_n680# divider_1/nor_1/A 0.35fF
+C945 divider_0/tspc_1/a_630_n680# divider_0/nor_1/B 0.35fF
+C946 divider_2/nor_1/B divider_2/tspc_1/Z4 0.21fF
+C947 divider_0/nor_1/A divider_0/tspc_0/Z1 0.03fF
+C948 divider_0/prescaler_0/tspc_2/Z4 divider_0/clk 0.12fF
+C949 divider_1/prescaler_0/tspc_2/Z2 divider_1/and_0/OUT 0.05fF
+C950 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C951 divider_0/prescaler_0/tspc_0/Z1 divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C952 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 0.22fF
+C953 ro_complete_buffered_0/tapered_buf_4/a_580_0# ro_complete_buffered_0/tapered_buf_4/a_160_230# 0.02fF
+C954 pll_full_1/ro_complete_0/cbank_2/switch_0/vin pll_full_1/ro_complete_0/cbank_2/v 1.45fF
+C955 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/and_pd_0/Out1 0.05fF
+C956 divider_2/tspc_0/a_630_n680# divider_2/nor_1/A 0.35fF
+C957 pll_full_0/pd_0/R pll_full_0/pd_0/UP 0.46fF
+C958 divider_2/tspc_2/Z3 divider_2/tspc_2/Z4 0.65fF
+C959 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/tspc_r_1/z5 0.20fF
+C960 divider_0/nor_1/Z1 divider_0/nor_1/B 0.06fF
+C961 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C962 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.33fF
+C963 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.09fF
+C964 divider_0/tspc_1/Z1 divider_0/tspc_1/Z3 0.06fF
+C965 io_clamp_low[1] io_analog[5] 0.53fF
+C966 pd_0/tspc_r_0/Qbar pd_0/and_pd_0/Out1 0.05fF
+C967 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/Qbar 0.01fF
+C968 pd_0/tspc_r_1/Z3 pd_0/R 0.27fF
+C969 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/and_0/B 0.01fF
+C970 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/R 0.21fF
+C971 divider_1/tspc_1/Q divider_1/tspc_2/Z2 0.14fF
+C972 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/tspc_0/D 0.32fF
+C973 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/clk 0.01fF
+C974 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C975 pll_full_1/ro_complete_0/cbank_0/switch_2/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
+C976 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C977 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/Z2 0.36fF
+C978 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/and_pd_0/Z1 0.02fF
+C979 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z3 0.16fF
+C980 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/pd_0/tspc_r_1/Z2 0.14fF
+C981 pll_full_1/div pll_full_1/vco 2.26fF
+C982 pd_buffered_0/tapered_buf_0/a_160_230# pd_buffered_0/tapered_buf_0/a_160_n140# 0.17fF
+C983 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/and_pd_0/Z1 0.18fF
+C984 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/a0 0.13fF
+C985 pll_full_0/pd_0/R pll_full_0/div 0.51fF
+C986 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_6/in 0.10fF
+C987 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/a0 0.09fF
+C988 cp_buffered_0/cp_0/upbar cp_buffered_0/tapered_buf_0/a_210_n610# 26.29fF
+C989 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/nand_0/z1 0.07fF
+C990 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C991 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/nand_0/z1 0.07fF
+C992 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C993 divider_2/tspc_0/Z2 divider_2/tspc_0/Z4 0.36fF
+C994 divider_1/tspc_2/Z1 divider_1/tspc_2/Z3 0.06fF
+C995 divider_1/nor_0/B divider_1/Out 0.22fF
+C996 divider_0/tspc_0/Z3 divider_0/tspc_0/a_630_n680# 0.05fF
+C997 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Q 0.55fF
+C998 pll_full_1/ro_complete_0/cbank_1/switch_5/vin pll_full_1/vco 1.46fF
+C999 divider_1/nor_1/B divider_1/tspc_1/Z2 0.30fF
+C1000 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/Z1 0.00fF
+C1001 pd_buffered_0/tapered_buf_3/in pd_buffered_0/pd_0/DIV 0.02fF
+C1002 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/nor_1/B 0.18fF
+C1003 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z4 0.12fF
+C1004 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C1005 cp_buffered_0/tapered_buf_0/a_160_n140# cp_buffered_0/tapered_buf_0/in 0.19fF
+C1006 cp_buffered_0/tapered_buf_0/a_1650_0# cp_buffered_0/tapered_buf_0/a_210_n610# 2.89fF
+C1007 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_0/Q 0.14fF
+C1008 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/vco 0.01fF
+C1009 divider_2/mc2 divider_2/and_0/OUT 0.05fF
+C1010 divider_0/tspc_1/Q divider_0/tspc_2/a_630_n680# 0.01fF
+C1011 divider_0/prescaler_0/m1_2700_2190# divider_0/clk 0.01fF
+C1012 pll_full_0/cp_0/upbar pll_full_0/cp_0/down 0.02fF
+C1013 divider_1/tspc_1/Z2 divider_1/tspc_1/Z4 0.36fF
+C1014 divider_1/tspc_1/Z3 divider_1/tspc_1/Q 0.05fF
+C1015 divider_1/nor_1/A divider_1/tspc_0/Z4 0.21fF
+C1016 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z3 0.05fF
+C1017 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Z4 0.08fF
+C1018 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1019 pd_buffered_0/tapered_buf_2/a_4670_0# pd_buffered_0/tapered_buf_2/a_210_n610# 29.21fF
+C1020 pd_buffered_0/tapered_buf_2/a_n10_230# pd_buffered_0/tapered_buf_2/a_160_230# 0.09fF
+C1021 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z1 0.01fF
+C1022 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_0/Q 0.22fF
+C1023 divider_2/and_0/OUT divider_2/and_0/B 0.01fF
+C1024 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z4 0.12fF
+C1025 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C1026 cp_buffered_0/tapered_buf_2/in cp_buffered_0/tapered_buf_2/a_160_n140# 0.19fF
+C1027 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Qbar1 0.12fF
+C1028 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C1029 divider_0/nor_1/B divider_0/tspc_1/Z2 0.30fF
+C1030 pll_full_0/divider_0/and_0/OUT pll_full_0/div 0.01fF
+C1031 pll_full_0/divider_0/prescaler_0/tspc_0/D pll_full_0/divider_0/prescaler_0/nand_1/z1 0.21fF
+C1032 divider_0/and_0/OUT divider_0/and_0/Z1 0.04fF
+C1033 divider_0/tspc_2/a_630_n680# divider_0/tspc_2/Z2 0.01fF
+C1034 divider_0/prescaler_0/tspc_2/Q divider_0/clk 0.05fF
+C1035 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1036 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# ro_complete_buffered_0/tapered_buf_3/in 0.04fF
+C1037 divider_2/tspc_1/Z2 divider_2/tspc_1/a_630_n680# 0.01fF
+C1038 divider_2/prescaler_0/tspc_2/a_740_n680# divider_2/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C1039 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1040 pll_full_1/divider_0/nor_1/Z1 pll_full_1/divider_0/and_0/A 0.80fF
+C1041 pll_full_1/ro_complete_0/cbank_2/switch_5/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
+C1042 pd_buffered_0/tapered_buf_3/a_580_0# pd_buffered_0/tapered_buf_3/a_1650_0# 1.27fF
+C1043 ro_complete_buffered_0/tapered_buf_7/a_4670_0# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 29.21fF
+C1044 ro_complete_buffered_0/tapered_buf_7/a_n10_230# ro_complete_buffered_0/tapered_buf_7/a_160_230# 0.09fF
+C1045 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/tspc_2/Z4 0.12fF
+C1046 pll_full_1/divider_0/tspc_2/Z1 pll_full_1/divider_0/tspc_2/Z2 1.07fF
+C1047 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z3 0.38fF
+C1048 divider_1/nor_1/B divider_1/and_0/A 0.26fF
+C1049 divider_0/prescaler_0/tspc_0/Z3 divider_0/clk 0.64fF
+C1050 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
+C1051 pd_0/REF pd_0/tspc_r_0/Z3 0.65fF
+C1052 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 0.06fF
+C1053 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C1054 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1055 cp_buffered_0/tapered_buf_1/a_580_0# cp_buffered_0/tapered_buf_1/a_1650_0# 1.27fF
+C1056 pll_full_0/divider_0/nor_0/Z1 pll_full_0/divider_0/and_0/B 0.78fF
+C1057 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/vco 1.46fF
+C1058 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1059 pll_full_1/pd_0/tspc_r_1/Z2 pll_full_1/div 0.19fF
+C1060 divider_1/tspc_0/Q divider_1/tspc_1/a_630_n680# 0.01fF
+C1061 divider_1/prescaler_0/tspc_0/Z3 divider_1/clk 0.64fF
+C1062 divider_1/nor_0/Z1 divider_1/and_0/B 0.78fF
+C1063 divider_0/and_0/out1 divider_0/and_0/B 0.18fF
+C1064 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z2 1.07fF
+C1065 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1066 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/tspc_1/Z4 0.12fF
+C1067 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1068 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z4 0.28fF
+C1069 pll_full_1/divider_0/and_0/out1 pll_full_1/divider_0/and_0/Z1 0.36fF
+C1070 ro_complete_buffered_0/tapered_buf_0/a_1650_0# ro_complete_buffered_0/tapered_buf_0/a_580_0# 1.27fF
+C1071 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1072 ro_complete_buffered_0/ro_complete_0/cbank_0/v ro_complete_buffered_0/tapered_buf_6/in 1.27fF
+C1073 pll_full_1/pd_0/tspc_r_0/Z4 pll_full_1/pd_0/tspc_r_0/Z2 0.14fF
+C1074 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1075 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/ref 0.12fF
+C1076 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C1077 divider_0/prescaler_0/tspc_2/Z3 divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1078 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1079 divider_1/prescaler_0/tspc_0/Z2 divider_1/clk 0.11fF
+C1080 divider_2/tspc_0/Q divider_2/tspc_1/Z1 0.01fF
+C1081 divider_2/prescaler_0/tspc_1/Z1 divider_2/prescaler_0/tspc_1/Z4 0.00fF
+C1082 ro_complete_0/a0 ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1083 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1084 divider_2/prescaler_0/tspc_0/D divider_2/prescaler_0/nand_1/z1 0.21fF
+C1085 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1086 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/vco 0.11fF
+C1087 pd_buffered_0/tapered_buf_1/a_4670_0# pd_buffered_0/tapered_buf_1/a_1650_0# 4.78fF
+C1088 pd_buffered_0/pd_0/tspc_r_0/Z4 pd_buffered_0/pd_0/tspc_r_0/z5 0.04fF
+C1089 divider_1/nor_1/B divider_1/tspc_1/Z4 0.21fF
+C1090 divider_0/mc2 divider_0/and_0/B 0.20fF
+C1091 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1092 ro_complete_buffered_0/tapered_buf_6/a_n10_n140# ro_complete_buffered_0/tapered_buf_6/in 0.04fF
+C1093 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/pd_0/tspc_r_0/Z4 0.02fF
+C1094 divider_0/nor_1/Z1 divider_0/and_0/A 0.80fF
+C1095 cp_buffered_0/cp_0/a_10_n50# cp_buffered_0/cp_0/a_1710_0# 0.04fF
+C1096 pd_0/tspc_r_0/Z3 pd_0/UP 0.03fF
+C1097 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1098 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1099 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/Q 0.20fF
+C1100 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/D 0.09fF
+C1101 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/in 0.19fF
+C1102 ro_complete_buffered_0/tapered_buf_4/a_1650_0# ro_complete_buffered_0/tapered_buf_4/a_210_n610# 2.89fF
+C1103 divider_0/mc2 divider_0/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C1104 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/div 0.03fF
+C1105 pll_full_1/divider_0/and_0/OUT pll_full_1/vco 0.06fF
+C1106 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/UP 0.11fF
+C1107 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_630_n680# 0.12fF
+C1108 pll_full_0/ro_complete_0/a4 pll_full_0/ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C1109 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/pd_0/tspc_r_0/Z3 0.09fF
+C1110 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z4 0.12fF
+C1111 divider_0/prescaler_0/tspc_2/a_630_n680# divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1112 pll_full_1/pd_0/DOWN pll_full_1/pd_0/UP 4.58fF
+C1113 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/div 0.12fF
+C1114 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/a_630_n680# 0.05fF
+C1115 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/nor_1/B 0.03fF
+C1116 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.05fF
+C1117 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.08fF
+C1118 pd_0/DOWN pd_0/R 0.36fF
+C1119 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z4 0.20fF
+C1120 pd_0/DIV pd_0/tspc_r_1/z5 0.04fF
+C1121 pd_0/tspc_r_1/Z1 pd_0/tspc_r_1/Z2 0.71fF
+C1122 pll_full_0/ref pll_full_0/pd_0/DOWN 1.48fF
+C1123 divider_2/nor_1/B divider_2/tspc_2/Z4 0.02fF
+C1124 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_4670_0# 29.21fF
+C1125 ro_complete_buffered_0/tapered_buf_3/a_160_230# ro_complete_buffered_0/tapered_buf_3/a_n10_230# 0.09fF
+C1126 pll_full_1/ro_complete_0/cbank_0/switch_4/vin pll_full_1/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1127 divider_2/tspc_0/Z2 divider_2/tspc_0/Z1 1.07fF
+C1128 divider_1/prescaler_0/tspc_1/Q divider_1/prescaler_0/nand_1/z1 0.22fF
+C1129 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/tspc_0/D 0.04fF
+C1130 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/Qbar 0.21fF
+C1131 divider_2/tspc_1/a_630_n680# divider_2/tspc_1/Z4 0.12fF
+C1132 divider_2/prescaler_0/tspc_2/Z2 divider_2/prescaler_0/tspc_2/Z4 0.36fF
+C1133 divider_2/prescaler_0/tspc_0/Z1 divider_2/prescaler_0/tspc_0/D 0.03fF
+C1134 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/vco 0.64fF
+C1135 pd_buffered_0/tapered_buf_0/a_210_n610# pd_buffered_0/tapered_buf_0/a_580_0# 0.84fF
+C1136 pd_buffered_0/tapered_buf_0/a_n10_n140# pd_buffered_0/tapered_buf_0/a_160_n140# 0.05fF
+C1137 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1138 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C1139 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_1/Z1 0.08fF
+C1140 divider_0/prescaler_0/tspc_1/Z2 divider_0/and_0/OUT 0.06fF
+C1141 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1142 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/Qbar 0.01fF
+C1143 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/and_0/OUT 0.06fF
+C1144 pll_full_0/divider_0/prescaler_0/m1_2700_2190# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.38fF
+C1145 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.11fF
+C1146 pll_full_0/ro_complete_0/cbank_1/switch_4/vin pll_full_0/vco 1.46fF
+C1147 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/A 0.01fF
+C1148 pll_full_0/divider_0/tspc_0/Z3 pll_full_0/divider_0/tspc_0/Q 0.05fF
+C1149 pll_full_1/ro_complete_0/cbank_2/switch_1/vin pll_full_1/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1150 pll_full_1/ro_complete_0/cbank_2/switch_3/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
+C1151 divider_1/tspc_2/Z1 divider_1/tspc_2/Z4 0.00fF
+C1152 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/a_740_n680# 0.08fF
+C1153 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1154 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/and_0/A 0.01fF
+C1155 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z4 0.02fF
+C1156 ro_complete_buffered_0/tapered_buf_1/in gnd 0.04fF
+C1157 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1158 pd_0/REF pd_0/tspc_r_0/z5 0.04fF
+C1159 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1160 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_2/v 0.08fF
+C1161 pll_full_0/ro_complete_0/a0 pll_full_0/ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C1162 divider_1/prescaler_0/Out divider_1/tspc_0/Z3 0.45fF
+C1163 divider_0/tspc_1/Q divider_0/nor_0/B 0.22fF
+C1164 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1165 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/clk 0.01fF
+C1166 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/vco 0.01fF
+C1167 ro_complete_buffered_0/tapered_buf_2/a_n10_n140# ro_complete_buffered_0/tapered_buf_2/in 0.04fF
+C1168 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a1 0.14fF
+C1169 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z4 0.12fF
+C1170 divider_1/prescaler_0/tspc_2/Z1 divider_1/prescaler_0/tspc_2/Z2 1.07fF
+C1171 ro_complete_0/cbank_1/v ro_complete_0/cbank_2/v 1.36fF
+C1172 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z4 0.21fF
+C1173 ro_complete_buffered_0/tapered_buf_6/a_210_n610# ro_complete_buffered_0/tapered_buf_6/out 26.29fF
+C1174 pd_buffered_0/tapered_buf_2/a_n10_230# pd_buffered_0/tapered_buf_2/a_n10_n140# 0.01fF
+C1175 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z3 0.45fF
+C1176 pll_full_1/divider_0/tspc_0/a_630_n680# pll_full_1/divider_0/tspc_0/Q 0.04fF
+C1177 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/and_0/A 0.26fF
+C1178 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/DOWN 0.03fF
+C1179 pll_full_0/ro_complete_0/cbank_0/switch_1/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1180 divider_1/tspc_0/a_630_n680# divider_1/prescaler_0/Out 0.01fF
+C1181 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1182 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1183 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.22fF
+C1184 pll_full_0/ro_complete_0/cbank_2/switch_4/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1185 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_1/Q 0.13fF
+C1186 divider_0/tspc_2/a_630_n680# divider_0/Out 0.04fF
+C1187 divider_0/nor_0/B divider_0/tspc_2/Z2 0.40fF
+C1188 divider_0/prescaler_0/tspc_0/D divider_0/clk 0.29fF
+C1189 pd_0/tspc_r_0/Qbar pd_0/R 0.03fF
+C1190 ro_complete_0/a2 ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C1191 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1192 pll_full_1/ro_complete_0/cbank_1/switch_3/vin pll_full_1/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1193 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_1/Z4 0.02fF
+C1194 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1195 ro_complete_buffered_0/tapered_buf_7/a_n10_230# ro_complete_buffered_0/tapered_buf_7/a_n10_n140# 0.01fF
+C1196 pd_buffered_0/tapered_buf_3/a_1650_0# pd_buffered_0/tapered_buf_3/a_4670_0# 4.78fF
+C1197 pd_buffered_0/tapered_buf_3/a_160_n140# pd_buffered_0/tapered_buf_3/a_160_230# 0.17fF
+C1198 divider_2/and_0/out1 divider_2/and_0/A 0.01fF
+C1199 pll_full_1/divider_0/tspc_2/Z2 pll_full_1/divider_0/tspc_2/Z3 0.16fF
+C1200 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z4 0.22fF
+C1201 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C1202 divider_0/prescaler_0/tspc_0/Z4 divider_0/clk 0.12fF
+C1203 cp_buffered_0/tapered_buf_1/a_1650_0# cp_buffered_0/tapered_buf_1/a_4670_0# 4.78fF
+C1204 cp_buffered_0/tapered_buf_1/a_160_n140# cp_buffered_0/tapered_buf_1/a_160_230# 0.17fF
+C1205 divider_0/tspc_1/Z2 divider_0/tspc_1/Z4 0.36fF
+C1206 divider_0/tspc_1/Z3 divider_0/tspc_1/Q 0.05fF
+C1207 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/D 0.15fF
+C1208 divider_0/prescaler_0/tspc_1/Z1 divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1209 pll_full_0/divider_0/tspc_1/Z2 pll_full_0/divider_0/tspc_1/Z4 0.36fF
+C1210 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/tspc_1/Q 0.05fF
+C1211 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_1/Q 0.06fF
+C1212 pd_0/tspc_r_0/z5 pd_0/UP 0.03fF
+C1213 ro_complete_0/cbank_1/switch_2/vin ro_complete_0/cbank_1/v 1.30fF
+C1214 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Z4 0.20fF
+C1215 ro_complete_buffered_0/tapered_buf_5/a_n10_230# ro_complete_buffered_0/tapered_buf_5/in 0.02fF
+C1216 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_1/Z4 0.21fF
+C1217 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1218 pll_full_1/ro_complete_0/a0 pll_full_1/vco 0.11fF
+C1219 pll_full_1/divider_0/and_0/A pll_full_1/divider_0/and_0/B 0.18fF
+C1220 pd_buffered_0/tapered_buf_0/a_160_n140# pd_buffered_0/pd_0/UP 0.19fF
+C1221 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.36fF
+C1222 divider_0/nor_1/B divider_0/and_0/A 0.26fF
+C1223 pll_full_1/pd_0/tspc_r_0/z5 pll_full_1/pd_0/UP 0.03fF
+C1224 pd_0/and_pd_0/Z1 pd_0/UP 0.06fF
+C1225 ro_complete_0/a0 ro_complete_0/cbank_2/v 0.05fF
+C1226 divider_2/tspc_0/Q divider_2/tspc_1/Z3 0.45fF
+C1227 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 0.22fF
+C1228 ro_complete_buffered_0/tapered_buf_6/a_580_0# ro_complete_buffered_0/tapered_buf_6/a_160_230# 0.02fF
+C1229 pll_full_1/divider_0/prescaler_0/tspc_2/D pll_full_1/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1230 divider_0/prescaler_0/Out divider_0/nor_1/A 0.15fF
+C1231 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1232 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/a4 0.09fF
+C1233 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/a5 0.09fF
+C1234 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/R 0.61fF
+C1235 pll_full_0/ro_complete_0/cbank_0/v pll_full_0/ro_complete_0/cbank_2/v 0.04fF
+C1236 divider_1/prescaler_0/Out divider_1/tspc_0/Z4 0.12fF
+C1237 divider_0/nor_1/A divider_0/and_0/B 0.08fF
+C1238 divider_0/and_0/OUT divider_0/and_0/out1 0.31fF
+C1239 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.01fF
+C1240 pll_full_0/cp_0/a_1710_0# pll_full_0/pd_0/DOWN 0.04fF
+C1241 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Q 0.04fF
+C1242 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1243 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1244 pll_full_1/divider_0/prescaler_0/tspc_2/D pll_full_1/vco 0.26fF
+C1245 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/UP 0.03fF
+C1246 divider_1/nor_1/B divider_1/tspc_2/Z4 0.02fF
+C1247 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# ro_complete_buffered_0/tapered_buf_0/in 0.04fF
+C1248 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1249 pll_full_0/divider_0/tspc_1/Z3 pll_full_0/divider_0/nor_1/B 0.38fF
+C1250 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z1 0.00fF
+C1251 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.12fF
+C1252 pll_full_0/ro_complete_0/a2 pll_full_0/vco 0.11fF
+C1253 divider_0/nor_1/B divider_0/tspc_1/Z4 0.21fF
+C1254 pd_0/tspc_r_1/Qbar1 pd_0/tspc_r_1/z5 0.20fF
+C1255 io_clamp_high[0] io_analog[4] 0.53fF
+C1256 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/ref 0.65fF
+C1257 divider_1/tspc_0/Q divider_1/tspc_0/Z3 0.05fF
+C1258 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z3 0.06fF
+C1259 divider_0/nor_0/B divider_0/and_0/B 0.29fF
+C1260 pll_full_1/ref pll_full_1/pd_0/R 0.61fF
+C1261 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z3 0.05fF
+C1262 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z1 0.03fF
+C1263 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z3 0.25fF
+C1264 divider_2/tspc_0/Z2 divider_2/tspc_0/a_630_n680# 0.01fF
+C1265 divider_1/nor_1/A divider_1/and_0/B 0.08fF
+C1266 divider_1/prescaler_0/tspc_2/Q divider_1/prescaler_0/nand_1/z1 0.01fF
+C1267 divider_1/prescaler_0/tspc_2/Z2 divider_1/clk 0.11fF
+C1268 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# ro_complete_buffered_0/tapered_buf_3/a_n10_230# 0.01fF
+C1269 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/tapered_buf_2/a_580_0# 0.84fF
+C1270 ro_complete_0/a4 ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1271 pll_full_1/ro_complete_0/a5 pll_full_1/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1272 pll_full_1/ro_complete_0/cbank_0/switch_4/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
+C1273 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_580_0# 0.35fF
+C1274 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/Z3 0.45fF
+C1275 pll_full_1/ro_complete_0/a3 pll_full_1/vco 0.11fF
+C1276 divider_0/mc2 divider_0/and_0/OUT 0.05fF
+C1277 divider_1/tspc_0/a_630_n680# divider_1/tspc_0/Q 0.04fF
+C1278 divider_0/tspc_0/Z3 divider_0/tspc_0/Z1 0.06fF
+C1279 pd_buffered_0/tapered_buf_0/a_210_n610# pd_buffered_0/tapered_buf_0/a_4670_0# 29.21fF
+C1280 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/div 0.65fF
+C1281 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.01fF
+C1282 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z4 0.20fF
+C1283 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.04fF
+C1284 pll_full_0/ro_complete_0/cbank_1/switch_0/vin pll_full_0/vco 1.58fF
+C1285 divider_0/prescaler_0/tspc_2/Z2 divider_0/and_0/OUT 0.05fF
+C1286 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Q 0.04fF
+C1287 pd_0/and_pd_0/Out1 pd_0/and_pd_0/Z1 0.18fF
+C1288 divider_1/nor_1/Z1 divider_1/and_0/B 0.18fF
+C1289 divider_2/tspc_0/Q divider_2/tspc_0/a_630_n680# 0.04fF
+C1290 divider_1/tspc_2/Z3 divider_1/tspc_2/Z4 0.65fF
+C1291 ro_complete_0/a3 ro_complete_0/cbank_2/v 0.05fF
+C1292 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1293 pll_full_0/pd_0/DOWN pll_full_0/pd_0/tspc_r_1/z5 0.03fF
+C1294 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1295 divider_0/tspc_0/Q divider_0/tspc_1/a_630_n680# 0.01fF
+C1296 divider_0/prescaler_0/tspc_0/a_740_n680# divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1297 pd_buffered_0/tapered_buf_1/a_210_n610# pd_buffered_0/tapered_buf_1/a_4670_0# 29.21fF
+C1298 pd_buffered_0/tapered_buf_1/a_160_230# pd_buffered_0/tapered_buf_1/a_n10_230# 0.09fF
+C1299 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/z5 0.11fF
+C1300 divider_1/prescaler_0/tspc_0/Z4 divider_1/clk 0.12fF
+C1301 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1302 ro_complete_buffered_0/tapered_buf_2/a_160_n140# ro_complete_buffered_0/tapered_buf_2/a_160_230# 0.17fF
+C1303 cp_buffered_0/tapered_buf_0/a_n10_230# cp_buffered_0/tapered_buf_0/in 0.02fF
+C1304 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z3 0.65fF
+C1305 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/D 0.03fF
+C1306 divider_2/nor_1/B divider_2/tspc_1/a_630_n680# 0.35fF
+C1307 divider_0/tspc_1/Q divider_0/tspc_2/Z2 0.14fF
+C1308 divider_0/tspc_0/Z4 divider_0/tspc_0/Z1 0.00fF
+C1309 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/tspc_0/D 0.32fF
+C1310 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a1 0.14fF
+C1311 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z3 0.16fF
+C1312 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1313 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/div 0.65fF
+C1314 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_1/Z3 0.06fF
+C1315 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/Z2 0.11fF
+C1316 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1317 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z3 0.05fF
+C1318 divider_2/nor_0/B divider_2/tspc_2/Z1 0.03fF
+C1319 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/Z4 0.15fF
+C1320 divider_0/tspc_0/Z3 divider_0/nor_1/A 0.38fF
+C1321 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1322 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/a5 2.39fF
+C1323 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1324 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/Z1 0.09fF
+C1325 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z2 0.19fF
+C1326 pll_full_0/pd_0/tspc_r_1/Z4 pll_full_0/div 0.02fF
+C1327 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/Z1 0.00fF
+C1328 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Qbar1 0.38fF
+C1329 pll_full_0/ro_complete_0/cbank_2/switch_0/vin pll_full_0/ro_complete_0/cbank_2/v 1.45fF
+C1330 pd_0/DIV pd_0/tspc_r_1/Qbar1 0.12fF
+C1331 divider_0/tspc_2/Z1 divider_0/tspc_2/Z3 0.06fF
+C1332 divider_0/nor_0/B divider_0/Out 0.22fF
+C1333 ro_complete_0/a3 ro_complete_0/cbank_1/switch_2/vin 0.09fF
+C1334 divider_2/prescaler_0/tspc_0/Z2 divider_2/and_0/OUT 0.06fF
+C1335 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/clk 0.14fF
+C1336 divider_2/nor_0/Z1 divider_2/nor_0/B 0.06fF
+C1337 pll_full_1/divider_0/tspc_0/Z4 pll_full_1/divider_0/tspc_0/a_630_n680# 0.12fF
+C1338 cp_buffered_0/tapered_buf_2/a_n10_230# cp_buffered_0/tapered_buf_2/in 0.02fF
+C1339 pd_buffered_0/tapered_buf_3/a_580_0# pd_buffered_0/tapered_buf_3/a_210_n610# 0.84fF
+C1340 pd_buffered_0/tapered_buf_3/a_160_n140# pd_buffered_0/tapered_buf_3/a_n10_n140# 0.05fF
+C1341 pll_full_1/pd_0/tspc_r_1/Z4 pll_full_1/pd_0/tspc_r_1/z5 0.04fF
+C1342 pll_full_1/divider_0/tspc_2/Z2 pll_full_1/divider_0/tspc_2/Z4 0.36fF
+C1343 pll_full_1/divider_0/tspc_2/Z3 pll_full_1/div 0.05fF
+C1344 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_4670_0# 29.21fF
+C1345 ro_complete_buffered_0/tapered_buf_0/a_160_230# ro_complete_buffered_0/tapered_buf_0/a_n10_230# 0.09fF
+C1346 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.14fF
+C1347 pll_full_0/ro_complete_0/cbank_0/switch_2/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1348 divider_0/tspc_0/Z4 divider_0/nor_1/A 0.21fF
+C1349 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1350 cp_buffered_0/tapered_buf_1/a_580_0# cp_buffered_0/tapered_buf_1/a_210_n610# 0.84fF
+C1351 cp_buffered_0/tapered_buf_1/a_160_n140# cp_buffered_0/tapered_buf_1/a_n10_n140# 0.05fF
+C1352 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.03fF
+C1353 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/Z2 0.36fF
+C1354 pll_full_0/div pll_full_0/vco 2.26fF
+C1355 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z1 0.09fF
+C1356 ro_complete_buffered_0/tapered_buf_3/a_1650_0# ro_complete_buffered_0/tapered_buf_3/a_4670_0# 4.78fF
+C1357 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1358 divider_2/tspc_0/Z2 divider_2/nor_1/A 0.23fF
+C1359 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_0/Z2 0.16fF
+C1360 divider_1/and_0/OUT divider_1/and_0/B 0.01fF
+C1361 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1362 pll_full_1/ro_complete_0/a3 pll_full_1/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1363 pll_full_1/pd_0/tspc_r_1/Qbar1 pll_full_1/pd_0/DOWN 0.11fF
+C1364 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Out1 0.12fF
+C1365 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Z3 0.29fF
+C1366 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/D 0.03fF
+C1367 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1368 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z3 0.65fF
+C1369 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/a_740_n680# 0.19fF
+C1370 pd_0/tspc_r_0/Z3 pd_0/R 0.29fF
+C1371 cp_buffered_0/tapered_buf_0/a_160_n140# cp_buffered_0/tapered_buf_0/a_580_0# 0.35fF
+C1372 pll_full_1/pd_0/and_pd_0/Out1 pll_full_1/pd_0/R 0.33fF
+C1373 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/pd_0/tspc_r_0/Qbar 0.01fF
+C1374 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Q 0.55fF
+C1375 pll_full_0/ro_complete_0/cbank_1/switch_5/vin pll_full_0/vco 1.46fF
+C1376 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/a_740_n680# 0.08fF
+C1377 divider_1/tspc_1/Z2 divider_1/tspc_1/a_630_n680# 0.01fF
+C1378 divider_1/prescaler_0/tspc_2/a_740_n680# divider_1/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C1379 divider_2/tspc_0/Q divider_2/nor_1/A 0.55fF
+C1380 pll_full_1/ro_complete_0/cbank_2/switch_1/vin pll_full_1/ro_complete_0/cbank_2/v 1.30fF
+C1381 pll_full_0/pd_0/DOWN pll_full_0/pd_0/and_pd_0/Z1 0.07fF
+C1382 ro_complete_buffered_0/tapered_buf_6/a_1650_0# ro_complete_buffered_0/tapered_buf_6/a_210_n610# 2.89fF
+C1383 pll_full_1/divider_0/nor_1/B pll_full_1/divider_0/tspc_2/Z4 0.02fF
+C1384 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1385 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 pll_full_1/vco 0.45fF
+C1386 cp_buffered_0/tapered_buf_2/a_210_n610# cp_buffered_0/tapered_buf_2/a_1650_0# 2.89fF
+C1387 pd_buffered_0/tapered_buf_1/a_580_0# pd_buffered_0/tapered_buf_1/a_1650_0# 1.27fF
+C1388 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/DOWN 0.02fF
+C1389 pd_buffered_0/pd_0/tspc_r_0/Qbar1 pd_buffered_0/pd_0/R 0.30fF
+C1390 divider_0/tspc_0/Q divider_0/tspc_1/Z2 0.14fF
+C1391 divider_0/prescaler_0/tspc_2/a_740_n680# divider_0/prescaler_0/tspc_2/a_630_n680# 0.19fF
+C1392 ro_complete_buffered_0/tapered_buf_6/in ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.36fF
+C1393 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/R 0.27fF
+C1394 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z2 1.07fF
+C1395 ro_complete_buffered_0/tapered_buf_2/a_160_n140# ro_complete_buffered_0/tapered_buf_2/a_n10_n140# 0.05fF
+C1396 pd_0/tspc_r_0/Z4 pd_0/tspc_r_0/z5 0.04fF
+C1397 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z1 0.01fF
+C1398 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_0/Q 0.22fF
+C1399 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1400 ro_complete_0/cbank_0/switch_2/vin ro_complete_0/a3 0.09fF
+C1401 pll_full_1/ro_complete_0/cbank_0/switch_3/vin pll_full_1/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1402 ro_complete_buffered_0/tapered_buf_4/a_n10_230# ro_complete_buffered_0/tapered_buf_4/in 0.02fF
+C1403 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1404 divider_2/tspc_1/Z1 divider_2/tspc_1/Z2 1.07fF
+C1405 pll_full_0/pd_0/and_pd_0/Out1 pll_full_0/pd_0/and_pd_0/Z1 0.18fF
+C1406 pll_full_0/pd_0/tspc_r_0/Qbar1 pll_full_0/pd_0/UP 0.11fF
+C1407 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin 0.19fF
+C1408 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1409 divider_0/prescaler_0/m1_2700_2190# divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1410 cp_buffered_0/cp_0/a_1710_0# cp_buffered_0/cp_0/out 0.84fF
+C1411 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/R 0.02fF
+C1412 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 0.16fF
+C1413 pll_full_0/divider_0/nor_1/Z1 pll_full_0/divider_0/and_0/A 0.80fF
+C1414 pll_full_0/ro_complete_0/cbank_2/switch_5/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1415 divider_1/tspc_0/Q divider_1/tspc_1/Z1 0.01fF
+C1416 divider_1/prescaler_0/tspc_1/Z1 divider_1/prescaler_0/tspc_1/Z4 0.00fF
+C1417 pll_full_1/pd_0/tspc_r_1/z5 pll_full_1/div 0.04fF
+C1418 pll_full_0/divider_0/tspc_2/a_630_n680# pll_full_0/divider_0/tspc_2/Z4 0.12fF
+C1419 pll_full_0/divider_0/tspc_2/Z1 pll_full_0/divider_0/tspc_2/Z2 1.07fF
+C1420 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z3 0.38fF
+C1421 ro_complete_buffered_0/tapered_buf_3/a_210_n610# ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.22fF
+C1422 ro_complete_buffered_0/tapered_buf_3/a_160_230# ro_complete_buffered_0/tapered_buf_3/a_580_0# 0.02fF
+C1423 ro_complete_0/cbank_1/switch_1/vin ro_complete_0/cbank_1/v 1.30fF
+C1424 ro_complete_0/cbank_0/switch_5/vin ro_complete_0/cbank_0/v 1.30fF
+C1425 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z2 0.01fF
+C1426 divider_1/prescaler_0/tspc_0/D divider_1/prescaler_0/nand_1/z1 0.21fF
+C1427 ro_complete_buffered_0/tapered_buf_5/a_580_0# ro_complete_buffered_0/tapered_buf_5/a_1650_0# 1.27fF
+C1428 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/ro_complete_0/a3 26.29fF
+C1429 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/UP 0.03fF
+C1430 pd_buffered_0/tapered_buf_0/a_n10_n140# pd_buffered_0/pd_0/UP 0.04fF
+C1431 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1432 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_1/Q 0.21fF
+C1433 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
+C1434 divider_0/nor_1/B divider_0/tspc_2/Z4 0.02fF
+C1435 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/D 0.09fF
+C1436 pd_0/tspc_r_0/Qbar1 pd_0/tspc_r_0/z5 0.20fF
+C1437 pll_full_0/divider_0/tspc_1/a_630_n680# pll_full_0/divider_0/tspc_1/Z4 0.12fF
+C1438 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_2/Z2 0.01fF
+C1439 divider_1/mc2 divider_1/and_0/A 0.16fF
+C1440 ro_complete_buffered_0/tapered_buf_2/a_160_n140# ro_complete_buffered_0/tapered_buf_2/a_580_0# 0.35fF
+C1441 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/a2 0.09fF
+C1442 pll_full_0/divider_0/and_0/out1 pll_full_0/divider_0/and_0/Z1 0.36fF
+C1443 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Z4 0.01fF
+C1444 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_0/Q 0.01fF
+C1445 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 pll_full_1/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1446 divider_2/tspc_1/Q divider_2/tspc_2/Z1 0.01fF
+C1447 divider_1/nor_1/B divider_1/tspc_1/a_630_n680# 0.35fF
+C1448 divider_0/tspc_0/Q divider_0/nor_1/B 0.22fF
+C1449 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/in 0.19fF
+C1450 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# pll_full_0/divider_0/prescaler_0/tspc_0/Z4 0.12fF
+C1451 ro_complete_buffered_0/ro_complete_0/a0 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1452 divider_0/prescaler_0/tspc_1/Q divider_0/prescaler_0/nand_1/z1 0.22fF
+C1453 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/tspc_0/D 0.04fF
+C1454 divider_0/prescaler_0/tspc_1/Z2 divider_0/clk 0.11fF
+C1455 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/nand_0/z1 0.01fF
+C1456 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/vco 0.11fF
+C1457 divider_1/tspc_1/a_630_n680# divider_1/tspc_1/Z4 0.12fF
+C1458 divider_1/prescaler_0/tspc_2/Z2 divider_1/prescaler_0/tspc_2/Z4 0.36fF
+C1459 ro_complete_0/cbank_0/switch_3/vin ro_complete_0/cbank_0/v 1.30fF
+C1460 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/a4 0.12fF
+C1461 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1462 divider_2/prescaler_0/m1_2700_2190# divider_2/nor_1/A 0.01fF
+C1463 divider_2/prescaler_0/tspc_0/a_740_n680# divider_2/prescaler_0/tspc_1/Q 0.15fF
+C1464 divider_1/nor_1/B divider_1/mc2 0.06fF
+C1465 pd_buffered_0/tapered_buf_2/a_n10_n140# pd_buffered_0/tapered_buf_2/in 0.04fF
+C1466 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/vco 0.45fF
+C1467 divider_2/tspc_2/a_630_n680# divider_2/tspc_2/Z4 0.12fF
+C1468 divider_2/tspc_2/Z1 divider_2/tspc_2/Z2 1.07fF
+C1469 divider_2/nor_0/B divider_2/tspc_2/Z3 0.38fF
+C1470 pd_buffered_0/tapered_buf_1/a_210_n610# pd_buffered_0/tapered_buf_1/a_160_n140# 0.22fF
+C1471 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/R 0.51fF
+C1472 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_2/vin 0.20fF
+C1473 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/D 0.05fF
+C1474 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1475 pll_full_1/pd_0/DOWN pll_full_1/cp_0/a_1710_0# 0.04fF
+C1476 pll_full_0/filter_0/a_4216_n5230# pll_full_0/vco 1.58fF
+C1477 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/tspc_1/Z3 0.65fF
+C1478 pll_full_0/pd_0/tspc_r_0/Z2 pll_full_0/pd_0/tspc_r_0/Z4 0.14fF
+C1479 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/D 0.05fF
+C1480 divider_0/tspc_2/Z1 divider_0/tspc_2/Z4 0.00fF
+C1481 pd_0/tspc_r_1/Z3 pd_0/DOWN 0.03fF
+C1482 pll_full_0/divider_0/prescaler_0/tspc_1/Q pll_full_0/div 0.03fF
+C1483 pll_full_0/divider_0/and_0/OUT pll_full_0/vco 0.06fF
+C1484 ro_complete_0/a3 ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1485 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1486 pll_full_1/ro_complete_0/cbank_1/switch_1/vin pll_full_1/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1487 divider_0/prescaler_0/tspc_0/Z3 divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1488 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1489 pll_full_1/ro_complete_0/a4 pll_full_1/vco 0.01fF
+C1490 divider_2/tspc_1/Z1 divider_2/tspc_1/Z4 0.00fF
+C1491 divider_2/prescaler_0/tspc_2/a_630_n680# divider_2/prescaler_0/tspc_2/Z2 0.01fF
+C1492 ro_complete_buffered_0/tapered_buf_7/a_n10_n140# ro_complete_buffered_0/tapered_buf_7/in 0.04fF
+C1493 pd_buffered_0/tapered_buf_3/a_4670_0# pd_buffered_0/tapered_buf_3/a_210_n610# 29.21fF
+C1494 pd_buffered_0/tapered_buf_3/a_n10_230# pd_buffered_0/tapered_buf_3/a_160_230# 0.09fF
+C1495 divider_2/and_0/out1 divider_2/and_0/Z1 0.36fF
+C1496 pd_0/REF pd_0/tspc_r_0/Z2 0.19fF
+C1497 pd_buffered_0/pd_0/DOWN pd_buffered_0/tapered_buf_1/a_n10_n140# 0.04fF
+C1498 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/switch_5/vin 0.20fF
+C1499 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# ro_complete_buffered_0/tapered_buf_0/a_n10_230# 0.01fF
+C1500 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.12fF
+C1501 cp_buffered_0/tapered_buf_1/a_4670_0# cp_buffered_0/tapered_buf_1/a_210_n610# 29.21fF
+C1502 cp_buffered_0/tapered_buf_1/a_n10_230# cp_buffered_0/tapered_buf_1/a_160_230# 0.09fF
+C1503 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/vco 0.64fF
+C1504 divider_1/prescaler_0/tspc_0/Z2 divider_1/prescaler_0/tspc_0/D 0.09fF
+C1505 pd_0/R pd_0/and_pd_0/Z1 0.02fF
+C1506 ro_complete_0/a4 ro_complete_0/cbank_2/v 0.05fF
+C1507 ro_complete_0/cbank_1/switch_4/vin ro_complete_0/cbank_1/v 1.30fF
+C1508 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/nor_1/A 0.15fF
+C1509 pll_full_1/ro_complete_0/cbank_0/switch_5/vin pll_full_1/ro_complete_0/a0 0.09fF
+C1510 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1511 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.21fF
+C1512 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_0/Qbar1 0.30fF
+C1513 divider_2/and_0/OUT divider_2/prescaler_0/nand_0/z1 0.01fF
+C1514 pd_buffered_0/tapered_buf_1/out pd_buffered_0/tapered_buf_1/a_210_n610# 26.29fF
+C1515 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1516 pll_full_1/divider_0/and_0/B pll_full_1/divider_0/and_0/Z1 0.07fF
+C1517 pll_full_1/pd_0/tspc_r_0/Z4 pll_full_1/pd_0/tspc_r_0/z5 0.04fF
+C1518 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/switch_0/vin 0.19fF
+C1519 pll_full_0/ro_complete_0/cbank_2/switch_3/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1520 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1521 cp_buffered_0/tapered_buf_0/a_580_0# cp_buffered_0/tapered_buf_0/a_1650_0# 1.27fF
+C1522 pll_full_1/pd_0/tspc_r_0/Z2 pll_full_1/pd_0/R 0.21fF
+C1523 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Z2 0.25fF
+C1524 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.15fF
+C1525 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/and_0/A 0.01fF
+C1526 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/DOWN 0.03fF
+C1527 divider_1/and_0/out1 divider_1/and_0/A 0.01fF
+C1528 ro_complete_0/cbank_2/switch_2/vin ro_complete_0/cbank_2/v 1.30fF
+C1529 pll_full_1/divider_0/tspc_0/Z1 pll_full_1/divider_0/tspc_0/Z3 0.06fF
+C1530 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 pll_full_1/vco 0.12fF
+C1531 divider_2/and_0/OUT divider_2/clk 0.04fF
+C1532 divider_0/prescaler_0/tspc_0/Z2 divider_0/and_0/OUT 0.06fF
+C1533 cp_buffered_0/tapered_buf_2/a_160_230# cp_buffered_0/tapered_buf_2/a_580_0# 0.02fF
+C1534 pd_buffered_0/tapered_buf_1/a_n10_230# pd_buffered_0/pd_0/DOWN 0.02fF
+C1535 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_0/Z4 0.21fF
+C1536 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z3 0.45fF
+C1537 pll_full_0/divider_0/tspc_0/a_630_n680# pll_full_0/divider_0/tspc_0/Q 0.04fF
+C1538 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/and_0/A 0.26fF
+C1539 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/cbank_2/switch_4/vin 0.20fF
+C1540 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/a3 0.13fF
+C1541 divider_2/tspc_1/Z2 divider_2/tspc_1/Z3 0.16fF
+C1542 divider_2/prescaler_0/m1_2700_2190# divider_2/and_0/OUT 0.14fF
+C1543 divider_2/prescaler_0/tspc_0/Z3 divider_2/clk 0.64fF
+C1544 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/tspc_1/a_630_n680# 0.01fF
+C1545 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 1.07fF
+C1546 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/D 0.05fF
+C1547 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/nor_0/B 0.35fF
+C1548 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/vco 0.60fF
+C1549 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin 0.21fF
+C1550 pd_buffered_0/pd_0/tspc_r_1/Z4 pd_buffered_0/pd_0/tspc_r_1/z5 0.04fF
+C1551 pll_full_0/ro_complete_0/cbank_1/switch_3/vin pll_full_0/ro_complete_0/cbank_1/switch_4/vin 0.20fF
+C1552 pll_full_0/divider_0/nor_1/A pll_full_0/divider_0/tspc_1/Z4 0.02fF
+C1553 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.36fF
+C1554 divider_0/prescaler_0/tspc_2/Z1 divider_0/prescaler_0/tspc_2/Z4 0.00fF
+C1555 pll_full_1/pd_0/tspc_r_0/Qbar pll_full_1/pd_0/R 0.03fF
+C1556 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z3 0.16fF
+C1557 pll_full_0/divider_0/nor_0/B pll_full_0/divider_0/tspc_2/Z4 0.22fF
+C1558 divider_1/tspc_0/Q divider_1/tspc_1/Z3 0.45fF
+C1559 ro_complete_buffered_0/tapered_buf_3/in ro_complete_buffered_0/tapered_buf_3/a_160_n140# 0.19fF
+C1560 ro_complete_0/a5 ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C1561 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/UP 0.21fF
+C1562 divider_2/nor_1/A divider_2/prescaler_0/tspc_1/Q 0.03fF
+C1563 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/D 0.15fF
+C1564 divider_2/nor_0/Z1 divider_2/and_0/B 0.78fF
+C1565 divider_0/nor_0/Z1 divider_0/nor_1/B 0.18fF
+C1566 divider_0/prescaler_0/Out divider_0/tspc_0/Z3 0.45fF
+C1567 ro_complete_buffered_0/tapered_buf_5/a_1650_0# ro_complete_buffered_0/tapered_buf_5/a_4670_0# 4.78fF
+C1568 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_160_230# 0.17fF
+C1569 pll_full_1/divider_0/tspc_0/Z1 pll_full_1/divider_0/tspc_0/Z2 1.07fF
+C1570 pll_full_1/ro_complete_0/a1 pll_full_1/vco 0.11fF
+C1571 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z3 0.05fF
+C1572 divider_0/tspc_0/a_630_n680# divider_0/tspc_0/Z2 0.01fF
+C1573 ro_complete_buffered_0/tapered_buf_0/a_1650_0# ro_complete_buffered_0/tapered_buf_0/a_4670_0# 4.78fF
+C1574 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin 0.20fF
+C1575 pd_buffered_0/pd_0/and_pd_0/Out1 pd_buffered_0/pd_0/UP 0.33fF
+C1576 pll_full_0/pd_0/tspc_r_1/Qbar1 pll_full_0/div 0.12fF
+C1577 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_1/Z4 0.21fF
+C1578 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1579 pll_full_0/ro_complete_0/a0 pll_full_0/vco 0.11fF
+C1580 divider_0/prescaler_0/tspc_1/Z2 divider_0/prescaler_0/tspc_1/Q 0.06fF
+C1581 divider_0/prescaler_0/tspc_1/Z4 divider_0/clk 0.12fF
+C1582 ro_complete_0/cbank_2/switch_3/vin ro_complete_0/a2 0.09fF
+C1583 pll_full_1/pd_0/tspc_r_0/Z3 pll_full_1/pd_0/tspc_r_0/Z1 0.09fF
+C1584 pll_full_0/divider_0/and_0/A pll_full_0/divider_0/and_0/B 0.18fF
+C1585 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z3 0.65fF
+C1586 ro_complete_0/a1 ro_complete_0/cbank_2/v 0.05fF
+C1587 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_2/switch_4/vin 0.13fF
+C1588 divider_2/tspc_1/Q divider_2/tspc_2/Z3 0.45fF
+C1589 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_0/Q 0.45fF
+C1590 pd_buffered_0/tapered_buf_1/a_210_n610# pd_buffered_0/tapered_buf_1/a_580_0# 0.84fF
+C1591 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/tspc_r_0/Z4 0.14fF
+C1592 divider_0/tspc_0/a_630_n680# divider_0/nor_1/B 0.01fF
+C1593 divider_0/prescaler_0/Out divider_0/tspc_0/Z4 0.12fF
+C1594 gnd ro_complete_buffered_0/tapered_buf_1/a_580_0# 5.71fF
+C1595 pll_full_1/cp_0/down pll_full_1/cp_0/a_1710_0# 0.32fF
+C1596 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/divider_0/prescaler_0/nand_0/z1 0.24fF
+C1597 divider_1/prescaler_0/Out divider_1/nor_1/A 0.15fF
+C1598 divider_0/prescaler_0/tspc_2/Q divider_0/prescaler_0/nand_1/z1 0.01fF
+C1599 divider_0/prescaler_0/tspc_2/Z2 divider_0/clk 0.11fF
+C1600 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_2/switch_3/vin 0.09fF
+C1601 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/tspc_0/Z2 0.01fF
+C1602 divider_2/prescaler_0/tspc_1/Z2 divider_2/and_0/OUT 0.06fF
+C1603 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/and_0/OUT 0.06fF
+C1604 pll_full_1/pd_0/R pll_full_1/div 0.51fF
+C1605 pll_full_0/pd_0/tspc_r_0/Z1 pll_full_0/ref 0.17fF
+C1606 divider_2/tspc_2/Z2 divider_2/tspc_2/Z3 0.16fF
+C1607 divider_2/nor_0/B divider_2/tspc_2/Z4 0.22fF
+C1608 pll_full_1/divider_0/tspc_0/Z2 pll_full_1/divider_0/tspc_0/Z3 0.16fF
+C1609 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 pll_full_1/vco 0.12fF
+C1610 pd_buffered_0/pd_0/tspc_r_1/Qbar1 pd_buffered_0/pd_0/R 0.01fF
+C1611 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z4 0.02fF
+C1612 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/tspc_r_1/Qbar 0.21fF
+C1613 divider_0/tspc_0/Q divider_0/tspc_1/Z4 0.15fF
+C1614 divider_0/prescaler_0/tspc_0/Z4 divider_0/prescaler_0/tspc_0/D 0.11fF
+C1615 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1616 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1617 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin ro_complete_buffered_0/ro_complete_0/a3 0.09fF
+C1618 pd_0/tspc_r_0/Z3 pd_0/tspc_r_0/Z1 0.09fF
+C1619 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Q 0.13fF
+C1620 pd_0/tspc_r_1/Z3 pd_0/tspc_r_1/Z1 0.09fF
+C1621 pd_0/DIV pd_0/tspc_r_1/Z2 0.19fF
+C1622 io_clamp_low[2] io_analog[6] 0.53fF
+C1623 pll_full_0/divider_0/prescaler_0/tspc_2/D pll_full_0/vco 0.26fF
+C1624 divider_2/mc2 divider_2/and_0/A 0.16fF
+C1625 divider_2/nor_1/B divider_2/nor_0/B 0.47fF
+C1626 divider_0/tspc_2/Z3 divider_0/tspc_2/Z4 0.65fF
+C1627 ro_complete_0/cbank_0/switch_4/vin ro_complete_0/a0 0.13fF
+C1628 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 0.16fF
+C1629 divider_2/prescaler_0/Out divider_2/prescaler_0/tspc_1/Z1 0.08fF
+C1630 divider_2/tspc_1/Z3 divider_2/tspc_1/Z4 0.65fF
+C1631 pll_full_1/divider_0/tspc_1/Z1 pll_full_1/divider_0/tspc_1/Z4 0.00fF
+C1632 pd_buffered_0/tapered_buf_3/a_n10_230# pd_buffered_0/tapered_buf_3/a_n10_n140# 0.01fF
+C1633 divider_2/and_0/A divider_2/and_0/B 0.18fF
+C1634 ro_complete_buffered_0/tapered_buf_0/a_210_n610# ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.22fF
+C1635 ro_complete_buffered_0/tapered_buf_0/a_160_230# ro_complete_buffered_0/tapered_buf_0/a_580_0# 0.02fF
+C1636 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
+C1637 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin ro_complete_buffered_0/ro_complete_0/cbank_0/v 1.30fF
+C1638 pll_full_0/ro_complete_0/a5 pll_full_0/ro_complete_0/cbank_1/switch_0/vin 0.09fF
+C1639 pll_full_0/ro_complete_0/cbank_0/switch_4/vin pll_full_0/ro_complete_0/cbank_0/v 1.30fF
+C1640 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z3 0.16fF
+C1641 cp_buffered_0/tapered_buf_1/a_n10_230# cp_buffered_0/tapered_buf_1/a_n10_n140# 0.01fF
+C1642 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z3 0.45fF
+C1643 pll_full_0/ro_complete_0/a3 pll_full_0/vco 0.11fF
+C1644 ro_complete_buffered_0/tapered_buf_2/a_n10_230# ro_complete_buffered_0/tapered_buf_2/a_160_230# 0.09fF
+C1645 ro_complete_0/cbank_1/switch_0/vin ro_complete_0/cbank_1/v 1.43fF
+C1646 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.00fF
+C1647 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_2/v 0.05fF
+C1648 divider_2/prescaler_0/Out divider_2/tspc_0/Z3 0.45fF
+C1649 divider_2/nor_1/Z1 divider_2/and_0/A 0.80fF
+C1650 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z3 0.05fF
+C1651 divider_1/nor_0/B divider_1/tspc_2/Z1 0.03fF
+C1652 pll_full_0/pd_0/R pll_full_0/pd_0/tspc_r_1/Qbar1 0.01fF
+C1653 divider_2/prescaler_0/tspc_2/D divider_2/prescaler_0/nand_0/z1 0.24fF
+C1654 divider_2/prescaler_0/tspc_0/Z2 divider_2/clk 0.11fF
+C1655 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 0.65fF
+C1656 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/vco 0.14fF
+C1657 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/tspc_r_0/Z1 0.17fF
+C1658 pll_full_1/pd_0/tspc_r_1/z5 pll_full_1/pd_0/DOWN 0.03fF
+C1659 ro_complete_buffered_0/tapered_buf_1/a_160_230# ro_complete_buffered_0/tapered_buf_1/a_580_0# 0.02fF
+C1660 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/prescaler_0/m1_2700_2190# 0.11fF
+C1661 divider_2/nor_1/B divider_2/tspc_1/Z1 0.03fF
+C1662 cp_buffered_0/tapered_buf_0/a_1650_0# cp_buffered_0/tapered_buf_0/a_4670_0# 4.78fF
+C1663 cp_buffered_0/tapered_buf_0/a_160_n140# cp_buffered_0/tapered_buf_0/a_160_230# 0.17fF
+C1664 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.05fF
+C1665 ro_complete_buffered_0/tapered_buf_2/a_210_n610# ro_complete_buffered_0/tapered_buf_2/a_1650_0# 2.89fF
+C1666 ro_complete_0/cbank_0/switch_0/vin ro_complete_0/a4 0.12fF
+C1667 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/cbank_0/switch_1/vin 0.19fF
+C1668 divider_1/nor_1/B divider_1/tspc_0/a_630_n680# 0.01fF
+C1669 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/switch_5/vin 0.20fF
+C1670 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_1/Z2 0.15fF
+C1671 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/tspc_0/a_630_n680# 0.01fF
+C1672 pll_full_0/pd_0/tspc_r_0/Qbar pll_full_0/pd_0/R 0.03fF
+C1673 divider_2/prescaler_0/tspc_0/Z3 divider_2/prescaler_0/tspc_1/Q 0.13fF
+C1674 pd_buffered_0/tapered_buf_2/a_160_n140# pd_buffered_0/tapered_buf_2/a_210_n610# 0.22fF
+C1675 pd_buffered_0/tapered_buf_2/a_580_0# pd_buffered_0/tapered_buf_2/a_160_230# 0.02fF
+C1676 divider_2/prescaler_0/tspc_2/D divider_2/clk 0.26fF
+C1677 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/tspc_2/a_630_n680# 0.01fF
+C1678 pd_buffered_0/pd_0/tspc_r_0/Z2 pd_buffered_0/pd_0/R 0.21fF
+C1679 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_1/switch_3/vin 0.09fF
+C1680 divider_2/prescaler_0/tspc_0/a_630_n680# divider_2/prescaler_0/tspc_0/Z2 0.01fF
+C1681 divider_0/tspc_0/Z3 divider_0/tspc_0/Z4 0.65fF
+C1682 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_1/Z3 0.06fF
+C1683 pll_full_0/divider_0/prescaler_0/Out pll_full_0/divider_0/tspc_0/Z2 0.11fF
+C1684 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_0/divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1685 divider_1/mc2 divider_1/prescaler_0/tspc_2/a_630_n680# 0.33fF
+C1686 divider_0/and_0/OUT divider_0/and_0/B 0.01fF
+C1687 pd_0/tspc_r_0/Qbar pd_0/DOWN 0.02fF
+C1688 pll_full_0/divider_0/tspc_1/Q pll_full_0/divider_0/tspc_2/Z4 0.15fF
+C1689 divider_2/prescaler_0/tspc_0/Z4 divider_2/prescaler_0/tspc_0/Z2 0.36fF
+C1690 divider_1/and_0/OUT divider_1/prescaler_0/tspc_2/D 0.03fF
+C1691 ro_complete_0/a4 ro_complete_0/cbank_2/switch_1/vin 0.09fF
+C1692 pll_full_1/divider_0/tspc_1/Z2 pll_full_1/divider_0/nor_1/B 0.30fF
+C1693 divider_2/tspc_1/Z2 divider_2/nor_1/A 0.15fF
+C1694 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_2/D 0.16fF
+C1695 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 0.22fF
+C1696 ro_complete_buffered_0/tapered_buf_7/a_580_0# ro_complete_buffered_0/tapered_buf_7/a_160_230# 0.02fF
+C1697 pll_full_1/divider_0/and_0/OUT pll_full_1/divider_0/and_0/Z1 0.04fF
+C1698 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/divider_0/tspc_2/Z2 0.01fF
+C1699 pll_full_1/divider_0/prescaler_0/tspc_2/Q pll_full_1/vco 0.05fF
+C1700 pd_buffered_0/tapered_buf_1/a_n10_230# pd_buffered_0/tapered_buf_1/a_n10_n140# 0.01fF
+C1701 pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/and_pd_0/Z1 0.07fF
+C1702 ro_complete_buffered_0/ro_complete_0/a3 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin 0.13fF
+C1703 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1704 divider_1/prescaler_0/tspc_0/Z3 divider_1/prescaler_0/tspc_0/Z2 0.16fF
+C1705 pll_full_0/divider_0/tspc_0/Z4 pll_full_0/divider_0/tspc_0/a_630_n680# 0.12fF
+C1706 divider_1/tspc_0/Q divider_1/nor_1/A 0.55fF
+C1707 pll_full_0/divider_0/tspc_2/Z2 pll_full_0/divider_0/tspc_2/Z4 0.36fF
+C1708 pll_full_0/divider_0/tspc_2/Z3 pll_full_0/div 0.05fF
+C1709 ro_complete_0/cbank_2/switch_1/vin ro_complete_0/cbank_2/switch_2/vin 0.20fF
+C1710 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_0/a_740_n680# 0.21fF
+C1711 ro_complete_buffered_0/tapered_buf_5/a_580_0# ro_complete_buffered_0/tapered_buf_5/a_210_n610# 0.84fF
+C1712 ro_complete_buffered_0/tapered_buf_5/a_160_n140# ro_complete_buffered_0/tapered_buf_5/a_n10_n140# 0.05fF
+C1713 divider_2/prescaler_0/tspc_2/Z3 divider_2/prescaler_0/tspc_2/D 0.05fF
+C1714 ro_complete_buffered_0/tapered_buf_5/a_210_n610# ro_complete_buffered_0/ro_complete_0/a0 26.29fF
+C1715 pll_full_1/divider_0/and_0/out1 pll_full_1/divider_0/and_0/B 0.18fF
+C1716 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# 0.33fF
+C1717 pll_full_0/ro_complete_0/a3 pll_full_0/ro_complete_0/cbank_2/switch_2/vin 0.09fF
+C1718 divider_1/prescaler_0/tspc_0/Z4 divider_1/prescaler_0/tspc_0/D 0.11fF
+C1719 ro_complete_buffered_0/ro_complete_0/a4 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1720 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/tapered_buf_6/in 1.30fF
+C1721 pd_0/tspc_r_0/Z2 pd_0/tspc_r_0/Z4 0.14fF
+C1722 pll_full_0/pd_0/tspc_r_1/Z3 pll_full_0/pd_0/tspc_r_1/Z4 0.20fF
+C1723 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 0.06fF
+C1724 divider_1/tspc_1/Z1 divider_1/tspc_1/Z2 1.07fF
+C1725 ro_complete_buffered_0/tapered_buf_2/a_n10_230# ro_complete_buffered_0/tapered_buf_2/a_n10_n140# 0.01fF
+C1726 divider_2/prescaler_0/Out divider_2/tspc_0/Z4 0.12fF
+C1727 ro_complete_0/cbank_1/switch_5/vin ro_complete_0/cbank_1/v 1.30fF
+C1728 pll_full_1/divider_0/prescaler_0/Out pll_full_1/divider_0/prescaler_0/tspc_1/Z2 0.19fF
+C1729 ro_complete_buffered_0/tapered_buf_6/a_160_n140# ro_complete_buffered_0/tapered_buf_6/a_580_0# 0.35fF
+C1730 pll_full_1/divider_0/tspc_1/a_630_n680# pll_full_1/divider_0/nor_0/B 0.00fF
+C1731 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.05fF
+C1732 divider_2/tspc_1/Q divider_2/tspc_2/Z4 0.15fF
+C1733 divider_2/nor_1/A divider_2/and_0/A 0.01fF
+C1734 divider_0/prescaler_0/Out divider_0/prescaler_0/tspc_1/Z1 0.08fF
+C1735 gnd ro_complete_buffered_0/tapered_buf_1/a_1650_0# 20.70fF
+C1736 ro_complete_buffered_0/tapered_buf_6/a_n10_230# ro_complete_buffered_0/tapered_buf_6/in 0.02fF
+C1737 cp_buffered_0/tapered_buf_2/a_160_230# cp_buffered_0/tapered_buf_2/a_160_n140# 0.17fF
+C1738 pll_full_0/ro_complete_0/cbank_2/switch_1/vin pll_full_0/ro_complete_0/cbank_2/v 1.30fF
+C1739 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin ro_complete_buffered_0/ro_complete_0/cbank_2/v 1.30fF
+C1740 divider_2/nor_1/B divider_2/tspc_1/Q 0.51fF
+C1741 divider_0/prescaler_0/tspc_0/D divider_0/prescaler_0/nand_1/z1 0.21fF
+C1742 pll_full_1/pd_0/tspc_r_0/Qbar1 pll_full_1/pd_0/UP 0.11fF
+C1743 pll_full_0/divider_0/nor_1/B pll_full_0/divider_0/tspc_2/Z4 0.02fF
+C1744 pll_full_0/divider_0/and_0/OUT pll_full_0/divider_0/prescaler_0/tspc_2/Q 0.04fF
+C1745 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/vco 0.45fF
+C1746 ro_complete_0/cbank_0/switch_1/vin ro_complete_0/a3 0.13fF
+C1747 ro_complete_0/a4 ro_complete_0/cbank_1/switch_1/vin 0.09fF
+C1748 pll_full_1/ro_complete_0/a2 pll_full_1/ro_complete_0/cbank_0/switch_2/vin 0.14fF
+C1749 pll_full_1/ro_complete_0/cbank_0/switch_1/vin pll_full_1/ro_complete_0/a4 0.09fF
+C1750 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/a5 0.09fF
+C1751 pll_full_1/pd_0/tspc_r_1/Z1 pll_full_1/div 0.17fF
+C1752 divider_0/prescaler_0/tspc_0/a_630_n680# divider_0/prescaler_0/Out 0.04fF
+C1753 ro_complete_buffered_0/tapered_buf_4/a_160_n140# ro_complete_buffered_0/tapered_buf_4/a_160_230# 0.17fF
+C1754 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z1 0.03fF
+C1755 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Z4 0.01fF
+C1756 pll_full_1/divider_0/prescaler_0/m1_2700_2190# pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# 0.19fF
+C1757 divider_0/mc2 divider_0/nor_1/B 0.06fF
+C1758 divider_2/tspc_2/Z2 divider_2/tspc_2/Z4 0.36fF
+C1759 divider_2/tspc_2/Z3 divider_2/Out 0.05fF
+C1760 divider_1/nor_1/B divider_1/nor_0/B 0.47fF
+C1761 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin ro_complete_buffered_0/ro_complete_0/a3 0.13fF
+C1762 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/tapered_buf_0/a_210_n610# 26.29fF
+C1763 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin ro_complete_buffered_0/ro_complete_0/a1 0.14fF
+C1764 pd_buffered_0/pd_0/tspc_r_0/Qbar pd_buffered_0/pd_0/and_pd_0/Z1 0.02fF
+C1765 pd_buffered_0/pd_0/tspc_r_1/Z3 pd_buffered_0/pd_0/tspc_r_1/z5 0.11fF
+C1766 pll_full_1/pd_0/tspc_r_1/z5 pll_full_1/pd_0/tspc_r_0/z5 0.02fF
+C1767 pll_full_0/ro_complete_0/cbank_0/switch_3/vin pll_full_0/ro_complete_0/cbank_0/switch_4/vin 0.20fF
+C1768 pll_full_1/pd_0/tspc_r_0/z5 pll_full_1/pd_0/tspc_r_0/Qbar1 0.20fF
+C1769 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/D 0.03fF
+C1770 pll_full_0/ref pll_full_0/pd_0/tspc_r_0/Z2 0.19fF
+C1771 divider_0/tspc_1/Z1 divider_0/tspc_1/Z2 1.07fF
+C1772 pd_0/DIV pd_0/R 0.51fF
+C1773 divider_2/nor_1/B divider_2/tspc_2/Z2 0.20fF
+C1774 divider_1/tspc_1/Q divider_1/tspc_2/Z1 0.01fF
+C1775 ro_complete_0/cbank_1/switch_3/vin ro_complete_0/cbank_1/v 1.30fF
+C1776 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/Out 0.05fF
+C1777 divider_2/nor_1/A divider_2/tspc_1/Z4 0.02fF
+C1778 divider_2/prescaler_0/tspc_0/Z2 divider_2/prescaler_0/tspc_1/Q 0.06fF
+C1779 divider_2/prescaler_0/tspc_2/Z1 divider_2/prescaler_0/tspc_2/Z3 0.06fF
+C1780 pll_full_1/divider_0/tspc_1/Z3 pll_full_1/divider_0/tspc_1/Z4 0.65fF
+C1781 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# pll_full_1/divider_0/prescaler_0/tspc_1/Q 0.15fF
+C1782 pll_full_1/ro_complete_0/a5 pll_full_1/vco 0.15fF
+C1783 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C1784 ro_complete_buffered_0/tapered_buf_0/in ro_complete_buffered_0/tapered_buf_0/a_160_n140# 0.19fF
+C1785 ro_complete_buffered_0/ro_complete_0/a5 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin 0.09fF
+C1786 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/UP 0.45fF
+C1787 divider_0/tspc_1/a_630_n680# divider_0/nor_0/B 0.00fF
+C1788 divider_0/prescaler_0/tspc_2/Z2 divider_0/prescaler_0/tspc_2/Z4 0.36fF
+C1789 divider_1/prescaler_0/m1_2700_2190# divider_1/nor_1/A 0.01fF
+C1790 pll_full_1/pd_0/tspc_r_1/Z3 pll_full_1/pd_0/tspc_r_1/Z2 0.25fF
+C1791 divider_1/tspc_2/a_630_n680# divider_1/tspc_2/Z4 0.12fF
+C1792 divider_1/tspc_2/Z1 divider_1/tspc_2/Z2 1.07fF
+C1793 divider_1/nor_0/B divider_1/tspc_2/Z3 0.38fF
+C1794 ro_complete_0/a5 ro_complete_0/cbank_2/v 0.08fF
+C1795 ro_complete_0/a0 ro_complete_0/cbank_1/switch_5/vin 0.09fF
+C1796 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 0.65fF
+C1797 pll_full_0/pd_0/tspc_r_0/Z3 pll_full_0/pd_0/tspc_r_0/Qbar1 0.38fF
+C1798 divider_2/tspc_1/a_630_n680# divider_2/nor_0/B 0.00fF
+C1799 divider_2/and_0/OUT divider_2/prescaler_0/tspc_2/Q 0.04fF
+C1800 divider_2/prescaler_0/tspc_1/Z3 divider_2/clk 0.45fF
+C1801 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z3 0.38fF
+C1802 divider_1/nor_1/B divider_1/tspc_1/Z1 0.03fF
+C1803 ro_complete_buffered_0/tapered_buf_1/a_210_n610# gnd 212.43fF
+C1804 pd_buffered_0/pd_0/tspc_r_0/Z3 pd_buffered_0/pd_0/tspc_r_0/Z2 0.25fF
+C1805 divider_1/tspc_0/Z1 divider_1/tspc_0/Z2 1.07fF
+C1806 ro_complete_buffered_0/ro_complete_0/a1 ro_complete_buffered_0/ro_complete_0/cbank_2/v 0.05fF
+C1807 pd_0/tspc_r_0/Z2 pd_0/R 0.21fF
+C1808 cp_buffered_0/tapered_buf_0/a_580_0# cp_buffered_0/tapered_buf_0/a_210_n610# 0.84fF
+C1809 cp_buffered_0/tapered_buf_0/a_160_n140# cp_buffered_0/tapered_buf_0/a_n10_n140# 0.05fF
+C1810 pll_full_0/divider_0/tspc_1/Z1 pll_full_0/divider_0/tspc_0/Q 0.01fF
+C1811 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 pll_full_0/divider_0/prescaler_0/tspc_2/D 0.11fF
+C1812 divider_2/nor_1/B divider_2/tspc_1/Z3 0.38fF
+C1813 divider_1/prescaler_0/Out divider_1/prescaler_0/tspc_0/a_630_n680# 0.04fF
+C1814 divider_1/tspc_1/Z1 divider_1/tspc_1/Z4 0.00fF
+C1815 divider_1/prescaler_0/tspc_2/a_630_n680# divider_1/prescaler_0/tspc_2/Z2 0.01fF
+C1816 pll_full_0/pd_0/tspc_r_0/z5 pll_full_0/pd_0/tspc_r_0/Z3 0.11fF
+C1817 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/tspc_1/Z3 0.33fF
+C1818 divider_1/and_0/out1 divider_1/and_0/Z1 0.36fF
+C1819 ro_complete_0/cbank_2/switch_4/vin ro_complete_0/cbank_2/v 1.30fF
+C1820 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/prescaler_0/m1_2700_2190# 0.01fF
+C1821 pll_full_1/ro_complete_0/a0 pll_full_1/ro_complete_0/cbank_2/switch_5/vin 0.09fF
+C1822 pd_buffered_0/tapered_buf_2/a_160_n140# pd_buffered_0/tapered_buf_2/in 0.19fF
+C1823 pd_buffered_0/tapered_buf_2/a_1650_0# pd_buffered_0/tapered_buf_2/a_210_n610# 2.89fF
+C1824 pll_full_1/divider_0/tspc_1/Q pll_full_1/divider_0/nor_0/B 0.22fF
+C1825 pll_full_1/divider_0/prescaler_0/tspc_1/Q pll_full_1/divider_0/prescaler_0/tspc_2/Q 0.19fF
+C1826 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# pll_full_1/vco 0.01fF
+C1827 cp_buffered_0/tapered_buf_2/a_n10_n140# cp_buffered_0/tapered_buf_2/a_160_n140# 0.05fF
+C1828 pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/tspc_r_1/Z3 0.65fF
+C1829 pll_full_0/ro_complete_0/cbank_0/switch_0/vin pll_full_0/ro_complete_0/a4 0.12fF
+C1830 pll_full_0/ro_complete_0/a2 pll_full_0/ro_complete_0/cbank_0/switch_3/vin 0.09fF
+C1831 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/tspc_0/a_630_n680# 0.19fF
+C1832 divider_0/tspc_1/a_630_n680# divider_0/tspc_1/Z3 0.05fF
+C1833 divider_0/nor_1/B divider_0/tspc_1/Z1 0.03fF
+C1834 divider_0/prescaler_0/tspc_1/Z4 divider_0/prescaler_0/m1_2700_2190# 0.08fF
+C1835 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 pll_full_0/vco 0.45fF
+C1836 pll_full_1/ro_complete_0/cbank_0/switch_0/vin pll_full_1/ro_complete_0/cbank_0/v 1.30fF
+C1837 divider_1/and_0/OUT divider_1/prescaler_0/nand_0/z1 0.01fF
+C1838 divider_2/prescaler_0/m1_2700_2190# divider_2/prescaler_0/nand_0/z1 0.07fF
+C1839 ro_complete_buffered_0/tapered_buf_4/a_n10_n140# ro_complete_buffered_0/tapered_buf_4/in 0.04fF
+C1840 pll_full_1/divider_0/nor_1/A pll_full_1/divider_0/tspc_0/Z2 0.23fF
+C1841 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 0.06fF
+C1842 pll_full_1/ro_complete_0/cbank_1/switch_3/vin pll_full_1/vco 1.46fF
+C1843 divider_2/mc2 divider_2/nor_1/B 0.06fF
+C1844 ro_complete_buffered_0/tapered_buf_7/a_160_n140# ro_complete_buffered_0/tapered_buf_7/in 0.19fF
+C1845 ro_complete_buffered_0/tapered_buf_7/a_1650_0# ro_complete_buffered_0/tapered_buf_7/a_210_n610# 2.89fF
+C1846 ro_complete_buffered_0/tapered_buf_4/a_210_n610# ro_complete_buffered_0/ro_complete_0/a1 26.29fF
+C1847 pll_full_1/divider_0/tspc_2/a_630_n680# pll_full_1/div 0.04fF
+C1848 pll_full_1/divider_0/nor_0/B pll_full_1/divider_0/tspc_2/Z2 0.40fF
+C1849 pll_full_1/divider_0/prescaler_0/tspc_0/D pll_full_1/vco 0.29fF
+C1850 divider_1/prescaler_0/tspc_0/a_740_n680# divider_1/prescaler_0/Out 0.21fF
+C1851 divider_0/prescaler_0/tspc_0/Z2 divider_0/clk 0.11fF
+C1852 ro_complete_buffered_0/ro_complete_0/a2 ro_complete_buffered_0/tapered_buf_6/in 0.05fF
+C1853 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin ro_complete_buffered_0/ro_complete_0/a0 0.13fF
+C1854 pd_buffered_0/tapered_buf_0/a_n10_230# pd_buffered_0/tapered_buf_0/a_160_230# 0.09fF
+C1855 pd_buffered_0/pd_0/R pd_buffered_0/pd_0/and_pd_0/Out1 0.33fF
+C1856 pll_full_1/pd_0/and_pd_0/Z1 pll_full_1/pd_0/and_pd_0/Out1 0.18fF
+C1857 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 1.07fF
+C1858 pll_full_0/ro_complete_0/cbank_1/switch_1/vin pll_full_0/ro_complete_0/cbank_1/switch_2/vin 0.20fF
+C1859 divider_0/tspc_1/Z2 divider_0/nor_1/A 0.15fF
+C1860 divider_0/prescaler_0/tspc_1/a_630_n680# divider_0/prescaler_0/tspc_1/Z2 0.01fF
+C1861 pll_full_1/pd_0/DOWN pll_full_1/pd_0/R 0.36fF
+C1862 pll_full_1/pd_0/tspc_r_0/Z2 pll_full_1/ref 0.19fF
+C1863 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 0.65fF
+C1864 pll_full_0/ro_complete_0/a4 pll_full_0/vco 0.01fF
+C1865 pd_0/tspc_r_1/Z4 pd_0/tspc_r_1/z5 0.04fF
+Xpd_buffered_0/tapered_buf_2 pd_buffered_0/pd_0/DIV pd_buffered_0/tapered_buf_2/in
++ vdda1 vssa1 tapered_buf
+Xpd_buffered_0/tapered_buf_3 pd_buffered_0/pd_0/REF pd_buffered_0/tapered_buf_3/in
++ vdda1 vssa1 tapered_buf
+Xpd_buffered_0/pd_0 vssa1 pd_buffered_0/pd_0/REF pd_buffered_0/pd_0/DIV pd_buffered_0/pd_0/UP
++ pd_buffered_0/pd_0/DOWN pd_buffered_0/pd_0/R vssa1 vdd pd
+Xpd_buffered_0/tapered_buf_1 pd_buffered_0/tapered_buf_1/out pd_buffered_0/pd_0/DOWN
++ vdd vssa1 tapered_buf
+Xpd_buffered_0/tapered_buf_0 pd_buffered_0/tapered_buf_0/out pd_buffered_0/pd_0/UP
++ vdd vssa1 tapered_buf
+Xcp_buffered_0 vdda1 vdda1 cp_buffered
 Xpd_0 vssa1 pd_0/REF pd_0/DIV pd_0/UP pd_0/DOWN pd_0/R vssa1 vdda1 pd
-Xpd_1 vssa1 pd_1/REF pd_1/DIV pd_1/UP pd_1/DOWN pd_1/R vssa1 vdda1 pd
-Xcp_0 cp_0/vbias vdda1 vdda1 cp_0/out cp_0/down cp_0/upbar cp
 Xfilter_0 vssa1 filter_0/v filter
 Xro_complete_0 ro_complete_0/a0 ro_complete_0/a1 ro_complete_0/a5 ro_complete_0/a4
 + ro_complete_0/a3 ro_complete_0/a2 ro_complete
@@ -1870,1234 +1993,1296 @@
 Xdivider_2 vssa1 vdda1 divider_2/Out divider_2/clk divider_2/mc2 vssa1 vdda1 divider
 Xpll_full_0 vdd pll_full_0/ref pll_full_0/div pll_full_0/vco pll_full
 Xpll_full_1 vdd pll_full_1/ref pll_full_1/div pll_full_1/vco pll_full
-C1752 io_analog[4] vssa1 43.96fF
-C1753 io_analog[5] vssa1 44.13fF
-C1754 io_analog[6] vssa1 43.46fF
-C1755 io_in_3v3[0] vssa1 0.61fF
-C1756 io_oeb[26] vssa1 0.61fF
-C1757 io_in[0] vssa1 0.61fF
-C1758 io_out[26] vssa1 0.61fF
-C1759 io_out[0] vssa1 0.61fF
-C1760 io_in[26] vssa1 0.61fF
-C1761 io_oeb[0] vssa1 0.61fF
-C1762 io_in_3v3[26] vssa1 0.61fF
-C1763 io_in_3v3[1] vssa1 0.61fF
-C1764 io_oeb[25] vssa1 0.61fF
-C1765 io_in[1] vssa1 0.61fF
-C1766 io_out[25] vssa1 0.61fF
-C1767 io_out[1] vssa1 0.61fF
-C1768 io_in[25] vssa1 0.61fF
-C1769 io_oeb[1] vssa1 0.61fF
-C1770 io_in_3v3[25] vssa1 0.61fF
-C1771 io_in_3v3[2] vssa1 0.61fF
-C1772 io_oeb[24] vssa1 0.61fF
-C1773 io_in[2] vssa1 0.61fF
-C1774 io_out[24] vssa1 0.61fF
-C1775 io_out[2] vssa1 0.61fF
-C1776 io_in[24] vssa1 0.61fF
-C1777 io_oeb[2] vssa1 0.61fF
-C1778 io_in_3v3[24] vssa1 0.61fF
-C1779 io_in_3v3[3] vssa1 0.61fF
-C1780 gpio_noesd[17] vssa1 2.32fF
-C1781 io_in[3] vssa1 0.61fF
-C1782 gpio_analog[17] vssa1 2.30fF
-C1783 io_out[3] vssa1 0.61fF
-C1784 io_oeb[3] vssa1 0.61fF
-C1785 io_in_3v3[4] vssa1 0.61fF
-C1786 io_in[4] vssa1 0.61fF
-C1787 io_out[4] vssa1 0.61fF
-C1788 io_oeb[4] vssa1 0.61fF
-C1789 io_oeb[23] vssa1 0.61fF
-C1790 io_out[23] vssa1 0.61fF
-C1791 io_in[23] vssa1 0.61fF
-C1792 io_in_3v3[23] vssa1 0.61fF
-C1793 gpio_noesd[16] vssa1 2.30fF
-C1794 gpio_analog[16] vssa1 2.30fF
-C1795 io_in_3v3[5] vssa1 0.61fF
-C1796 io_in[5] vssa1 0.61fF
-C1797 io_out[5] vssa1 0.61fF
-C1798 io_oeb[5] vssa1 0.61fF
-C1799 io_oeb[22] vssa1 0.61fF
-C1800 io_out[22] vssa1 0.61fF
-C1801 io_in[22] vssa1 0.61fF
-C1802 io_in_3v3[22] vssa1 0.61fF
-C1803 gpio_noesd[15] vssa1 2.31fF
-C1804 gpio_analog[15] vssa1 2.30fF
-C1805 io_in_3v3[6] vssa1 0.61fF
-C1806 io_in[6] vssa1 0.61fF
-C1807 io_out[6] vssa1 0.61fF
-C1808 io_oeb[6] vssa1 0.61fF
-C1809 io_oeb[21] vssa1 0.61fF
-C1810 io_out[21] vssa1 0.61fF
-C1811 io_in[21] vssa1 0.61fF
-C1812 io_in_3v3[21] vssa1 0.61fF
-C1813 gpio_noesd[14] vssa1 2.30fF
-C1814 gpio_analog[14] vssa1 2.29fF
-C1815 vssd2 vssa1 38.54fF
-C1816 vssd1 vssa1 13.04fF
-C1817 vdda2 vssa1 38.30fF
-C1818 io_oeb[20] vssa1 0.61fF
-C1819 io_out[20] vssa1 0.61fF
-C1820 io_in[20] vssa1 0.61fF
-C1821 io_in_3v3[20] vssa1 0.61fF
-C1822 gpio_noesd[13] vssa1 2.31fF
-C1823 gpio_analog[13] vssa1 2.30fF
-C1824 gpio_analog[0] vssa1 0.61fF
-C1825 gpio_noesd[0] vssa1 0.61fF
-C1826 io_in_3v3[7] vssa1 0.61fF
-C1827 io_in[7] vssa1 0.61fF
-C1828 io_out[7] vssa1 0.61fF
-C1829 io_oeb[7] vssa1 0.61fF
-C1830 io_oeb[19] vssa1 0.61fF
-C1831 io_out[19] vssa1 0.61fF
-C1832 io_in[19] vssa1 0.61fF
-C1833 io_in_3v3[19] vssa1 0.61fF
-C1834 gpio_noesd[12] vssa1 2.32fF
-C1835 gpio_analog[12] vssa1 2.30fF
-C1836 gpio_analog[1] vssa1 0.61fF
-C1837 gpio_noesd[1] vssa1 0.61fF
-C1838 io_in_3v3[8] vssa1 0.61fF
-C1839 io_in[8] vssa1 0.61fF
-C1840 io_out[8] vssa1 0.61fF
-C1841 io_oeb[8] vssa1 0.61fF
-C1842 io_oeb[18] vssa1 0.61fF
-C1843 io_out[18] vssa1 0.61fF
-C1844 io_in[18] vssa1 0.61fF
-C1845 io_in_3v3[18] vssa1 0.61fF
-C1846 gpio_noesd[11] vssa1 2.30fF
-C1847 gpio_analog[11] vssa1 2.29fF
-C1848 gpio_analog[2] vssa1 0.61fF
-C1849 gpio_noesd[2] vssa1 0.61fF
-C1850 io_in_3v3[9] vssa1 0.61fF
-C1851 io_in[9] vssa1 0.61fF
-C1852 io_out[9] vssa1 0.61fF
-C1853 io_oeb[9] vssa1 0.61fF
-C1854 io_oeb[17] vssa1 0.61fF
-C1855 io_out[17] vssa1 0.61fF
-C1856 io_in[17] vssa1 0.61fF
-C1857 io_in_3v3[17] vssa1 0.61fF
-C1858 gpio_noesd[10] vssa1 2.31fF
-C1859 gpio_analog[10] vssa1 2.29fF
-C1860 gpio_analog[3] vssa1 0.61fF
-C1861 gpio_noesd[3] vssa1 0.61fF
-C1862 io_in_3v3[10] vssa1 0.61fF
-C1863 io_in[10] vssa1 0.61fF
-C1864 io_out[10] vssa1 0.61fF
-C1865 io_oeb[10] vssa1 0.61fF
-C1866 io_oeb[16] vssa1 0.61fF
-C1867 io_out[16] vssa1 0.61fF
-C1868 io_in[16] vssa1 0.61fF
-C1869 io_in_3v3[16] vssa1 0.61fF
-C1870 gpio_noesd[9] vssa1 2.28fF
-C1871 gpio_analog[9] vssa1 2.28fF
-C1872 gpio_analog[4] vssa1 0.61fF
-C1873 gpio_noesd[4] vssa1 0.61fF
-C1874 io_in_3v3[11] vssa1 0.61fF
-C1875 io_in[11] vssa1 0.61fF
-C1876 io_out[11] vssa1 0.61fF
-C1877 io_oeb[11] vssa1 0.61fF
-C1878 io_oeb[15] vssa1 0.61fF
-C1879 io_out[15] vssa1 0.61fF
-C1880 io_in[15] vssa1 0.61fF
-C1881 io_in_3v3[15] vssa1 0.61fF
-C1882 gpio_noesd[8] vssa1 2.28fF
-C1883 gpio_analog[8] vssa1 2.26fF
-C1884 gpio_analog[5] vssa1 0.61fF
-C1885 gpio_noesd[5] vssa1 0.61fF
-C1886 io_in_3v3[12] vssa1 0.61fF
-C1887 io_in[12] vssa1 0.61fF
-C1888 io_out[12] vssa1 0.61fF
-C1889 io_oeb[12] vssa1 0.61fF
-C1890 io_oeb[14] vssa1 0.61fF
-C1891 io_out[14] vssa1 0.61fF
-C1892 io_in[14] vssa1 0.61fF
-C1893 io_in_3v3[14] vssa1 0.61fF
-C1894 gpio_noesd[7] vssa1 2.30fF
-C1895 gpio_analog[7] vssa1 2.28fF
-C1896 vssa2 vssa1 38.35fF
-C1897 gpio_analog[6] vssa1 5.71fF
-C1898 gpio_noesd[6] vssa1 5.70fF
-C1899 io_in_3v3[13] vssa1 0.61fF
-C1900 io_in[13] vssa1 0.61fF
-C1901 io_out[13] vssa1 0.61fF
-C1902 io_oeb[13] vssa1 0.61fF
-C1903 vccd1 vssa1 39.84fF
-C1904 vccd2 vssa1 38.46fF
-C1905 io_analog[0] vssa1 19.99fF
-C1906 io_analog[10] vssa1 19.36fF
-C1907 io_analog[1] vssa1 13.17fF
-C1908 io_analog[2] vssa1 12.57fF
-C1909 io_analog[3] vssa1 12.83fF
-C1910 io_clamp_high[0] vssa1 3.58fF
-C1911 io_clamp_low[0] vssa1 3.58fF
-C1912 io_clamp_high[1] vssa1 3.58fF
-C1913 io_clamp_low[1] vssa1 3.58fF
-C1914 io_clamp_high[2] vssa1 3.58fF
-C1915 io_clamp_low[2] vssa1 3.58fF
-C1916 io_analog[7] vssa1 12.74fF
-C1917 io_analog[8] vssa1 13.08fF
-C1918 io_analog[9] vssa1 13.08fF
-C1919 user_irq[2] vssa1 0.63fF
-C1920 user_irq[1] vssa1 0.63fF
-C1921 user_irq[0] vssa1 0.63fF
-C1922 user_clock2 vssa1 0.63fF
-C1923 la_oenb[127] vssa1 0.63fF
-C1924 la_data_out[127] vssa1 0.63fF
-C1925 la_data_in[127] vssa1 0.63fF
-C1926 la_oenb[126] vssa1 0.63fF
-C1927 la_data_out[126] vssa1 0.63fF
-C1928 la_data_in[126] vssa1 0.63fF
-C1929 la_oenb[125] vssa1 0.63fF
-C1930 la_data_out[125] vssa1 0.63fF
-C1931 la_data_in[125] vssa1 0.63fF
-C1932 la_oenb[124] vssa1 0.63fF
-C1933 la_data_out[124] vssa1 0.63fF
-C1934 la_data_in[124] vssa1 0.63fF
-C1935 la_oenb[123] vssa1 0.63fF
-C1936 la_data_out[123] vssa1 0.63fF
-C1937 la_data_in[123] vssa1 0.63fF
-C1938 la_oenb[122] vssa1 0.63fF
-C1939 la_data_out[122] vssa1 0.63fF
-C1940 la_data_in[122] vssa1 0.63fF
-C1941 la_oenb[121] vssa1 0.63fF
-C1942 la_data_out[121] vssa1 0.63fF
-C1943 la_data_in[121] vssa1 0.63fF
-C1944 la_oenb[120] vssa1 0.63fF
-C1945 la_data_out[120] vssa1 0.63fF
-C1946 la_data_in[120] vssa1 0.63fF
-C1947 la_oenb[119] vssa1 0.63fF
-C1948 la_data_out[119] vssa1 0.63fF
-C1949 la_data_in[119] vssa1 0.63fF
-C1950 la_oenb[118] vssa1 0.63fF
-C1951 la_data_out[118] vssa1 0.63fF
-C1952 la_data_in[118] vssa1 0.63fF
-C1953 la_oenb[117] vssa1 0.63fF
-C1954 la_data_out[117] vssa1 0.63fF
-C1955 la_data_in[117] vssa1 0.63fF
-C1956 la_oenb[116] vssa1 0.63fF
-C1957 la_data_out[116] vssa1 0.63fF
-C1958 la_data_in[116] vssa1 0.63fF
-C1959 la_oenb[115] vssa1 0.63fF
-C1960 la_data_out[115] vssa1 0.63fF
-C1961 la_data_in[115] vssa1 0.63fF
-C1962 la_oenb[114] vssa1 0.63fF
-C1963 la_data_out[114] vssa1 0.63fF
-C1964 la_data_in[114] vssa1 0.63fF
-C1965 la_oenb[113] vssa1 0.63fF
-C1966 la_data_out[113] vssa1 0.63fF
-C1967 la_data_in[113] vssa1 0.63fF
-C1968 la_oenb[112] vssa1 0.63fF
-C1969 la_data_out[112] vssa1 0.63fF
-C1970 la_data_in[112] vssa1 0.63fF
-C1971 la_oenb[111] vssa1 0.63fF
-C1972 la_data_out[111] vssa1 0.63fF
-C1973 la_data_in[111] vssa1 0.63fF
-C1974 la_oenb[110] vssa1 0.63fF
-C1975 la_data_out[110] vssa1 0.63fF
-C1976 la_data_in[110] vssa1 0.63fF
-C1977 la_oenb[109] vssa1 0.63fF
-C1978 la_data_out[109] vssa1 0.63fF
-C1979 la_data_in[109] vssa1 0.63fF
-C1980 la_oenb[108] vssa1 0.63fF
-C1981 la_data_out[108] vssa1 0.63fF
-C1982 la_data_in[108] vssa1 0.63fF
-C1983 la_oenb[107] vssa1 0.63fF
-C1984 la_data_out[107] vssa1 0.63fF
-C1985 la_data_in[107] vssa1 0.63fF
-C1986 la_oenb[106] vssa1 0.63fF
-C1987 la_data_out[106] vssa1 0.63fF
-C1988 la_data_in[106] vssa1 0.63fF
-C1989 la_oenb[105] vssa1 0.63fF
-C1990 la_data_out[105] vssa1 0.63fF
-C1991 la_data_in[105] vssa1 0.63fF
-C1992 la_oenb[104] vssa1 0.63fF
-C1993 la_data_out[104] vssa1 0.63fF
-C1994 la_data_in[104] vssa1 0.63fF
-C1995 la_oenb[103] vssa1 0.63fF
-C1996 la_data_out[103] vssa1 0.63fF
-C1997 la_data_in[103] vssa1 0.63fF
-C1998 la_oenb[102] vssa1 0.63fF
-C1999 la_data_out[102] vssa1 0.63fF
-C2000 la_data_in[102] vssa1 0.63fF
-C2001 la_oenb[101] vssa1 0.63fF
-C2002 la_data_out[101] vssa1 0.63fF
-C2003 la_data_in[101] vssa1 0.63fF
-C2004 la_oenb[100] vssa1 0.63fF
-C2005 la_data_out[100] vssa1 0.63fF
-C2006 la_data_in[100] vssa1 0.63fF
-C2007 la_oenb[99] vssa1 0.63fF
-C2008 la_data_out[99] vssa1 0.63fF
-C2009 la_data_in[99] vssa1 0.63fF
-C2010 la_oenb[98] vssa1 0.63fF
-C2011 la_data_out[98] vssa1 0.63fF
-C2012 la_data_in[98] vssa1 0.63fF
-C2013 la_oenb[97] vssa1 0.63fF
-C2014 la_data_out[97] vssa1 0.63fF
-C2015 la_data_in[97] vssa1 0.63fF
-C2016 la_oenb[96] vssa1 0.63fF
-C2017 la_data_out[96] vssa1 0.63fF
-C2018 la_data_in[96] vssa1 0.63fF
-C2019 la_oenb[95] vssa1 0.63fF
-C2020 la_data_out[95] vssa1 0.63fF
-C2021 la_data_in[95] vssa1 0.63fF
-C2022 la_oenb[94] vssa1 0.63fF
-C2023 la_data_out[94] vssa1 0.63fF
-C2024 la_data_in[94] vssa1 0.63fF
-C2025 la_oenb[93] vssa1 0.63fF
-C2026 la_data_out[93] vssa1 0.63fF
-C2027 la_data_in[93] vssa1 0.63fF
-C2028 la_oenb[92] vssa1 0.63fF
-C2029 la_data_out[92] vssa1 0.63fF
-C2030 la_data_in[92] vssa1 0.63fF
-C2031 la_oenb[91] vssa1 0.63fF
-C2032 la_data_out[91] vssa1 0.63fF
-C2033 la_data_in[91] vssa1 0.63fF
-C2034 la_oenb[90] vssa1 0.63fF
-C2035 la_data_out[90] vssa1 0.63fF
-C2036 la_data_in[90] vssa1 0.63fF
-C2037 la_oenb[89] vssa1 0.63fF
-C2038 la_data_out[89] vssa1 0.63fF
-C2039 la_data_in[89] vssa1 0.63fF
-C2040 la_oenb[88] vssa1 0.63fF
-C2041 la_data_out[88] vssa1 0.63fF
-C2042 la_data_in[88] vssa1 0.63fF
-C2043 la_oenb[87] vssa1 0.63fF
-C2044 la_data_out[87] vssa1 0.63fF
-C2045 la_data_in[87] vssa1 0.63fF
-C2046 la_oenb[86] vssa1 0.63fF
-C2047 la_data_out[86] vssa1 0.63fF
-C2048 la_data_in[86] vssa1 0.63fF
-C2049 la_oenb[85] vssa1 0.63fF
-C2050 la_data_out[85] vssa1 0.63fF
-C2051 la_data_in[85] vssa1 0.63fF
-C2052 la_oenb[84] vssa1 0.63fF
-C2053 la_data_out[84] vssa1 0.63fF
-C2054 la_data_in[84] vssa1 0.63fF
-C2055 la_oenb[83] vssa1 0.63fF
-C2056 la_data_out[83] vssa1 0.63fF
-C2057 la_data_in[83] vssa1 0.63fF
-C2058 la_oenb[82] vssa1 0.63fF
-C2059 la_data_out[82] vssa1 0.63fF
-C2060 la_data_in[82] vssa1 0.63fF
-C2061 la_oenb[81] vssa1 0.63fF
-C2062 la_data_out[81] vssa1 0.63fF
-C2063 la_data_in[81] vssa1 0.63fF
-C2064 la_oenb[80] vssa1 0.63fF
-C2065 la_data_out[80] vssa1 0.63fF
-C2066 la_data_in[80] vssa1 0.63fF
-C2067 la_oenb[79] vssa1 0.63fF
-C2068 la_data_out[79] vssa1 0.63fF
-C2069 la_data_in[79] vssa1 0.63fF
-C2070 la_oenb[78] vssa1 0.63fF
-C2071 la_data_out[78] vssa1 0.63fF
-C2072 la_data_in[78] vssa1 0.63fF
-C2073 la_oenb[77] vssa1 0.63fF
-C2074 la_data_out[77] vssa1 0.63fF
-C2075 la_data_in[77] vssa1 0.63fF
-C2076 la_oenb[76] vssa1 0.63fF
-C2077 la_data_out[76] vssa1 0.63fF
-C2078 la_data_in[76] vssa1 0.63fF
-C2079 la_oenb[75] vssa1 0.63fF
-C2080 la_data_out[75] vssa1 0.63fF
-C2081 la_data_in[75] vssa1 0.63fF
-C2082 la_oenb[74] vssa1 0.63fF
-C2083 la_data_out[74] vssa1 0.63fF
-C2084 la_data_in[74] vssa1 0.63fF
-C2085 la_oenb[73] vssa1 0.63fF
-C2086 la_data_out[73] vssa1 0.63fF
-C2087 la_data_in[73] vssa1 0.63fF
-C2088 la_oenb[72] vssa1 0.63fF
-C2089 la_data_out[72] vssa1 0.63fF
-C2090 la_data_in[72] vssa1 0.63fF
-C2091 la_oenb[71] vssa1 0.63fF
-C2092 la_data_out[71] vssa1 0.63fF
-C2093 la_data_in[71] vssa1 0.63fF
-C2094 la_oenb[70] vssa1 0.63fF
-C2095 la_data_out[70] vssa1 0.63fF
-C2096 la_data_in[70] vssa1 0.63fF
-C2097 la_oenb[69] vssa1 0.63fF
-C2098 la_data_out[69] vssa1 0.63fF
-C2099 la_data_in[69] vssa1 0.63fF
-C2100 la_oenb[68] vssa1 0.63fF
-C2101 la_data_out[68] vssa1 0.63fF
-C2102 la_data_in[68] vssa1 0.63fF
-C2103 la_oenb[67] vssa1 0.63fF
-C2104 la_data_out[67] vssa1 0.63fF
-C2105 la_data_in[67] vssa1 0.63fF
-C2106 la_oenb[66] vssa1 0.63fF
-C2107 la_data_out[66] vssa1 0.63fF
-C2108 la_data_in[66] vssa1 0.63fF
-C2109 la_oenb[65] vssa1 0.63fF
-C2110 la_data_out[65] vssa1 0.63fF
-C2111 la_data_in[65] vssa1 0.63fF
-C2112 la_oenb[64] vssa1 0.63fF
-C2113 la_data_out[64] vssa1 0.63fF
-C2114 la_data_in[64] vssa1 0.63fF
-C2115 la_oenb[63] vssa1 0.63fF
-C2116 la_data_out[63] vssa1 0.63fF
-C2117 la_data_in[63] vssa1 0.63fF
-C2118 la_oenb[62] vssa1 0.63fF
-C2119 la_data_out[62] vssa1 0.63fF
-C2120 la_data_in[62] vssa1 0.63fF
-C2121 la_oenb[61] vssa1 0.63fF
-C2122 la_data_out[61] vssa1 0.63fF
-C2123 la_data_in[61] vssa1 0.63fF
-C2124 la_oenb[60] vssa1 0.63fF
-C2125 la_data_out[60] vssa1 0.63fF
-C2126 la_data_in[60] vssa1 0.63fF
-C2127 la_oenb[59] vssa1 0.63fF
-C2128 la_data_out[59] vssa1 0.63fF
-C2129 la_data_in[59] vssa1 0.63fF
-C2130 la_oenb[58] vssa1 0.63fF
-C2131 la_data_out[58] vssa1 0.63fF
-C2132 la_data_in[58] vssa1 0.63fF
-C2133 la_oenb[57] vssa1 0.63fF
-C2134 la_data_out[57] vssa1 0.63fF
-C2135 la_data_in[57] vssa1 0.63fF
-C2136 la_oenb[56] vssa1 0.63fF
-C2137 la_data_out[56] vssa1 0.63fF
-C2138 la_data_in[56] vssa1 0.63fF
-C2139 la_oenb[55] vssa1 0.63fF
-C2140 la_data_out[55] vssa1 0.63fF
-C2141 la_data_in[55] vssa1 0.63fF
-C2142 la_oenb[54] vssa1 0.63fF
-C2143 la_data_out[54] vssa1 0.63fF
-C2144 la_data_in[54] vssa1 0.63fF
-C2145 la_oenb[53] vssa1 0.63fF
-C2146 la_data_out[53] vssa1 0.63fF
-C2147 la_data_in[53] vssa1 0.63fF
-C2148 la_oenb[52] vssa1 0.63fF
-C2149 la_data_out[52] vssa1 0.63fF
-C2150 la_data_in[52] vssa1 0.63fF
-C2151 la_oenb[51] vssa1 0.63fF
-C2152 la_data_out[51] vssa1 0.63fF
-C2153 la_data_in[51] vssa1 0.63fF
-C2154 la_oenb[50] vssa1 0.63fF
-C2155 la_data_out[50] vssa1 0.63fF
-C2156 la_data_in[50] vssa1 0.63fF
-C2157 la_oenb[49] vssa1 0.63fF
-C2158 la_data_out[49] vssa1 0.63fF
-C2159 la_data_in[49] vssa1 0.63fF
-C2160 la_oenb[48] vssa1 0.63fF
-C2161 la_data_out[48] vssa1 0.63fF
-C2162 la_data_in[48] vssa1 0.63fF
-C2163 la_oenb[47] vssa1 0.63fF
-C2164 la_data_out[47] vssa1 0.63fF
-C2165 la_data_in[47] vssa1 0.63fF
-C2166 la_oenb[46] vssa1 0.63fF
-C2167 la_data_out[46] vssa1 0.63fF
-C2168 la_data_in[46] vssa1 0.63fF
-C2169 la_oenb[45] vssa1 0.63fF
-C2170 la_data_out[45] vssa1 0.63fF
-C2171 la_data_in[45] vssa1 0.63fF
-C2172 la_oenb[44] vssa1 0.63fF
-C2173 la_data_out[44] vssa1 0.63fF
-C2174 la_data_in[44] vssa1 0.63fF
-C2175 la_oenb[43] vssa1 0.63fF
-C2176 la_data_out[43] vssa1 0.63fF
-C2177 la_data_in[43] vssa1 0.63fF
-C2178 la_oenb[42] vssa1 0.63fF
-C2179 la_data_out[42] vssa1 0.63fF
-C2180 la_data_in[42] vssa1 0.63fF
-C2181 la_oenb[41] vssa1 0.63fF
-C2182 la_data_out[41] vssa1 0.63fF
-C2183 la_data_in[41] vssa1 0.63fF
-C2184 la_oenb[40] vssa1 0.63fF
-C2185 la_data_out[40] vssa1 0.63fF
-C2186 la_data_in[40] vssa1 0.63fF
-C2187 la_oenb[39] vssa1 0.63fF
-C2188 la_data_out[39] vssa1 0.63fF
-C2189 la_data_in[39] vssa1 0.63fF
-C2190 la_oenb[38] vssa1 0.63fF
-C2191 la_data_out[38] vssa1 0.63fF
-C2192 la_data_in[38] vssa1 0.63fF
-C2193 la_oenb[37] vssa1 0.63fF
-C2194 la_data_out[37] vssa1 0.63fF
-C2195 la_data_in[37] vssa1 0.63fF
-C2196 la_oenb[36] vssa1 0.63fF
-C2197 la_data_out[36] vssa1 0.63fF
-C2198 la_data_in[36] vssa1 0.63fF
-C2199 la_oenb[35] vssa1 0.63fF
-C2200 la_data_out[35] vssa1 0.63fF
-C2201 la_data_in[35] vssa1 0.63fF
-C2202 la_oenb[34] vssa1 0.63fF
-C2203 la_data_out[34] vssa1 0.63fF
-C2204 la_data_in[34] vssa1 0.63fF
-C2205 la_oenb[33] vssa1 0.63fF
-C2206 la_data_out[33] vssa1 0.63fF
-C2207 la_data_in[33] vssa1 0.63fF
-C2208 la_oenb[32] vssa1 0.63fF
-C2209 la_data_out[32] vssa1 0.63fF
-C2210 la_data_in[32] vssa1 0.63fF
-C2211 la_oenb[31] vssa1 0.63fF
-C2212 la_data_out[31] vssa1 0.63fF
-C2213 la_data_in[31] vssa1 0.63fF
-C2214 la_oenb[30] vssa1 0.63fF
-C2215 la_data_out[30] vssa1 0.63fF
-C2216 la_data_in[30] vssa1 0.63fF
-C2217 la_oenb[29] vssa1 0.63fF
-C2218 la_data_out[29] vssa1 0.63fF
-C2219 la_data_in[29] vssa1 0.63fF
-C2220 la_oenb[28] vssa1 0.63fF
-C2221 la_data_out[28] vssa1 0.63fF
-C2222 la_data_in[28] vssa1 0.63fF
-C2223 la_oenb[27] vssa1 0.63fF
-C2224 la_data_out[27] vssa1 0.63fF
-C2225 la_data_in[27] vssa1 0.63fF
-C2226 la_oenb[26] vssa1 0.63fF
-C2227 la_data_out[26] vssa1 0.63fF
-C2228 la_data_in[26] vssa1 0.63fF
-C2229 la_oenb[25] vssa1 0.63fF
-C2230 la_data_out[25] vssa1 0.63fF
-C2231 la_data_in[25] vssa1 0.63fF
-C2232 la_oenb[24] vssa1 0.63fF
-C2233 la_data_out[24] vssa1 0.63fF
-C2234 la_data_in[24] vssa1 0.63fF
-C2235 la_oenb[23] vssa1 0.63fF
-C2236 la_data_out[23] vssa1 0.63fF
-C2237 la_data_in[23] vssa1 0.63fF
-C2238 la_oenb[22] vssa1 0.63fF
-C2239 la_data_out[22] vssa1 0.63fF
-C2240 la_data_in[22] vssa1 0.63fF
-C2241 la_oenb[21] vssa1 0.63fF
-C2242 la_data_out[21] vssa1 0.63fF
-C2243 la_data_in[21] vssa1 0.63fF
-C2244 la_oenb[20] vssa1 0.63fF
-C2245 la_data_out[20] vssa1 0.63fF
-C2246 la_data_in[20] vssa1 0.63fF
-C2247 la_oenb[19] vssa1 0.63fF
-C2248 la_data_out[19] vssa1 0.63fF
-C2249 la_data_in[19] vssa1 0.63fF
-C2250 la_oenb[18] vssa1 0.63fF
-C2251 la_data_out[18] vssa1 0.63fF
-C2252 la_data_in[18] vssa1 0.63fF
-C2253 la_oenb[17] vssa1 0.63fF
-C2254 la_data_out[17] vssa1 0.63fF
-C2255 la_data_in[17] vssa1 0.63fF
-C2256 la_oenb[16] vssa1 0.63fF
-C2257 la_data_out[16] vssa1 0.63fF
-C2258 la_data_in[16] vssa1 0.63fF
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-C2260 la_data_out[15] vssa1 0.63fF
-C2261 la_data_in[15] vssa1 0.63fF
-C2262 la_oenb[14] vssa1 0.63fF
-C2263 la_data_out[14] vssa1 0.63fF
-C2264 la_data_in[14] vssa1 0.63fF
-C2265 la_oenb[13] vssa1 0.63fF
-C2266 la_data_out[13] vssa1 0.63fF
-C2267 la_data_in[13] vssa1 0.63fF
-C2268 la_oenb[12] vssa1 0.63fF
-C2269 la_data_out[12] vssa1 0.63fF
-C2270 la_data_in[12] vssa1 0.63fF
-C2271 la_oenb[11] vssa1 0.63fF
-C2272 la_data_out[11] vssa1 0.63fF
-C2273 la_data_in[11] vssa1 0.63fF
-C2274 la_oenb[10] vssa1 0.63fF
-C2275 la_data_out[10] vssa1 0.63fF
-C2276 la_data_in[10] vssa1 0.63fF
-C2277 la_oenb[9] vssa1 0.63fF
-C2278 la_data_out[9] vssa1 0.63fF
-C2279 la_data_in[9] vssa1 0.63fF
-C2280 la_oenb[8] vssa1 0.63fF
-C2281 la_data_out[8] vssa1 0.63fF
-C2282 la_data_in[8] vssa1 0.63fF
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-C2284 la_data_out[7] vssa1 0.63fF
-C2285 la_data_in[7] vssa1 0.63fF
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-C2287 la_data_out[6] vssa1 0.63fF
-C2288 la_data_in[6] vssa1 0.63fF
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-C2290 la_data_out[5] vssa1 0.63fF
-C2291 la_data_in[5] vssa1 0.63fF
-C2292 la_oenb[4] vssa1 0.63fF
-C2293 la_data_out[4] vssa1 0.63fF
-C2294 la_data_in[4] vssa1 0.63fF
-C2295 la_oenb[3] vssa1 0.63fF
-C2296 la_data_out[3] vssa1 0.63fF
-C2297 la_data_in[3] vssa1 0.63fF
-C2298 la_oenb[2] vssa1 0.63fF
-C2299 la_data_out[2] vssa1 0.63fF
-C2300 la_data_in[2] vssa1 0.63fF
-C2301 la_oenb[1] vssa1 0.63fF
-C2302 la_data_out[1] vssa1 0.63fF
-C2303 la_data_in[1] vssa1 0.63fF
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-C2305 la_data_out[0] vssa1 0.63fF
-C2306 la_data_in[0] vssa1 0.63fF
-C2307 wbs_dat_o[31] vssa1 0.63fF
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-C2310 wbs_dat_o[30] vssa1 0.63fF
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-C2675 divider_2/prescaler_0/tspc_1/Z1 vssa1 0.99fF
-C2676 divider_2/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
-C2677 divider_2/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
-C2678 divider_2/prescaler_0/tspc_0/Z4 vssa1 0.86fF
-C2679 divider_2/prescaler_0/Out vssa1 4.59fF
-C2680 divider_2/prescaler_0/tspc_0/Z3 vssa1 2.26fF
-C2681 divider_2/prescaler_0/tspc_0/Z2 vssa1 1.46fF
-C2682 divider_2/prescaler_0/tspc_0/Z1 vssa1 0.99fF
-C2683 divider_2/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
-C2684 divider_2/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
-C2685 divider_2/nor_1/Z1 vssa1 1.34fF
-C2686 divider_2/nor_0/Z1 vssa1 1.34fF
-C2687 divider_2/mc2 vssa1 5.29fF
-C2688 divider_1/and_0/Z1 vssa1 0.74fF
-C2689 divider_1/and_0/B vssa1 2.25fF
-C2690 divider_1/and_0/A vssa1 2.19fF
-C2691 divider_1/and_0/out1 vssa1 2.93fF
-C2692 divider_1/tspc_2/Z4 vssa1 0.86fF
-C2693 divider_1/Out vssa1 1.60fF
-C2694 divider_1/tspc_2/Z3 vssa1 2.26fF
-C2695 divider_1/tspc_2/Z2 vssa1 1.46fF
-C2696 divider_1/tspc_2/Z1 vssa1 0.99fF
-C2697 divider_1/nor_0/B vssa1 6.44fF
-C2698 divider_1/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
-C2699 divider_1/tspc_1/Z4 vssa1 0.86fF
-C2700 divider_1/tspc_1/Q vssa1 3.12fF
-C2701 divider_1/tspc_1/Z3 vssa1 2.26fF
-C2702 divider_1/tspc_1/Z2 vssa1 1.46fF
-C2703 divider_1/tspc_1/Z1 vssa1 0.99fF
-C2704 divider_1/nor_1/B vssa1 7.05fF
-C2705 divider_1/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
-C2706 divider_1/tspc_0/Z4 vssa1 0.86fF
-C2707 divider_1/tspc_0/Q vssa1 3.14fF
-C2708 divider_1/tspc_0/Z3 vssa1 2.26fF
-C2709 divider_1/tspc_0/Z2 vssa1 1.46fF
-C2710 divider_1/tspc_0/Z1 vssa1 0.99fF
-C2711 divider_1/nor_1/A vssa1 7.04fF
-C2712 divider_1/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
-C2713 divider_1/clk vssa1 5.63fF
-C2714 divider_1/prescaler_0/nand_1/z1 vssa1 0.36fF
-C2715 divider_1/prescaler_0/tspc_0/D vssa1 2.64fF
-C2716 divider_1/prescaler_0/tspc_2/Q vssa1 3.74fF
-C2717 divider_1/prescaler_0/tspc_1/Q vssa1 3.61fF
-C2718 divider_1/prescaler_0/nand_0/z1 vssa1 0.36fF
-C2719 divider_1/prescaler_0/tspc_2/D vssa1 3.12fF
-C2720 divider_1/and_0/OUT vssa1 5.62fF
-C2721 divider_1/prescaler_0/tspc_2/Z4 vssa1 0.86fF
-C2722 divider_1/prescaler_0/tspc_2/Z3 vssa1 2.26fF
-C2723 divider_1/prescaler_0/tspc_2/Z2 vssa1 1.46fF
-C2724 divider_1/prescaler_0/tspc_2/Z1 vssa1 0.99fF
-C2725 divider_1/prescaler_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
-C2726 divider_1/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
-C2727 divider_1/prescaler_0/tspc_1/Z4 vssa1 0.86fF
-C2728 divider_1/prescaler_0/tspc_1/Z3 vssa1 2.26fF
-C2729 divider_1/prescaler_0/tspc_1/Z2 vssa1 1.48fF
-C2730 divider_1/prescaler_0/tspc_1/Z1 vssa1 0.99fF
-C2731 divider_1/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
-C2732 divider_1/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
-C2733 divider_1/prescaler_0/tspc_0/Z4 vssa1 0.86fF
-C2734 divider_1/prescaler_0/Out vssa1 4.59fF
-C2735 divider_1/prescaler_0/tspc_0/Z3 vssa1 2.26fF
-C2736 divider_1/prescaler_0/tspc_0/Z2 vssa1 1.46fF
-C2737 divider_1/prescaler_0/tspc_0/Z1 vssa1 0.99fF
-C2738 divider_1/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
-C2739 divider_1/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
-C2740 divider_1/nor_1/Z1 vssa1 1.34fF
-C2741 divider_1/nor_0/Z1 vssa1 1.34fF
-C2742 divider_1/mc2 vssa1 5.29fF
-C2743 divider_0/and_0/Z1 vssa1 0.74fF
-C2744 divider_0/and_0/B vssa1 2.25fF
-C2745 divider_0/and_0/A vssa1 2.19fF
-C2746 divider_0/and_0/out1 vssa1 2.93fF
-C2747 divider_0/tspc_2/Z4 vssa1 0.86fF
-C2748 divider_0/Out vssa1 1.60fF
-C2749 divider_0/tspc_2/Z3 vssa1 2.26fF
-C2750 divider_0/tspc_2/Z2 vssa1 1.46fF
-C2751 divider_0/tspc_2/Z1 vssa1 0.99fF
-C2752 divider_0/nor_0/B vssa1 6.33fF
-C2753 divider_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
-C2754 divider_0/tspc_1/Z4 vssa1 0.86fF
-C2755 divider_0/tspc_1/Q vssa1 3.12fF
-C2756 divider_0/tspc_1/Z3 vssa1 2.26fF
-C2757 divider_0/tspc_1/Z2 vssa1 1.46fF
-C2758 divider_0/tspc_1/Z1 vssa1 0.99fF
-C2759 divider_0/nor_1/B vssa1 7.05fF
-C2760 divider_0/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
-C2761 divider_0/tspc_0/Z4 vssa1 0.86fF
-C2762 divider_0/tspc_0/Q vssa1 3.14fF
-C2763 divider_0/tspc_0/Z3 vssa1 2.26fF
-C2764 divider_0/tspc_0/Z2 vssa1 1.46fF
-C2765 divider_0/tspc_0/Z1 vssa1 0.99fF
-C2766 divider_0/nor_1/A vssa1 7.04fF
-C2767 divider_0/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
-C2768 divider_0/clk vssa1 5.63fF
-C2769 divider_0/prescaler_0/nand_1/z1 vssa1 0.36fF
-C2770 divider_0/prescaler_0/tspc_0/D vssa1 2.64fF
-C2771 divider_0/prescaler_0/tspc_2/Q vssa1 3.64fF
-C2772 divider_0/prescaler_0/tspc_1/Q vssa1 3.61fF
-C2773 divider_0/prescaler_0/nand_0/z1 vssa1 0.36fF
-C2774 divider_0/prescaler_0/tspc_2/D vssa1 3.12fF
-C2775 divider_0/and_0/OUT vssa1 5.62fF
-C2776 divider_0/prescaler_0/tspc_2/Z4 vssa1 0.86fF
-C2777 divider_0/prescaler_0/tspc_2/Z3 vssa1 2.26fF
-C2778 divider_0/prescaler_0/tspc_2/Z2 vssa1 1.46fF
-C2779 divider_0/prescaler_0/tspc_2/Z1 vssa1 0.99fF
-C2780 divider_0/prescaler_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
-C2781 divider_0/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
-C2782 divider_0/prescaler_0/tspc_1/Z4 vssa1 0.86fF
-C2783 divider_0/prescaler_0/tspc_1/Z3 vssa1 2.26fF
-C2784 divider_0/prescaler_0/tspc_1/Z2 vssa1 1.48fF
-C2785 divider_0/prescaler_0/tspc_1/Z1 vssa1 0.99fF
-C2786 divider_0/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
-C2787 divider_0/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
-C2788 divider_0/prescaler_0/tspc_0/Z4 vssa1 0.86fF
-C2789 divider_0/prescaler_0/Out vssa1 4.59fF
-C2790 divider_0/prescaler_0/tspc_0/Z3 vssa1 2.26fF
-C2791 divider_0/prescaler_0/tspc_0/Z2 vssa1 1.46fF
-C2792 divider_0/prescaler_0/tspc_0/Z1 vssa1 0.99fF
-C2793 divider_0/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
-C2794 divider_0/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
-C2795 divider_0/nor_1/Z1 vssa1 1.34fF
-C2796 divider_0/nor_0/Z1 vssa1 1.34fF
-C2797 divider_0/mc2 vssa1 5.29fF
-C2798 ro_complete_buffered_0/tapered_buf_0/in vssa1 1.13fF
-C2799 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# vssa1 0.06fF **FLOATING
-C2800 ro_complete_buffered_0/tapered_buf_0/a_210_n610# vssa1 588.54fF **FLOATING
-C2801 ro_complete_buffered_0/tapered_buf_0/a_160_230# vssa1 0.15fF **FLOATING
-C2802 ro_complete_buffered_0/tapered_buf_0/a_n10_230# vssa1 0.13fF **FLOATING
-C2803 ro_complete_buffered_0/tapered_buf_0/a_4670_0# vssa1 250.63fF **FLOATING
-C2804 ro_complete_buffered_0/tapered_buf_0/a_1650_0# vssa1 63.04fF **FLOATING
-C2805 ro_complete_buffered_0/tapered_buf_0/a_580_0# vssa1 16.64fF **FLOATING
-C2806 ro_complete_buffered_0/tapered_buf_0/a_160_n140# vssa1 4.00fF **FLOATING
-C2807 gnd vssa1 96.41fF
-C2808 ro_complete_buffered_0/tapered_buf_1/in vssa1 1.09fF
-C2809 ro_complete_buffered_0/tapered_buf_1/a_n10_n140# vssa1 0.06fF **FLOATING
-C2810 ro_complete_buffered_0/tapered_buf_1/a_210_n610# vssa1 376.11fF **FLOATING
-C2811 ro_complete_buffered_0/tapered_buf_1/a_160_230# vssa1 0.15fF **FLOATING
-C2812 ro_complete_buffered_0/tapered_buf_1/a_n10_230# vssa1 0.13fF **FLOATING
-C2813 ro_complete_buffered_0/tapered_buf_1/a_4670_0# vssa1 168.15fF **FLOATING
-C2814 ro_complete_buffered_0/tapered_buf_1/a_1650_0# vssa1 42.34fF **FLOATING
-C2815 ro_complete_buffered_0/tapered_buf_1/a_580_0# vssa1 10.93fF **FLOATING
-C2816 ro_complete_buffered_0/tapered_buf_1/a_160_n140# vssa1 2.66fF **FLOATING
-C2817 ro_complete_buffered_0/ro_complete_0/cbank_2/v vssa1 16.53fF
-C2818 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin vssa1 0.78fF
-C2819 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin vssa1 1.50fF
-C2820 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin vssa1 1.30fF
-C2821 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin vssa1 0.56fF
-C2822 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin vssa1 1.14fF
-C2823 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin vssa1 1.02fF
-C2824 ro_complete_buffered_0/tapered_buf_6/in vssa1 23.85fF
-C2825 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin vssa1 0.78fF
-C2826 ro_complete_buffered_0/ro_complete_0/a0 vssa1 415.68fF
-C2827 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin vssa1 1.50fF
-C2828 ro_complete_buffered_0/ro_complete_0/a1 vssa1 411.44fF
-C2829 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin vssa1 1.30fF
-C2830 ro_complete_buffered_0/ro_complete_0/a3 vssa1 403.90fF
-C2831 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin vssa1 0.56fF
-C2832 ro_complete_buffered_0/ro_complete_0/a2 vssa1 407.33fF
-C2833 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin vssa1 1.14fF
-C2834 ro_complete_buffered_0/ro_complete_0/a4 vssa1 313.18fF
-C2835 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin vssa1 1.02fF
-C2836 ro_complete_buffered_0/ro_complete_0/a5 vssa1 400.20fF
-C2837 ro_complete_buffered_0/ro_complete_0/cbank_0/v vssa1 15.13fF
-C2838 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin vssa1 0.78fF
-C2839 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin vssa1 1.50fF
-C2840 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin vssa1 1.30fF
-C2841 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin vssa1 0.56fF
-C2842 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin vssa1 1.14fF
-C2843 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin vssa1 1.02fF
-C2844 ro_complete_buffered_0/tapered_buf_7/in vssa1 1.13fF
-C2845 ro_complete_buffered_0/tapered_buf_7/a_n10_n140# vssa1 0.06fF **FLOATING
-C2846 ro_complete_buffered_0/tapered_buf_7/a_210_n610# vssa1 614.83fF **FLOATING
-C2847 ro_complete_buffered_0/tapered_buf_7/a_160_230# vssa1 0.15fF **FLOATING
-C2848 ro_complete_buffered_0/tapered_buf_7/a_n10_230# vssa1 0.13fF **FLOATING
-C2849 ro_complete_buffered_0/tapered_buf_7/a_4670_0# vssa1 250.63fF **FLOATING
-C2850 ro_complete_buffered_0/tapered_buf_7/a_1650_0# vssa1 63.04fF **FLOATING
-C2851 ro_complete_buffered_0/tapered_buf_7/a_580_0# vssa1 16.64fF **FLOATING
-C2852 ro_complete_buffered_0/tapered_buf_7/a_160_n140# vssa1 4.00fF **FLOATING
-C2853 ro_complete_buffered_0/tapered_buf_6/out vssa1 385.11fF
-C2854 ro_complete_buffered_0/tapered_buf_6/a_n10_n140# vssa1 0.06fF **FLOATING
-C2855 ro_complete_buffered_0/tapered_buf_6/a_210_n610# vssa1 588.54fF **FLOATING
-C2856 ro_complete_buffered_0/tapered_buf_6/a_160_230# vssa1 0.15fF **FLOATING
-C2857 ro_complete_buffered_0/tapered_buf_6/a_n10_230# vssa1 0.13fF **FLOATING
-C2858 ro_complete_buffered_0/tapered_buf_6/a_4670_0# vssa1 250.63fF **FLOATING
-C2859 ro_complete_buffered_0/tapered_buf_6/a_1650_0# vssa1 63.04fF **FLOATING
-C2860 ro_complete_buffered_0/tapered_buf_6/a_580_0# vssa1 16.64fF **FLOATING
-C2861 ro_complete_buffered_0/tapered_buf_6/a_160_n140# vssa1 4.00fF **FLOATING
-C2862 ro_complete_buffered_0/tapered_buf_5/in vssa1 1.13fF
-C2863 ro_complete_buffered_0/tapered_buf_5/a_n10_n140# vssa1 0.06fF **FLOATING
-C2864 ro_complete_buffered_0/tapered_buf_5/a_210_n610# vssa1 588.54fF **FLOATING
-C2865 ro_complete_buffered_0/tapered_buf_5/a_160_230# vssa1 0.15fF **FLOATING
-C2866 ro_complete_buffered_0/tapered_buf_5/a_n10_230# vssa1 0.13fF **FLOATING
-C2867 ro_complete_buffered_0/tapered_buf_5/a_4670_0# vssa1 250.63fF **FLOATING
-C2868 ro_complete_buffered_0/tapered_buf_5/a_1650_0# vssa1 63.04fF **FLOATING
-C2869 ro_complete_buffered_0/tapered_buf_5/a_580_0# vssa1 16.64fF **FLOATING
-C2870 ro_complete_buffered_0/tapered_buf_5/a_160_n140# vssa1 4.00fF **FLOATING
-C2871 ro_complete_buffered_0/tapered_buf_4/in vssa1 1.13fF
-C2872 ro_complete_buffered_0/tapered_buf_4/a_n10_n140# vssa1 0.06fF **FLOATING
-C2873 ro_complete_buffered_0/tapered_buf_4/a_210_n610# vssa1 588.54fF **FLOATING
-C2874 ro_complete_buffered_0/tapered_buf_4/a_160_230# vssa1 0.15fF **FLOATING
-C2875 ro_complete_buffered_0/tapered_buf_4/a_n10_230# vssa1 0.13fF **FLOATING
-C2876 ro_complete_buffered_0/tapered_buf_4/a_4670_0# vssa1 250.63fF **FLOATING
-C2877 ro_complete_buffered_0/tapered_buf_4/a_1650_0# vssa1 63.04fF **FLOATING
-C2878 ro_complete_buffered_0/tapered_buf_4/a_580_0# vssa1 16.64fF **FLOATING
-C2879 ro_complete_buffered_0/tapered_buf_4/a_160_n140# vssa1 4.00fF **FLOATING
-C2880 ro_complete_buffered_0/tapered_buf_3/in vssa1 1.13fF
-C2881 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# vssa1 0.06fF **FLOATING
-C2882 ro_complete_buffered_0/tapered_buf_3/a_210_n610# vssa1 588.54fF **FLOATING
-C2883 ro_complete_buffered_0/tapered_buf_3/a_160_230# vssa1 0.15fF **FLOATING
-C2884 ro_complete_buffered_0/tapered_buf_3/a_n10_230# vssa1 0.13fF **FLOATING
-C2885 ro_complete_buffered_0/tapered_buf_3/a_4670_0# vssa1 250.63fF **FLOATING
-C2886 ro_complete_buffered_0/tapered_buf_3/a_1650_0# vssa1 63.04fF **FLOATING
-C2887 ro_complete_buffered_0/tapered_buf_3/a_580_0# vssa1 16.64fF **FLOATING
-C2888 ro_complete_buffered_0/tapered_buf_3/a_160_n140# vssa1 4.00fF **FLOATING
-C2889 ro_complete_buffered_0/tapered_buf_2/in vssa1 1.13fF
-C2890 ro_complete_buffered_0/tapered_buf_2/a_n10_n140# vssa1 0.06fF **FLOATING
-C2891 ro_complete_buffered_0/tapered_buf_2/a_210_n610# vssa1 588.54fF **FLOATING
-C2892 ro_complete_buffered_0/tapered_buf_2/a_160_230# vssa1 0.15fF **FLOATING
-C2893 ro_complete_buffered_0/tapered_buf_2/a_n10_230# vssa1 0.13fF **FLOATING
-C2894 ro_complete_buffered_0/tapered_buf_2/a_4670_0# vssa1 250.63fF **FLOATING
-C2895 ro_complete_buffered_0/tapered_buf_2/a_1650_0# vssa1 63.04fF **FLOATING
-C2896 ro_complete_buffered_0/tapered_buf_2/a_580_0# vssa1 16.64fF **FLOATING
-C2897 ro_complete_buffered_0/tapered_buf_2/a_160_n140# vssa1 4.00fF **FLOATING
-C2898 ro_complete_0/cbank_2/v vssa1 16.43fF
-C2899 ro_complete_0/cbank_2/switch_5/vin vssa1 0.78fF
-C2900 ro_complete_0/cbank_2/switch_4/vin vssa1 1.50fF
-C2901 ro_complete_0/cbank_2/switch_2/vin vssa1 1.30fF
-C2902 ro_complete_0/cbank_2/switch_3/vin vssa1 0.56fF
-C2903 ro_complete_0/cbank_2/switch_1/vin vssa1 1.14fF
-C2904 ro_complete_0/cbank_2/switch_0/vin vssa1 1.02fF
-C2905 ro_complete_0/cbank_1/v vssa1 16.43fF
-C2906 ro_complete_0/cbank_1/switch_5/vin vssa1 0.78fF
-C2907 ro_complete_0/a0 vssa1 5.35fF
-C2908 ro_complete_0/cbank_1/switch_4/vin vssa1 1.50fF
-C2909 ro_complete_0/a1 vssa1 6.54fF
-C2910 ro_complete_0/cbank_1/switch_2/vin vssa1 1.30fF
-C2911 ro_complete_0/a3 vssa1 5.96fF
-C2912 ro_complete_0/cbank_1/switch_3/vin vssa1 0.56fF
-C2913 ro_complete_0/a2 vssa1 5.21fF
-C2914 ro_complete_0/cbank_1/switch_1/vin vssa1 1.14fF
-C2915 ro_complete_0/a4 vssa1 5.81fF
-C2916 ro_complete_0/cbank_1/switch_0/vin vssa1 1.02fF
-C2917 ro_complete_0/a5 vssa1 6.74fF
-C2918 ro_complete_0/cbank_0/v vssa1 15.12fF
-C2919 ro_complete_0/cbank_0/switch_5/vin vssa1 0.78fF
-C2920 ro_complete_0/cbank_0/switch_4/vin vssa1 1.50fF
-C2921 ro_complete_0/cbank_0/switch_2/vin vssa1 1.30fF
-C2922 ro_complete_0/cbank_0/switch_3/vin vssa1 0.56fF
-C2923 ro_complete_0/cbank_0/switch_1/vin vssa1 1.14fF
-C2924 ro_complete_0/cbank_0/switch_0/vin vssa1 1.02fF
-C2925 filter_0/v vssa1 113.61fF
-C2926 filter_0/a_4216_n5230# vssa1 418.47fF **FLOATING
-C2927 filter_0/a_4216_n2998# vssa1 1.03fF **FLOATING
-C2928 cp_0/down vssa1 1.54fF
-C2929 cp_0/vbias vssa1 2.41fF
-C2930 cp_0/out vssa1 5.34fF
-C2931 cp_0/upbar vssa1 1.50fF
-C2932 cp_0/a_7110_n2840# vssa1 0.17fF **FLOATING
-C2933 cp_0/a_3060_n2840# vssa1 1.71fF **FLOATING
-C2934 cp_0/a_7110_0# vssa1 0.17fF **FLOATING
-C2935 cp_0/a_6370_0# vssa1 0.40fF **FLOATING
-C2936 cp_0/a_3060_0# vssa1 1.66fF **FLOATING
-C2937 cp_0/a_1710_0# vssa1 5.89fF **FLOATING
-C2938 cp_0/a_1710_n2840# vssa1 4.91fF **FLOATING
-C2939 cp_0/a_10_n50# vssa1 2.96fF **FLOATING
-C2940 pd_1/UP vssa1 2.21fF
-C2941 pd_1/and_pd_0/Z1 vssa1 0.39fF
-C2942 pd_1/and_pd_0/Out1 vssa1 2.22fF
-C2943 pd_1/tspc_r_1/z5 vssa1 1.10fF
-C2944 pd_1/tspc_r_1/Z4 vssa1 1.07fF
-C2945 pd_1/R vssa1 3.05fF
-C2946 pd_1/tspc_r_1/Qbar vssa1 0.79fF
-C2947 pd_1/tspc_r_1/Z2 vssa1 1.22fF
-C2948 pd_1/tspc_r_1/Z1 vssa1 0.67fF
-C2949 pd_1/DOWN vssa1 3.08fF
-C2950 pd_1/tspc_r_1/Qbar1 vssa1 1.34fF
-C2951 pd_1/tspc_r_1/Z3 vssa1 2.12fF
-C2952 pd_1/DIV vssa1 1.82fF
-C2953 pd_1/tspc_r_0/z5 vssa1 1.10fF
-C2954 pd_1/tspc_r_0/Z4 vssa1 1.07fF
-C2955 pd_1/tspc_r_0/Qbar vssa1 0.88fF
-C2956 pd_1/tspc_r_0/Z2 vssa1 1.22fF
-C2957 pd_1/tspc_r_0/Z1 vssa1 0.67fF
-C2958 pd_1/tspc_r_0/Qbar1 vssa1 1.34fF
-C2959 pd_1/tspc_r_0/Z3 vssa1 2.12fF
-C2960 pd_1/REF vssa1 1.80fF
-C2961 pd_0/UP vssa1 2.21fF
-C2962 pd_0/and_pd_0/Z1 vssa1 0.39fF
-C2963 pd_0/and_pd_0/Out1 vssa1 2.22fF
-C2964 pd_0/tspc_r_1/z5 vssa1 1.10fF
-C2965 pd_0/tspc_r_1/Z4 vssa1 1.07fF
-C2966 pd_0/R vssa1 3.05fF
-C2967 pd_0/tspc_r_1/Qbar vssa1 0.79fF
-C2968 pd_0/tspc_r_1/Z2 vssa1 1.22fF
-C2969 pd_0/tspc_r_1/Z1 vssa1 0.67fF
-C2970 pd_0/DOWN vssa1 3.08fF
-C2971 pd_0/tspc_r_1/Qbar1 vssa1 1.34fF
-C2972 pd_0/tspc_r_1/Z3 vssa1 2.12fF
-C2973 pd_0/DIV vssa1 1.82fF
-C2974 pd_0/tspc_r_0/z5 vssa1 1.10fF
-C2975 pd_0/tspc_r_0/Z4 vssa1 1.07fF
-C2976 pd_0/tspc_r_0/Qbar vssa1 0.88fF
-C2977 pd_0/tspc_r_0/Z2 vssa1 1.22fF
-C2978 pd_0/tspc_r_0/Z1 vssa1 0.67fF
-C2979 pd_0/tspc_r_0/Qbar1 vssa1 1.34fF
-C2980 pd_0/tspc_r_0/Z3 vssa1 2.12fF
-C2981 pd_0/REF vssa1 1.80fF
+C1866 io_analog[4] vssa1 43.96fF
+C1867 io_analog[5] vssa1 44.13fF
+C1868 io_analog[6] vssa1 43.46fF
+C1869 io_in_3v3[0] vssa1 0.61fF
+C1870 io_oeb[26] vssa1 0.61fF
+C1871 io_in[0] vssa1 0.61fF
+C1872 io_out[26] vssa1 0.61fF
+C1873 io_out[0] vssa1 0.61fF
+C1874 io_in[26] vssa1 0.61fF
+C1875 io_oeb[0] vssa1 0.61fF
+C1876 io_in_3v3[26] vssa1 0.61fF
+C1877 io_in_3v3[1] vssa1 0.61fF
+C1878 io_oeb[25] vssa1 0.61fF
+C1879 io_in[1] vssa1 0.61fF
+C1880 io_out[25] vssa1 0.61fF
+C1881 io_out[1] vssa1 0.61fF
+C1882 io_in[25] vssa1 0.61fF
+C1883 io_oeb[1] vssa1 0.61fF
+C1884 io_in_3v3[25] vssa1 0.61fF
+C1885 io_in_3v3[2] vssa1 0.61fF
+C1886 io_oeb[24] vssa1 0.61fF
+C1887 io_in[2] vssa1 0.61fF
+C1888 io_out[24] vssa1 0.61fF
+C1889 io_out[2] vssa1 0.61fF
+C1890 io_in[24] vssa1 0.61fF
+C1891 io_oeb[2] vssa1 0.61fF
+C1892 io_in_3v3[24] vssa1 0.61fF
+C1893 io_in_3v3[3] vssa1 0.61fF
+C1894 gpio_noesd[17] vssa1 2.32fF
+C1895 io_in[3] vssa1 0.61fF
+C1896 gpio_analog[17] vssa1 2.30fF
+C1897 io_out[3] vssa1 0.61fF
+C1898 io_oeb[3] vssa1 0.61fF
+C1899 io_in_3v3[4] vssa1 0.61fF
+C1900 io_in[4] vssa1 0.61fF
+C1901 io_out[4] vssa1 0.61fF
+C1902 io_oeb[4] vssa1 0.61fF
+C1903 io_oeb[23] vssa1 0.61fF
+C1904 io_out[23] vssa1 0.61fF
+C1905 io_in[23] vssa1 0.61fF
+C1906 io_in_3v3[23] vssa1 0.61fF
+C1907 gpio_noesd[16] vssa1 2.30fF
+C1908 gpio_analog[16] vssa1 2.30fF
+C1909 io_in_3v3[5] vssa1 0.61fF
+C1910 io_in[5] vssa1 0.61fF
+C1911 io_out[5] vssa1 0.61fF
+C1912 io_oeb[5] vssa1 0.61fF
+C1913 io_oeb[22] vssa1 0.61fF
+C1914 io_out[22] vssa1 0.61fF
+C1915 io_in[22] vssa1 0.61fF
+C1916 io_in_3v3[22] vssa1 0.61fF
+C1917 gpio_noesd[15] vssa1 2.31fF
+C1918 gpio_analog[15] vssa1 2.30fF
+C1919 io_in_3v3[6] vssa1 0.61fF
+C1920 io_in[6] vssa1 0.61fF
+C1921 io_out[6] vssa1 0.61fF
+C1922 io_oeb[6] vssa1 0.61fF
+C1923 io_oeb[21] vssa1 0.61fF
+C1924 io_out[21] vssa1 0.61fF
+C1925 io_in[21] vssa1 0.61fF
+C1926 io_in_3v3[21] vssa1 0.61fF
+C1927 gpio_noesd[14] vssa1 2.30fF
+C1928 gpio_analog[14] vssa1 2.29fF
+C1929 vssd2 vssa1 38.54fF
+C1930 vssd1 vssa1 13.04fF
+C1931 vdda2 vssa1 38.30fF
+C1932 io_oeb[20] vssa1 0.61fF
+C1933 io_out[20] vssa1 0.61fF
+C1934 io_in[20] vssa1 0.61fF
+C1935 io_in_3v3[20] vssa1 0.61fF
+C1936 gpio_noesd[13] vssa1 2.31fF
+C1937 gpio_analog[13] vssa1 2.30fF
+C1938 gpio_analog[0] vssa1 0.61fF
+C1939 gpio_noesd[0] vssa1 0.61fF
+C1940 io_in_3v3[7] vssa1 0.61fF
+C1941 io_in[7] vssa1 0.61fF
+C1942 io_out[7] vssa1 0.61fF
+C1943 io_oeb[7] vssa1 0.61fF
+C1944 io_oeb[19] vssa1 0.61fF
+C1945 io_out[19] vssa1 0.61fF
+C1946 io_in[19] vssa1 0.61fF
+C1947 io_in_3v3[19] vssa1 0.61fF
+C1948 gpio_noesd[12] vssa1 2.32fF
+C1949 gpio_analog[12] vssa1 2.30fF
+C1950 gpio_analog[1] vssa1 0.61fF
+C1951 gpio_noesd[1] vssa1 0.61fF
+C1952 io_in_3v3[8] vssa1 0.61fF
+C1953 io_in[8] vssa1 0.61fF
+C1954 io_out[8] vssa1 0.61fF
+C1955 io_oeb[8] vssa1 0.61fF
+C1956 io_oeb[18] vssa1 0.61fF
+C1957 io_out[18] vssa1 0.61fF
+C1958 io_in[18] vssa1 0.61fF
+C1959 io_in_3v3[18] vssa1 0.61fF
+C1960 gpio_noesd[11] vssa1 2.30fF
+C1961 gpio_analog[11] vssa1 2.29fF
+C1962 gpio_analog[2] vssa1 0.61fF
+C1963 gpio_noesd[2] vssa1 0.61fF
+C1964 io_in_3v3[9] vssa1 0.61fF
+C1965 io_in[9] vssa1 0.61fF
+C1966 io_out[9] vssa1 0.61fF
+C1967 io_oeb[9] vssa1 0.61fF
+C1968 io_oeb[17] vssa1 0.61fF
+C1969 io_out[17] vssa1 0.61fF
+C1970 io_in[17] vssa1 0.61fF
+C1971 io_in_3v3[17] vssa1 0.61fF
+C1972 gpio_noesd[10] vssa1 2.31fF
+C1973 gpio_analog[10] vssa1 2.29fF
+C1974 gpio_analog[3] vssa1 0.61fF
+C1975 gpio_noesd[3] vssa1 0.61fF
+C1976 io_in_3v3[10] vssa1 0.61fF
+C1977 io_in[10] vssa1 0.61fF
+C1978 io_out[10] vssa1 0.61fF
+C1979 io_oeb[10] vssa1 0.61fF
+C1980 io_oeb[16] vssa1 0.61fF
+C1981 io_out[16] vssa1 0.61fF
+C1982 io_in[16] vssa1 0.61fF
+C1983 io_in_3v3[16] vssa1 0.61fF
+C1984 gpio_noesd[9] vssa1 2.28fF
+C1985 gpio_analog[9] vssa1 2.28fF
+C1986 gpio_analog[4] vssa1 0.61fF
+C1987 gpio_noesd[4] vssa1 0.61fF
+C1988 io_in_3v3[11] vssa1 0.61fF
+C1989 io_in[11] vssa1 0.61fF
+C1990 io_out[11] vssa1 0.61fF
+C1991 io_oeb[11] vssa1 0.61fF
+C1992 io_oeb[15] vssa1 0.61fF
+C1993 io_out[15] vssa1 0.61fF
+C1994 io_in[15] vssa1 0.61fF
+C1995 io_in_3v3[15] vssa1 0.61fF
+C1996 gpio_noesd[8] vssa1 2.28fF
+C1997 gpio_analog[8] vssa1 2.26fF
+C1998 gpio_analog[5] vssa1 0.61fF
+C1999 gpio_noesd[5] vssa1 0.61fF
+C2000 io_in_3v3[12] vssa1 0.61fF
+C2001 io_in[12] vssa1 0.61fF
+C2002 io_out[12] vssa1 0.61fF
+C2003 io_oeb[12] vssa1 0.61fF
+C2004 io_oeb[14] vssa1 0.61fF
+C2005 io_out[14] vssa1 0.61fF
+C2006 io_in[14] vssa1 0.61fF
+C2007 io_in_3v3[14] vssa1 0.61fF
+C2008 gpio_noesd[7] vssa1 2.30fF
+C2009 gpio_analog[7] vssa1 2.28fF
+C2010 vssa2 vssa1 38.35fF
+C2011 gpio_analog[6] vssa1 5.71fF
+C2012 gpio_noesd[6] vssa1 5.70fF
+C2013 io_in_3v3[13] vssa1 0.61fF
+C2014 io_in[13] vssa1 0.61fF
+C2015 io_out[13] vssa1 0.61fF
+C2016 io_oeb[13] vssa1 0.61fF
+C2017 vccd1 vssa1 39.84fF
+C2018 vccd2 vssa1 38.46fF
+C2019 io_analog[0] vssa1 19.99fF
+C2020 io_analog[10] vssa1 19.36fF
+C2021 io_analog[1] vssa1 13.17fF
+C2022 io_analog[2] vssa1 12.57fF
+C2023 io_analog[3] vssa1 12.83fF
+C2024 io_clamp_high[0] vssa1 3.58fF
+C2025 io_clamp_low[0] vssa1 3.58fF
+C2026 io_clamp_high[1] vssa1 3.58fF
+C2027 io_clamp_low[1] vssa1 3.58fF
+C2028 io_clamp_high[2] vssa1 3.58fF
+C2029 io_clamp_low[2] vssa1 3.58fF
+C2030 io_analog[7] vssa1 12.74fF
+C2031 io_analog[8] vssa1 13.08fF
+C2032 io_analog[9] vssa1 13.08fF
+C2033 user_irq[2] vssa1 0.63fF
+C2034 user_irq[1] vssa1 0.63fF
+C2035 user_irq[0] vssa1 0.63fF
+C2036 user_clock2 vssa1 0.63fF
+C2037 la_oenb[127] vssa1 0.63fF
+C2038 la_data_out[127] vssa1 0.63fF
+C2039 la_data_in[127] vssa1 0.63fF
+C2040 la_oenb[126] vssa1 0.63fF
+C2041 la_data_out[126] vssa1 0.63fF
+C2042 la_data_in[126] vssa1 0.63fF
+C2043 la_oenb[125] vssa1 0.63fF
+C2044 la_data_out[125] vssa1 0.63fF
+C2045 la_data_in[125] vssa1 0.63fF
+C2046 la_oenb[124] vssa1 0.63fF
+C2047 la_data_out[124] vssa1 0.63fF
+C2048 la_data_in[124] vssa1 0.63fF
+C2049 la_oenb[123] vssa1 0.63fF
+C2050 la_data_out[123] vssa1 0.63fF
+C2051 la_data_in[123] vssa1 0.63fF
+C2052 la_oenb[122] vssa1 0.63fF
+C2053 la_data_out[122] vssa1 0.63fF
+C2054 la_data_in[122] vssa1 0.63fF
+C2055 la_oenb[121] vssa1 0.63fF
+C2056 la_data_out[121] vssa1 0.63fF
+C2057 la_data_in[121] vssa1 0.63fF
+C2058 la_oenb[120] vssa1 0.63fF
+C2059 la_data_out[120] vssa1 0.63fF
+C2060 la_data_in[120] vssa1 0.63fF
+C2061 la_oenb[119] vssa1 0.63fF
+C2062 la_data_out[119] vssa1 0.63fF
+C2063 la_data_in[119] vssa1 0.63fF
+C2064 la_oenb[118] vssa1 0.63fF
+C2065 la_data_out[118] vssa1 0.63fF
+C2066 la_data_in[118] vssa1 0.63fF
+C2067 la_oenb[117] vssa1 0.63fF
+C2068 la_data_out[117] vssa1 0.63fF
+C2069 la_data_in[117] vssa1 0.63fF
+C2070 la_oenb[116] vssa1 0.63fF
+C2071 la_data_out[116] vssa1 0.63fF
+C2072 la_data_in[116] vssa1 0.63fF
+C2073 la_oenb[115] vssa1 0.63fF
+C2074 la_data_out[115] vssa1 0.63fF
+C2075 la_data_in[115] vssa1 0.63fF
+C2076 la_oenb[114] vssa1 0.63fF
+C2077 la_data_out[114] vssa1 0.63fF
+C2078 la_data_in[114] vssa1 0.63fF
+C2079 la_oenb[113] vssa1 0.63fF
+C2080 la_data_out[113] vssa1 0.63fF
+C2081 la_data_in[113] vssa1 0.63fF
+C2082 la_oenb[112] vssa1 0.63fF
+C2083 la_data_out[112] vssa1 0.63fF
+C2084 la_data_in[112] vssa1 0.63fF
+C2085 la_oenb[111] vssa1 0.63fF
+C2086 la_data_out[111] vssa1 0.63fF
+C2087 la_data_in[111] vssa1 0.63fF
+C2088 la_oenb[110] vssa1 0.63fF
+C2089 la_data_out[110] vssa1 0.63fF
+C2090 la_data_in[110] vssa1 0.63fF
+C2091 la_oenb[109] vssa1 0.63fF
+C2092 la_data_out[109] vssa1 0.63fF
+C2093 la_data_in[109] vssa1 0.63fF
+C2094 la_oenb[108] vssa1 0.63fF
+C2095 la_data_out[108] vssa1 0.63fF
+C2096 la_data_in[108] vssa1 0.63fF
+C2097 la_oenb[107] vssa1 0.63fF
+C2098 la_data_out[107] vssa1 0.63fF
+C2099 la_data_in[107] vssa1 0.63fF
+C2100 la_oenb[106] vssa1 0.63fF
+C2101 la_data_out[106] vssa1 0.63fF
+C2102 la_data_in[106] vssa1 0.63fF
+C2103 la_oenb[105] vssa1 0.63fF
+C2104 la_data_out[105] vssa1 0.63fF
+C2105 la_data_in[105] vssa1 0.63fF
+C2106 la_oenb[104] vssa1 0.63fF
+C2107 la_data_out[104] vssa1 0.63fF
+C2108 la_data_in[104] vssa1 0.63fF
+C2109 la_oenb[103] vssa1 0.63fF
+C2110 la_data_out[103] vssa1 0.63fF
+C2111 la_data_in[103] vssa1 0.63fF
+C2112 la_oenb[102] vssa1 0.63fF
+C2113 la_data_out[102] vssa1 0.63fF
+C2114 la_data_in[102] vssa1 0.63fF
+C2115 la_oenb[101] vssa1 0.63fF
+C2116 la_data_out[101] vssa1 0.63fF
+C2117 la_data_in[101] vssa1 0.63fF
+C2118 la_oenb[100] vssa1 0.63fF
+C2119 la_data_out[100] vssa1 0.63fF
+C2120 la_data_in[100] vssa1 0.63fF
+C2121 la_oenb[99] vssa1 0.63fF
+C2122 la_data_out[99] vssa1 0.63fF
+C2123 la_data_in[99] vssa1 0.63fF
+C2124 la_oenb[98] vssa1 0.63fF
+C2125 la_data_out[98] vssa1 0.63fF
+C2126 la_data_in[98] vssa1 0.63fF
+C2127 la_oenb[97] vssa1 0.63fF
+C2128 la_data_out[97] vssa1 0.63fF
+C2129 la_data_in[97] vssa1 0.63fF
+C2130 la_oenb[96] vssa1 0.63fF
+C2131 la_data_out[96] vssa1 0.63fF
+C2132 la_data_in[96] vssa1 0.63fF
+C2133 la_oenb[95] vssa1 0.63fF
+C2134 la_data_out[95] vssa1 0.63fF
+C2135 la_data_in[95] vssa1 0.63fF
+C2136 la_oenb[94] vssa1 0.63fF
+C2137 la_data_out[94] vssa1 0.63fF
+C2138 la_data_in[94] vssa1 0.63fF
+C2139 la_oenb[93] vssa1 0.63fF
+C2140 la_data_out[93] vssa1 0.63fF
+C2141 la_data_in[93] vssa1 0.63fF
+C2142 la_oenb[92] vssa1 0.63fF
+C2143 la_data_out[92] vssa1 0.63fF
+C2144 la_data_in[92] vssa1 0.63fF
+C2145 la_oenb[91] vssa1 0.63fF
+C2146 la_data_out[91] vssa1 0.63fF
+C2147 la_data_in[91] vssa1 0.63fF
+C2148 la_oenb[90] vssa1 0.63fF
+C2149 la_data_out[90] vssa1 0.63fF
+C2150 la_data_in[90] vssa1 0.63fF
+C2151 la_oenb[89] vssa1 0.63fF
+C2152 la_data_out[89] vssa1 0.63fF
+C2153 la_data_in[89] vssa1 0.63fF
+C2154 la_oenb[88] vssa1 0.63fF
+C2155 la_data_out[88] vssa1 0.63fF
+C2156 la_data_in[88] vssa1 0.63fF
+C2157 la_oenb[87] vssa1 0.63fF
+C2158 la_data_out[87] vssa1 0.63fF
+C2159 la_data_in[87] vssa1 0.63fF
+C2160 la_oenb[86] vssa1 0.63fF
+C2161 la_data_out[86] vssa1 0.63fF
+C2162 la_data_in[86] vssa1 0.63fF
+C2163 la_oenb[85] vssa1 0.63fF
+C2164 la_data_out[85] vssa1 0.63fF
+C2165 la_data_in[85] vssa1 0.63fF
+C2166 la_oenb[84] vssa1 0.63fF
+C2167 la_data_out[84] vssa1 0.63fF
+C2168 la_data_in[84] vssa1 0.63fF
+C2169 la_oenb[83] vssa1 0.63fF
+C2170 la_data_out[83] vssa1 0.63fF
+C2171 la_data_in[83] vssa1 0.63fF
+C2172 la_oenb[82] vssa1 0.63fF
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+C2174 la_data_in[82] vssa1 0.63fF
+C2175 la_oenb[81] vssa1 0.63fF
+C2176 la_data_out[81] vssa1 0.63fF
+C2177 la_data_in[81] vssa1 0.63fF
+C2178 la_oenb[80] vssa1 0.63fF
+C2179 la_data_out[80] vssa1 0.63fF
+C2180 la_data_in[80] vssa1 0.63fF
+C2181 la_oenb[79] vssa1 0.63fF
+C2182 la_data_out[79] vssa1 0.63fF
+C2183 la_data_in[79] vssa1 0.63fF
+C2184 la_oenb[78] vssa1 0.63fF
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+C2186 la_data_in[78] vssa1 0.63fF
+C2187 la_oenb[77] vssa1 0.63fF
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+C2189 la_data_in[77] vssa1 0.63fF
+C2190 la_oenb[76] vssa1 0.63fF
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+C2192 la_data_in[76] vssa1 0.63fF
+C2193 la_oenb[75] vssa1 0.63fF
+C2194 la_data_out[75] vssa1 0.63fF
+C2195 la_data_in[75] vssa1 0.63fF
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+C2198 la_data_in[74] vssa1 0.63fF
+C2199 la_oenb[73] vssa1 0.63fF
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+C2201 la_data_in[73] vssa1 0.63fF
+C2202 la_oenb[72] vssa1 0.63fF
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+C2204 la_data_in[72] vssa1 0.63fF
+C2205 la_oenb[71] vssa1 0.63fF
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+C2208 la_oenb[70] vssa1 0.63fF
+C2209 la_data_out[70] vssa1 0.63fF
+C2210 la_data_in[70] vssa1 0.63fF
+C2211 la_oenb[69] vssa1 0.63fF
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+C2213 la_data_in[69] vssa1 0.63fF
+C2214 la_oenb[68] vssa1 0.63fF
+C2215 la_data_out[68] vssa1 0.63fF
+C2216 la_data_in[68] vssa1 0.63fF
+C2217 la_oenb[67] vssa1 0.63fF
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+C2219 la_data_in[67] vssa1 0.63fF
+C2220 la_oenb[66] vssa1 0.63fF
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+C2222 la_data_in[66] vssa1 0.63fF
+C2223 la_oenb[65] vssa1 0.63fF
+C2224 la_data_out[65] vssa1 0.63fF
+C2225 la_data_in[65] vssa1 0.63fF
+C2226 la_oenb[64] vssa1 0.63fF
+C2227 la_data_out[64] vssa1 0.63fF
+C2228 la_data_in[64] vssa1 0.63fF
+C2229 la_oenb[63] vssa1 0.63fF
+C2230 la_data_out[63] vssa1 0.63fF
+C2231 la_data_in[63] vssa1 0.63fF
+C2232 la_oenb[62] vssa1 0.63fF
+C2233 la_data_out[62] vssa1 0.63fF
+C2234 la_data_in[62] vssa1 0.63fF
+C2235 la_oenb[61] vssa1 0.63fF
+C2236 la_data_out[61] vssa1 0.63fF
+C2237 la_data_in[61] vssa1 0.63fF
+C2238 la_oenb[60] vssa1 0.63fF
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+C2240 la_data_in[60] vssa1 0.63fF
+C2241 la_oenb[59] vssa1 0.63fF
+C2242 la_data_out[59] vssa1 0.63fF
+C2243 la_data_in[59] vssa1 0.63fF
+C2244 la_oenb[58] vssa1 0.63fF
+C2245 la_data_out[58] vssa1 0.63fF
+C2246 la_data_in[58] vssa1 0.63fF
+C2247 la_oenb[57] vssa1 0.63fF
+C2248 la_data_out[57] vssa1 0.63fF
+C2249 la_data_in[57] vssa1 0.63fF
+C2250 la_oenb[56] vssa1 0.63fF
+C2251 la_data_out[56] vssa1 0.63fF
+C2252 la_data_in[56] vssa1 0.63fF
+C2253 la_oenb[55] vssa1 0.63fF
+C2254 la_data_out[55] vssa1 0.63fF
+C2255 la_data_in[55] vssa1 0.63fF
+C2256 la_oenb[54] vssa1 0.63fF
+C2257 la_data_out[54] vssa1 0.63fF
+C2258 la_data_in[54] vssa1 0.63fF
+C2259 la_oenb[53] vssa1 0.63fF
+C2260 la_data_out[53] vssa1 0.63fF
+C2261 la_data_in[53] vssa1 0.63fF
+C2262 la_oenb[52] vssa1 0.63fF
+C2263 la_data_out[52] vssa1 0.63fF
+C2264 la_data_in[52] vssa1 0.63fF
+C2265 la_oenb[51] vssa1 0.63fF
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+C2267 la_data_in[51] vssa1 0.63fF
+C2268 la_oenb[50] vssa1 0.63fF
+C2269 la_data_out[50] vssa1 0.63fF
+C2270 la_data_in[50] vssa1 0.63fF
+C2271 la_oenb[49] vssa1 0.63fF
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+C2273 la_data_in[49] vssa1 0.63fF
+C2274 la_oenb[48] vssa1 0.63fF
+C2275 la_data_out[48] vssa1 0.63fF
+C2276 la_data_in[48] vssa1 0.63fF
+C2277 la_oenb[47] vssa1 0.63fF
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+C2279 la_data_in[47] vssa1 0.63fF
+C2280 la_oenb[46] vssa1 0.63fF
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+C2282 la_data_in[46] vssa1 0.63fF
+C2283 la_oenb[45] vssa1 0.63fF
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+C2285 la_data_in[45] vssa1 0.63fF
+C2286 la_oenb[44] vssa1 0.63fF
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+C2288 la_data_in[44] vssa1 0.63fF
+C2289 la_oenb[43] vssa1 0.63fF
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+C2291 la_data_in[43] vssa1 0.63fF
+C2292 la_oenb[42] vssa1 0.63fF
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+C2294 la_data_in[42] vssa1 0.63fF
+C2295 la_oenb[41] vssa1 0.63fF
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+C2297 la_data_in[41] vssa1 0.63fF
+C2298 la_oenb[40] vssa1 0.63fF
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+C2300 la_data_in[40] vssa1 0.63fF
+C2301 la_oenb[39] vssa1 0.63fF
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+C2303 la_data_in[39] vssa1 0.63fF
+C2304 la_oenb[38] vssa1 0.63fF
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+C2306 la_data_in[38] vssa1 0.63fF
+C2307 la_oenb[37] vssa1 0.63fF
+C2308 la_data_out[37] vssa1 0.63fF
+C2309 la_data_in[37] vssa1 0.63fF
+C2310 la_oenb[36] vssa1 0.63fF
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+C2312 la_data_in[36] vssa1 0.63fF
+C2313 la_oenb[35] vssa1 0.63fF
+C2314 la_data_out[35] vssa1 0.63fF
+C2315 la_data_in[35] vssa1 0.63fF
+C2316 la_oenb[34] vssa1 0.63fF
+C2317 la_data_out[34] vssa1 0.63fF
+C2318 la_data_in[34] vssa1 0.63fF
+C2319 la_oenb[33] vssa1 0.63fF
+C2320 la_data_out[33] vssa1 0.63fF
+C2321 la_data_in[33] vssa1 0.63fF
+C2322 la_oenb[32] vssa1 0.63fF
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+C2324 la_data_in[32] vssa1 0.63fF
+C2325 la_oenb[31] vssa1 0.63fF
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+C2327 la_data_in[31] vssa1 0.63fF
+C2328 la_oenb[30] vssa1 0.63fF
+C2329 la_data_out[30] vssa1 0.63fF
+C2330 la_data_in[30] vssa1 0.63fF
+C2331 la_oenb[29] vssa1 0.63fF
+C2332 la_data_out[29] vssa1 0.63fF
+C2333 la_data_in[29] vssa1 0.63fF
+C2334 la_oenb[28] vssa1 0.63fF
+C2335 la_data_out[28] vssa1 0.63fF
+C2336 la_data_in[28] vssa1 0.63fF
+C2337 la_oenb[27] vssa1 0.63fF
+C2338 la_data_out[27] vssa1 0.63fF
+C2339 la_data_in[27] vssa1 0.63fF
+C2340 la_oenb[26] vssa1 0.63fF
+C2341 la_data_out[26] vssa1 0.63fF
+C2342 la_data_in[26] vssa1 0.63fF
+C2343 la_oenb[25] vssa1 0.63fF
+C2344 la_data_out[25] vssa1 0.63fF
+C2345 la_data_in[25] vssa1 0.63fF
+C2346 la_oenb[24] vssa1 0.63fF
+C2347 la_data_out[24] vssa1 0.63fF
+C2348 la_data_in[24] vssa1 0.63fF
+C2349 la_oenb[23] vssa1 0.63fF
+C2350 la_data_out[23] vssa1 0.63fF
+C2351 la_data_in[23] vssa1 0.63fF
+C2352 la_oenb[22] vssa1 0.63fF
+C2353 la_data_out[22] vssa1 0.63fF
+C2354 la_data_in[22] vssa1 0.63fF
+C2355 la_oenb[21] vssa1 0.63fF
+C2356 la_data_out[21] vssa1 0.63fF
+C2357 la_data_in[21] vssa1 0.63fF
+C2358 la_oenb[20] vssa1 0.63fF
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+C2360 la_data_in[20] vssa1 0.63fF
+C2361 la_oenb[19] vssa1 0.63fF
+C2362 la_data_out[19] vssa1 0.63fF
+C2363 la_data_in[19] vssa1 0.63fF
+C2364 la_oenb[18] vssa1 0.63fF
+C2365 la_data_out[18] vssa1 0.63fF
+C2366 la_data_in[18] vssa1 0.63fF
+C2367 la_oenb[17] vssa1 0.63fF
+C2368 la_data_out[17] vssa1 0.63fF
+C2369 la_data_in[17] vssa1 0.63fF
+C2370 la_oenb[16] vssa1 0.63fF
+C2371 la_data_out[16] vssa1 0.63fF
+C2372 la_data_in[16] vssa1 0.63fF
+C2373 la_oenb[15] vssa1 0.63fF
+C2374 la_data_out[15] vssa1 0.63fF
+C2375 la_data_in[15] vssa1 0.63fF
+C2376 la_oenb[14] vssa1 0.63fF
+C2377 la_data_out[14] vssa1 0.63fF
+C2378 la_data_in[14] vssa1 0.63fF
+C2379 la_oenb[13] vssa1 0.63fF
+C2380 la_data_out[13] vssa1 0.63fF
+C2381 la_data_in[13] vssa1 0.63fF
+C2382 la_oenb[12] vssa1 0.63fF
+C2383 la_data_out[12] vssa1 0.63fF
+C2384 la_data_in[12] vssa1 0.63fF
+C2385 la_oenb[11] vssa1 0.63fF
+C2386 la_data_out[11] vssa1 0.63fF
+C2387 la_data_in[11] vssa1 0.63fF
+C2388 la_oenb[10] vssa1 0.63fF
+C2389 la_data_out[10] vssa1 0.63fF
+C2390 la_data_in[10] vssa1 0.63fF
+C2391 la_oenb[9] vssa1 0.63fF
+C2392 la_data_out[9] vssa1 0.63fF
+C2393 la_data_in[9] vssa1 0.63fF
+C2394 la_oenb[8] vssa1 0.63fF
+C2395 la_data_out[8] vssa1 0.63fF
+C2396 la_data_in[8] vssa1 0.63fF
+C2397 la_oenb[7] vssa1 0.63fF
+C2398 la_data_out[7] vssa1 0.63fF
+C2399 la_data_in[7] vssa1 0.63fF
+C2400 la_oenb[6] vssa1 0.63fF
+C2401 la_data_out[6] vssa1 0.63fF
+C2402 la_data_in[6] vssa1 0.63fF
+C2403 la_oenb[5] vssa1 0.63fF
+C2404 la_data_out[5] vssa1 0.63fF
+C2405 la_data_in[5] vssa1 0.63fF
+C2406 la_oenb[4] vssa1 0.63fF
+C2407 la_data_out[4] vssa1 0.63fF
+C2408 la_data_in[4] vssa1 0.63fF
+C2409 la_oenb[3] vssa1 0.63fF
+C2410 la_data_out[3] vssa1 0.63fF
+C2411 la_data_in[3] vssa1 0.63fF
+C2412 la_oenb[2] vssa1 0.63fF
+C2413 la_data_out[2] vssa1 0.63fF
+C2414 la_data_in[2] vssa1 0.63fF
+C2415 la_oenb[1] vssa1 0.63fF
+C2416 la_data_out[1] vssa1 0.63fF
+C2417 la_data_in[1] vssa1 0.63fF
+C2418 la_oenb[0] vssa1 0.63fF
+C2419 la_data_out[0] vssa1 0.63fF
+C2420 la_data_in[0] vssa1 0.63fF
+C2421 wbs_dat_o[31] vssa1 0.63fF
+C2422 wbs_dat_i[31] vssa1 0.63fF
+C2423 wbs_adr_i[31] vssa1 0.63fF
+C2424 wbs_dat_o[30] vssa1 0.63fF
+C2425 wbs_dat_i[30] vssa1 0.63fF
+C2426 wbs_adr_i[30] vssa1 0.63fF
+C2427 wbs_dat_o[29] vssa1 0.63fF
+C2428 wbs_dat_i[29] vssa1 0.63fF
+C2429 wbs_adr_i[29] vssa1 0.63fF
+C2430 wbs_dat_o[28] vssa1 0.63fF
+C2431 wbs_dat_i[28] vssa1 0.63fF
+C2432 wbs_adr_i[28] vssa1 0.63fF
+C2433 wbs_dat_o[27] vssa1 0.63fF
+C2434 wbs_dat_i[27] vssa1 0.63fF
+C2435 wbs_adr_i[27] vssa1 0.63fF
+C2436 wbs_dat_o[26] vssa1 0.63fF
+C2437 wbs_dat_i[26] vssa1 0.63fF
+C2438 wbs_adr_i[26] vssa1 0.63fF
+C2439 wbs_dat_o[25] vssa1 0.63fF
+C2440 wbs_dat_i[25] vssa1 0.63fF
+C2441 wbs_adr_i[25] vssa1 0.63fF
+C2442 wbs_dat_o[24] vssa1 0.63fF
+C2443 wbs_dat_i[24] vssa1 0.63fF
+C2444 wbs_adr_i[24] vssa1 0.63fF
+C2445 wbs_dat_o[23] vssa1 0.63fF
+C2446 wbs_dat_i[23] vssa1 0.63fF
+C2447 wbs_adr_i[23] vssa1 0.63fF
+C2448 wbs_dat_o[22] vssa1 0.63fF
+C2449 wbs_dat_i[22] vssa1 0.63fF
+C2450 wbs_adr_i[22] vssa1 0.63fF
+C2451 wbs_dat_o[21] vssa1 0.63fF
+C2452 wbs_dat_i[21] vssa1 0.63fF
+C2453 wbs_adr_i[21] vssa1 0.63fF
+C2454 wbs_dat_o[20] vssa1 0.63fF
+C2455 wbs_dat_i[20] vssa1 0.63fF
+C2456 wbs_adr_i[20] vssa1 0.63fF
+C2457 wbs_dat_o[19] vssa1 0.63fF
+C2458 wbs_dat_i[19] vssa1 0.63fF
+C2459 wbs_adr_i[19] vssa1 0.63fF
+C2460 wbs_dat_o[18] vssa1 0.63fF
+C2461 wbs_dat_i[18] vssa1 0.63fF
+C2462 wbs_adr_i[18] vssa1 0.63fF
+C2463 wbs_dat_o[17] vssa1 0.63fF
+C2464 wbs_dat_i[17] vssa1 0.63fF
+C2465 wbs_adr_i[17] vssa1 0.63fF
+C2466 wbs_dat_o[16] vssa1 0.63fF
+C2467 wbs_dat_i[16] vssa1 0.63fF
+C2468 wbs_adr_i[16] vssa1 0.63fF
+C2469 wbs_dat_o[15] vssa1 0.63fF
+C2470 wbs_dat_i[15] vssa1 0.63fF
+C2471 wbs_adr_i[15] vssa1 0.63fF
+C2472 wbs_dat_o[14] vssa1 0.63fF
+C2473 wbs_dat_i[14] vssa1 0.63fF
+C2474 wbs_adr_i[14] vssa1 0.63fF
+C2475 wbs_dat_o[13] vssa1 0.63fF
+C2476 wbs_dat_i[13] vssa1 0.63fF
+C2477 wbs_adr_i[13] vssa1 0.63fF
+C2478 wbs_dat_o[12] vssa1 0.63fF
+C2479 wbs_dat_i[12] vssa1 0.63fF
+C2480 wbs_adr_i[12] vssa1 0.63fF
+C2481 wbs_dat_o[11] vssa1 0.63fF
+C2482 wbs_dat_i[11] vssa1 0.63fF
+C2483 wbs_adr_i[11] vssa1 0.63fF
+C2484 wbs_dat_o[10] vssa1 0.63fF
+C2485 wbs_dat_i[10] vssa1 0.63fF
+C2486 wbs_adr_i[10] vssa1 0.63fF
+C2487 wbs_dat_o[9] vssa1 0.63fF
+C2488 wbs_dat_i[9] vssa1 0.63fF
+C2489 wbs_adr_i[9] vssa1 0.63fF
+C2490 wbs_dat_o[8] vssa1 0.63fF
+C2491 wbs_dat_i[8] vssa1 0.63fF
+C2492 wbs_adr_i[8] vssa1 0.63fF
+C2493 wbs_dat_o[7] vssa1 0.63fF
+C2494 wbs_dat_i[7] vssa1 0.63fF
+C2495 wbs_adr_i[7] vssa1 0.63fF
+C2496 wbs_dat_o[6] vssa1 0.63fF
+C2497 wbs_dat_i[6] vssa1 0.63fF
+C2498 wbs_adr_i[6] vssa1 0.63fF
+C2499 wbs_dat_o[5] vssa1 0.63fF
+C2500 wbs_dat_i[5] vssa1 0.63fF
+C2501 wbs_adr_i[5] vssa1 0.63fF
+C2502 wbs_dat_o[4] vssa1 0.63fF
+C2503 wbs_dat_i[4] vssa1 0.63fF
+C2504 wbs_adr_i[4] vssa1 0.63fF
+C2505 wbs_sel_i[3] vssa1 0.63fF
+C2506 wbs_dat_o[3] vssa1 0.63fF
+C2507 wbs_dat_i[3] vssa1 0.63fF
+C2508 wbs_adr_i[3] vssa1 0.63fF
+C2509 wbs_sel_i[2] vssa1 0.63fF
+C2510 wbs_dat_o[2] vssa1 0.63fF
+C2511 wbs_dat_i[2] vssa1 0.63fF
+C2512 wbs_adr_i[2] vssa1 0.63fF
+C2513 wbs_sel_i[1] vssa1 0.63fF
+C2514 wbs_dat_o[1] vssa1 0.63fF
+C2515 wbs_dat_i[1] vssa1 0.63fF
+C2516 wbs_adr_i[1] vssa1 0.63fF
+C2517 wbs_sel_i[0] vssa1 0.63fF
+C2518 wbs_dat_o[0] vssa1 0.63fF
+C2519 wbs_dat_i[0] vssa1 0.63fF
+C2520 wbs_adr_i[0] vssa1 0.63fF
+C2521 wbs_we_i vssa1 0.63fF
+C2522 wbs_stb_i vssa1 0.63fF
+C2523 wbs_cyc_i vssa1 0.63fF
+C2524 wbs_ack_o vssa1 0.63fF
+C2525 wb_rst_i vssa1 0.63fF
+C2526 wb_clk_i vssa1 0.63fF
+C2527 pll_full_1/divider_0/and_0/Z1 vssa1 0.65fF
+C2528 pll_full_1/divider_0/and_0/B vssa1 2.45fF
+C2529 pll_full_1/divider_0/and_0/A vssa1 2.35fF
+C2530 pll_full_1/divider_0/and_0/out1 vssa1 2.99fF
+C2531 pll_full_1/divider_0/tspc_2/Z4 vssa1 0.86fF
+C2532 pll_full_1/div vssa1 14.90fF
+C2533 pll_full_1/divider_0/tspc_2/Z3 vssa1 2.26fF
+C2534 pll_full_1/divider_0/tspc_2/Z2 vssa1 1.46fF
+C2535 pll_full_1/divider_0/tspc_2/Z1 vssa1 0.99fF
+C2536 pll_full_1/divider_0/nor_0/B vssa1 6.48fF
+C2537 pll_full_1/divider_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2538 pll_full_1/divider_0/tspc_1/Z4 vssa1 0.86fF
+C2539 pll_full_1/divider_0/tspc_1/Q vssa1 3.12fF
+C2540 pll_full_1/divider_0/tspc_1/Z3 vssa1 2.26fF
+C2541 pll_full_1/divider_0/tspc_1/Z2 vssa1 1.46fF
+C2542 pll_full_1/divider_0/tspc_1/Z1 vssa1 0.99fF
+C2543 pll_full_1/divider_0/nor_1/B vssa1 7.12fF
+C2544 pll_full_1/divider_0/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
+C2545 pll_full_1/divider_0/tspc_0/Z4 vssa1 0.86fF
+C2546 pll_full_1/divider_0/tspc_0/Q vssa1 3.14fF
+C2547 pll_full_1/divider_0/tspc_0/Z3 vssa1 2.26fF
+C2548 pll_full_1/divider_0/tspc_0/Z2 vssa1 1.46fF
+C2549 pll_full_1/divider_0/tspc_0/Z1 vssa1 0.99fF
+C2550 pll_full_1/divider_0/nor_1/A vssa1 7.08fF
+C2551 pll_full_1/divider_0/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
+C2552 pll_full_1/vco vssa1 35.22fF
+C2553 pll_full_1/divider_0/prescaler_0/nand_1/z1 vssa1 0.36fF
+C2554 pll_full_1/divider_0/prescaler_0/tspc_0/D vssa1 2.64fF
+C2555 pll_full_1/divider_0/prescaler_0/tspc_2/Q vssa1 3.72fF
+C2556 pll_full_1/divider_0/prescaler_0/tspc_1/Q vssa1 3.61fF
+C2557 pll_full_1/divider_0/prescaler_0/nand_0/z1 vssa1 0.36fF
+C2558 pll_full_1/divider_0/prescaler_0/tspc_2/D vssa1 3.12fF
+C2559 pll_full_1/divider_0/and_0/OUT vssa1 5.67fF
+C2560 pll_full_1/divider_0/prescaler_0/tspc_2/Z4 vssa1 0.86fF
+C2561 pll_full_1/divider_0/prescaler_0/tspc_2/Z3 vssa1 2.26fF
+C2562 pll_full_1/divider_0/prescaler_0/tspc_2/Z2 vssa1 1.19fF
+C2563 pll_full_1/divider_0/prescaler_0/tspc_2/Z1 vssa1 0.99fF
+C2564 pll_full_1/divider_0/prescaler_0/tspc_2/a_630_n680# vssa1 1.47fF **FLOATING
+C2565 pll_full_1/divider_0/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
+C2566 pll_full_1/divider_0/prescaler_0/tspc_1/Z4 vssa1 0.86fF
+C2567 pll_full_1/divider_0/prescaler_0/tspc_1/Z3 vssa1 2.26fF
+C2568 pll_full_1/divider_0/prescaler_0/tspc_1/Z2 vssa1 1.48fF
+C2569 pll_full_1/divider_0/prescaler_0/tspc_1/Z1 vssa1 0.99fF
+C2570 pll_full_1/divider_0/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
+C2571 pll_full_1/divider_0/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
+C2572 pll_full_1/divider_0/prescaler_0/tspc_0/Z4 vssa1 0.86fF
+C2573 pll_full_1/divider_0/prescaler_0/Out vssa1 4.59fF
+C2574 pll_full_1/divider_0/prescaler_0/tspc_0/Z3 vssa1 2.26fF
+C2575 pll_full_1/divider_0/prescaler_0/tspc_0/Z2 vssa1 1.46fF
+C2576 pll_full_1/divider_0/prescaler_0/tspc_0/Z1 vssa1 0.99fF
+C2577 pll_full_1/divider_0/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
+C2578 pll_full_1/divider_0/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
+C2579 pll_full_1/divider_0/nor_1/Z1 vssa1 1.34fF
+C2580 pll_full_1/divider_0/nor_0/Z1 vssa1 1.34fF
+C2581 pll_full_1/ro_complete_0/cbank_2/v vssa1 16.43fF
+C2582 pll_full_1/ro_complete_0/cbank_2/switch_5/vin vssa1 0.78fF
+C2583 pll_full_1/ro_complete_0/cbank_2/switch_4/vin vssa1 1.50fF
+C2584 pll_full_1/ro_complete_0/cbank_2/switch_2/vin vssa1 1.30fF
+C2585 pll_full_1/ro_complete_0/cbank_2/switch_3/vin vssa1 0.56fF
+C2586 pll_full_1/ro_complete_0/cbank_2/switch_1/vin vssa1 1.14fF
+C2587 pll_full_1/ro_complete_0/cbank_2/switch_0/vin vssa1 1.02fF
+C2588 pll_full_1/ro_complete_0/cbank_1/switch_5/vin vssa1 0.78fF
+C2589 pll_full_1/ro_complete_0/a0 vssa1 5.35fF
+C2590 pll_full_1/ro_complete_0/cbank_1/switch_4/vin vssa1 1.50fF
+C2591 pll_full_1/ro_complete_0/a1 vssa1 6.54fF
+C2592 pll_full_1/ro_complete_0/cbank_1/switch_2/vin vssa1 1.30fF
+C2593 pll_full_1/ro_complete_0/a3 vssa1 5.96fF
+C2594 pll_full_1/ro_complete_0/cbank_1/switch_3/vin vssa1 0.56fF
+C2595 pll_full_1/ro_complete_0/a2 vssa1 5.21fF
+C2596 pll_full_1/ro_complete_0/cbank_1/switch_1/vin vssa1 1.14fF
+C2597 pll_full_1/ro_complete_0/a4 vssa1 5.81fF
+C2598 pll_full_1/ro_complete_0/cbank_1/switch_0/vin vssa1 1.02fF
+C2599 pll_full_1/ro_complete_0/a5 vssa1 6.74fF
+C2600 pll_full_1/ro_complete_0/cbank_0/v vssa1 15.12fF
+C2601 pll_full_1/ro_complete_0/cbank_0/switch_5/vin vssa1 0.78fF
+C2602 pll_full_1/ro_complete_0/cbank_0/switch_4/vin vssa1 1.50fF
+C2603 pll_full_1/ro_complete_0/cbank_0/switch_2/vin vssa1 1.30fF
+C2604 pll_full_1/ro_complete_0/cbank_0/switch_3/vin vssa1 0.56fF
+C2605 pll_full_1/ro_complete_0/cbank_0/switch_1/vin vssa1 1.14fF
+C2606 pll_full_1/ro_complete_0/cbank_0/switch_0/vin vssa1 1.02fF
+C2607 pll_full_1/filter_0/a_4216_n5230# vssa1 418.90fF **FLOATING
+C2608 pll_full_1/filter_0/a_4216_n2998# vssa1 1.39fF **FLOATING
+C2609 pll_full_1/cp_0/down vssa1 1.54fF
+C2610 pll_full_1/cp_0/upbar vssa1 1.79fF
+C2611 pll_full_1/cp_0/a_7110_n2840# vssa1 0.17fF **FLOATING
+C2612 pll_full_1/cp_0/a_3060_n2840# vssa1 1.71fF **FLOATING
+C2613 pll_full_1/cp_0/a_7110_0# vssa1 0.17fF **FLOATING
+C2614 pll_full_1/cp_0/a_6370_0# vssa1 0.40fF **FLOATING
+C2615 pll_full_1/cp_0/a_3060_0# vssa1 2.50fF **FLOATING
+C2616 pll_full_1/cp_0/a_1710_0# vssa1 7.47fF **FLOATING
+C2617 pll_full_1/pd_0/UP vssa1 5.89fF
+C2618 pll_full_1/pd_0/and_pd_0/Z1 vssa1 0.39fF
+C2619 pll_full_1/pd_0/and_pd_0/Out1 vssa1 2.22fF
+C2620 pll_full_1/pd_0/tspc_r_1/z5 vssa1 1.10fF
+C2621 pll_full_1/pd_0/tspc_r_1/Z4 vssa1 1.07fF
+C2622 pll_full_1/pd_0/R vssa1 3.05fF
+C2623 pll_full_1/pd_0/tspc_r_1/Qbar vssa1 0.79fF
+C2624 pll_full_1/pd_0/tspc_r_1/Z2 vssa1 1.22fF
+C2625 pll_full_1/pd_0/tspc_r_1/Z1 vssa1 0.67fF
+C2626 pll_full_1/pd_0/DOWN vssa1 7.38fF
+C2627 pll_full_1/pd_0/tspc_r_1/Qbar1 vssa1 1.34fF
+C2628 pll_full_1/pd_0/tspc_r_1/Z3 vssa1 2.12fF
+C2629 pll_full_1/pd_0/tspc_r_0/z5 vssa1 1.10fF
+C2630 pll_full_1/pd_0/tspc_r_0/Z4 vssa1 1.07fF
+C2631 pll_full_1/pd_0/tspc_r_0/Qbar vssa1 0.88fF
+C2632 pll_full_1/pd_0/tspc_r_0/Z2 vssa1 1.22fF
+C2633 pll_full_1/pd_0/tspc_r_0/Z1 vssa1 0.67fF
+C2634 pll_full_1/pd_0/tspc_r_0/Qbar1 vssa1 1.34fF
+C2635 pll_full_1/pd_0/tspc_r_0/Z3 vssa1 2.12fF
+C2636 pll_full_1/ref vssa1 4.34fF
+C2637 pll_full_0/divider_0/and_0/Z1 vssa1 0.65fF
+C2638 pll_full_0/divider_0/and_0/B vssa1 2.45fF
+C2639 pll_full_0/divider_0/and_0/A vssa1 2.35fF
+C2640 pll_full_0/divider_0/and_0/out1 vssa1 2.99fF
+C2641 pll_full_0/divider_0/tspc_2/Z4 vssa1 0.86fF
+C2642 pll_full_0/div vssa1 14.90fF
+C2643 pll_full_0/divider_0/tspc_2/Z3 vssa1 2.26fF
+C2644 pll_full_0/divider_0/tspc_2/Z2 vssa1 1.46fF
+C2645 pll_full_0/divider_0/tspc_2/Z1 vssa1 0.99fF
+C2646 pll_full_0/divider_0/nor_0/B vssa1 6.48fF
+C2647 pll_full_0/divider_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2648 pll_full_0/divider_0/tspc_1/Z4 vssa1 0.86fF
+C2649 pll_full_0/divider_0/tspc_1/Q vssa1 3.12fF
+C2650 pll_full_0/divider_0/tspc_1/Z3 vssa1 2.26fF
+C2651 pll_full_0/divider_0/tspc_1/Z2 vssa1 1.46fF
+C2652 pll_full_0/divider_0/tspc_1/Z1 vssa1 0.99fF
+C2653 pll_full_0/divider_0/nor_1/B vssa1 7.12fF
+C2654 pll_full_0/divider_0/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
+C2655 pll_full_0/divider_0/tspc_0/Z4 vssa1 0.86fF
+C2656 pll_full_0/divider_0/tspc_0/Q vssa1 3.14fF
+C2657 pll_full_0/divider_0/tspc_0/Z3 vssa1 2.26fF
+C2658 pll_full_0/divider_0/tspc_0/Z2 vssa1 1.46fF
+C2659 pll_full_0/divider_0/tspc_0/Z1 vssa1 0.99fF
+C2660 pll_full_0/divider_0/nor_1/A vssa1 7.08fF
+C2661 pll_full_0/divider_0/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
+C2662 pll_full_0/vco vssa1 35.22fF
+C2663 pll_full_0/divider_0/prescaler_0/nand_1/z1 vssa1 0.36fF
+C2664 pll_full_0/divider_0/prescaler_0/tspc_0/D vssa1 2.64fF
+C2665 pll_full_0/divider_0/prescaler_0/tspc_2/Q vssa1 3.72fF
+C2666 pll_full_0/divider_0/prescaler_0/tspc_1/Q vssa1 3.61fF
+C2667 pll_full_0/divider_0/prescaler_0/nand_0/z1 vssa1 0.36fF
+C2668 pll_full_0/divider_0/prescaler_0/tspc_2/D vssa1 3.12fF
+C2669 pll_full_0/divider_0/and_0/OUT vssa1 5.67fF
+C2670 pll_full_0/divider_0/prescaler_0/tspc_2/Z4 vssa1 0.86fF
+C2671 pll_full_0/divider_0/prescaler_0/tspc_2/Z3 vssa1 2.26fF
+C2672 pll_full_0/divider_0/prescaler_0/tspc_2/Z2 vssa1 1.19fF
+C2673 pll_full_0/divider_0/prescaler_0/tspc_2/Z1 vssa1 0.99fF
+C2674 pll_full_0/divider_0/prescaler_0/tspc_2/a_630_n680# vssa1 1.47fF **FLOATING
+C2675 pll_full_0/divider_0/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
+C2676 pll_full_0/divider_0/prescaler_0/tspc_1/Z4 vssa1 0.86fF
+C2677 pll_full_0/divider_0/prescaler_0/tspc_1/Z3 vssa1 2.26fF
+C2678 pll_full_0/divider_0/prescaler_0/tspc_1/Z2 vssa1 1.48fF
+C2679 pll_full_0/divider_0/prescaler_0/tspc_1/Z1 vssa1 0.99fF
+C2680 pll_full_0/divider_0/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
+C2681 pll_full_0/divider_0/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
+C2682 pll_full_0/divider_0/prescaler_0/tspc_0/Z4 vssa1 0.86fF
+C2683 pll_full_0/divider_0/prescaler_0/Out vssa1 4.59fF
+C2684 pll_full_0/divider_0/prescaler_0/tspc_0/Z3 vssa1 2.26fF
+C2685 pll_full_0/divider_0/prescaler_0/tspc_0/Z2 vssa1 1.46fF
+C2686 pll_full_0/divider_0/prescaler_0/tspc_0/Z1 vssa1 0.99fF
+C2687 pll_full_0/divider_0/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
+C2688 pll_full_0/divider_0/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
+C2689 pll_full_0/divider_0/nor_1/Z1 vssa1 1.34fF
+C2690 pll_full_0/divider_0/nor_0/Z1 vssa1 1.34fF
+C2691 pll_full_0/ro_complete_0/cbank_2/v vssa1 16.43fF
+C2692 pll_full_0/ro_complete_0/cbank_2/switch_5/vin vssa1 0.78fF
+C2693 pll_full_0/ro_complete_0/cbank_2/switch_4/vin vssa1 1.50fF
+C2694 pll_full_0/ro_complete_0/cbank_2/switch_2/vin vssa1 1.30fF
+C2695 pll_full_0/ro_complete_0/cbank_2/switch_3/vin vssa1 0.56fF
+C2696 pll_full_0/ro_complete_0/cbank_2/switch_1/vin vssa1 1.14fF
+C2697 pll_full_0/ro_complete_0/cbank_2/switch_0/vin vssa1 1.02fF
+C2698 pll_full_0/ro_complete_0/cbank_1/switch_5/vin vssa1 0.78fF
+C2699 pll_full_0/ro_complete_0/a0 vssa1 5.35fF
+C2700 pll_full_0/ro_complete_0/cbank_1/switch_4/vin vssa1 1.50fF
+C2701 pll_full_0/ro_complete_0/a1 vssa1 6.54fF
+C2702 pll_full_0/ro_complete_0/cbank_1/switch_2/vin vssa1 1.30fF
+C2703 pll_full_0/ro_complete_0/a3 vssa1 5.96fF
+C2704 pll_full_0/ro_complete_0/cbank_1/switch_3/vin vssa1 0.56fF
+C2705 pll_full_0/ro_complete_0/a2 vssa1 5.21fF
+C2706 pll_full_0/ro_complete_0/cbank_1/switch_1/vin vssa1 1.14fF
+C2707 pll_full_0/ro_complete_0/a4 vssa1 5.81fF
+C2708 pll_full_0/ro_complete_0/cbank_1/switch_0/vin vssa1 1.02fF
+C2709 pll_full_0/ro_complete_0/a5 vssa1 6.74fF
+C2710 pll_full_0/ro_complete_0/cbank_0/v vssa1 15.12fF
+C2711 pll_full_0/ro_complete_0/cbank_0/switch_5/vin vssa1 0.78fF
+C2712 pll_full_0/ro_complete_0/cbank_0/switch_4/vin vssa1 1.50fF
+C2713 pll_full_0/ro_complete_0/cbank_0/switch_2/vin vssa1 1.30fF
+C2714 pll_full_0/ro_complete_0/cbank_0/switch_3/vin vssa1 0.56fF
+C2715 pll_full_0/ro_complete_0/cbank_0/switch_1/vin vssa1 1.14fF
+C2716 pll_full_0/ro_complete_0/cbank_0/switch_0/vin vssa1 1.02fF
+C2717 pll_full_0/filter_0/a_4216_n5230# vssa1 418.90fF **FLOATING
+C2718 pll_full_0/filter_0/a_4216_n2998# vssa1 1.39fF **FLOATING
+C2719 pll_full_0/cp_0/down vssa1 1.54fF
+C2720 pll_full_0/cp_0/upbar vssa1 1.79fF
+C2721 pll_full_0/cp_0/a_7110_n2840# vssa1 0.17fF **FLOATING
+C2722 pll_full_0/cp_0/a_3060_n2840# vssa1 1.71fF **FLOATING
+C2723 pll_full_0/cp_0/a_7110_0# vssa1 0.17fF **FLOATING
+C2724 pll_full_0/cp_0/a_6370_0# vssa1 0.40fF **FLOATING
+C2725 pll_full_0/cp_0/a_3060_0# vssa1 2.50fF **FLOATING
+C2726 pll_full_0/cp_0/a_1710_0# vssa1 7.47fF **FLOATING
+C2727 pll_full_0/pd_0/UP vssa1 5.89fF
+C2728 pll_full_0/pd_0/and_pd_0/Z1 vssa1 0.39fF
+C2729 pll_full_0/pd_0/and_pd_0/Out1 vssa1 2.22fF
+C2730 pll_full_0/pd_0/tspc_r_1/z5 vssa1 1.10fF
+C2731 pll_full_0/pd_0/tspc_r_1/Z4 vssa1 1.07fF
+C2732 pll_full_0/pd_0/R vssa1 3.05fF
+C2733 pll_full_0/pd_0/tspc_r_1/Qbar vssa1 0.79fF
+C2734 pll_full_0/pd_0/tspc_r_1/Z2 vssa1 1.22fF
+C2735 pll_full_0/pd_0/tspc_r_1/Z1 vssa1 0.67fF
+C2736 pll_full_0/pd_0/DOWN vssa1 7.38fF
+C2737 pll_full_0/pd_0/tspc_r_1/Qbar1 vssa1 1.34fF
+C2738 pll_full_0/pd_0/tspc_r_1/Z3 vssa1 2.12fF
+C2739 pll_full_0/pd_0/tspc_r_0/z5 vssa1 1.10fF
+C2740 pll_full_0/pd_0/tspc_r_0/Z4 vssa1 1.07fF
+C2741 pll_full_0/pd_0/tspc_r_0/Qbar vssa1 0.88fF
+C2742 pll_full_0/pd_0/tspc_r_0/Z2 vssa1 1.22fF
+C2743 pll_full_0/pd_0/tspc_r_0/Z1 vssa1 0.67fF
+C2744 pll_full_0/pd_0/tspc_r_0/Qbar1 vssa1 1.34fF
+C2745 pll_full_0/pd_0/tspc_r_0/Z3 vssa1 2.12fF
+C2746 pll_full_0/ref vssa1 4.34fF
+C2747 divider_2/and_0/Z1 vssa1 0.74fF
+C2748 divider_2/and_0/B vssa1 2.25fF
+C2749 divider_2/and_0/A vssa1 2.19fF
+C2750 divider_2/and_0/out1 vssa1 2.93fF
+C2751 divider_2/tspc_2/Z4 vssa1 0.86fF
+C2752 divider_2/Out vssa1 1.60fF
+C2753 divider_2/tspc_2/Z3 vssa1 2.26fF
+C2754 divider_2/tspc_2/Z2 vssa1 1.46fF
+C2755 divider_2/tspc_2/Z1 vssa1 0.99fF
+C2756 divider_2/nor_0/B vssa1 6.44fF
+C2757 divider_2/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2758 divider_2/tspc_1/Z4 vssa1 0.86fF
+C2759 divider_2/tspc_1/Q vssa1 3.12fF
+C2760 divider_2/tspc_1/Z3 vssa1 2.26fF
+C2761 divider_2/tspc_1/Z2 vssa1 1.46fF
+C2762 divider_2/tspc_1/Z1 vssa1 0.99fF
+C2763 divider_2/nor_1/B vssa1 7.05fF
+C2764 divider_2/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
+C2765 divider_2/tspc_0/Z4 vssa1 0.86fF
+C2766 divider_2/tspc_0/Q vssa1 3.14fF
+C2767 divider_2/tspc_0/Z3 vssa1 2.26fF
+C2768 divider_2/tspc_0/Z2 vssa1 1.46fF
+C2769 divider_2/tspc_0/Z1 vssa1 0.99fF
+C2770 divider_2/nor_1/A vssa1 7.04fF
+C2771 divider_2/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
+C2772 divider_2/clk vssa1 5.63fF
+C2773 divider_2/prescaler_0/nand_1/z1 vssa1 0.36fF
+C2774 divider_2/prescaler_0/tspc_0/D vssa1 2.64fF
+C2775 divider_2/prescaler_0/tspc_2/Q vssa1 3.74fF
+C2776 divider_2/prescaler_0/tspc_1/Q vssa1 3.61fF
+C2777 divider_2/prescaler_0/nand_0/z1 vssa1 0.36fF
+C2778 divider_2/prescaler_0/tspc_2/D vssa1 3.12fF
+C2779 divider_2/and_0/OUT vssa1 5.62fF
+C2780 divider_2/prescaler_0/tspc_2/Z4 vssa1 0.86fF
+C2781 divider_2/prescaler_0/tspc_2/Z3 vssa1 2.26fF
+C2782 divider_2/prescaler_0/tspc_2/Z2 vssa1 1.46fF
+C2783 divider_2/prescaler_0/tspc_2/Z1 vssa1 0.99fF
+C2784 divider_2/prescaler_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2785 divider_2/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
+C2786 divider_2/prescaler_0/tspc_1/Z4 vssa1 0.86fF
+C2787 divider_2/prescaler_0/tspc_1/Z3 vssa1 2.26fF
+C2788 divider_2/prescaler_0/tspc_1/Z2 vssa1 1.48fF
+C2789 divider_2/prescaler_0/tspc_1/Z1 vssa1 0.99fF
+C2790 divider_2/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
+C2791 divider_2/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
+C2792 divider_2/prescaler_0/tspc_0/Z4 vssa1 0.86fF
+C2793 divider_2/prescaler_0/Out vssa1 4.59fF
+C2794 divider_2/prescaler_0/tspc_0/Z3 vssa1 2.26fF
+C2795 divider_2/prescaler_0/tspc_0/Z2 vssa1 1.46fF
+C2796 divider_2/prescaler_0/tspc_0/Z1 vssa1 0.99fF
+C2797 divider_2/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
+C2798 divider_2/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
+C2799 divider_2/nor_1/Z1 vssa1 1.34fF
+C2800 divider_2/nor_0/Z1 vssa1 1.34fF
+C2801 divider_2/mc2 vssa1 5.29fF
+C2802 divider_1/and_0/Z1 vssa1 0.74fF
+C2803 divider_1/and_0/B vssa1 2.25fF
+C2804 divider_1/and_0/A vssa1 2.19fF
+C2805 divider_1/and_0/out1 vssa1 2.93fF
+C2806 divider_1/tspc_2/Z4 vssa1 0.86fF
+C2807 divider_1/Out vssa1 1.60fF
+C2808 divider_1/tspc_2/Z3 vssa1 2.26fF
+C2809 divider_1/tspc_2/Z2 vssa1 1.46fF
+C2810 divider_1/tspc_2/Z1 vssa1 0.99fF
+C2811 divider_1/nor_0/B vssa1 6.33fF
+C2812 divider_1/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2813 divider_1/tspc_1/Z4 vssa1 0.86fF
+C2814 divider_1/tspc_1/Q vssa1 3.12fF
+C2815 divider_1/tspc_1/Z3 vssa1 2.26fF
+C2816 divider_1/tspc_1/Z2 vssa1 1.46fF
+C2817 divider_1/tspc_1/Z1 vssa1 0.99fF
+C2818 divider_1/nor_1/B vssa1 7.05fF
+C2819 divider_1/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
+C2820 divider_1/tspc_0/Z4 vssa1 0.86fF
+C2821 divider_1/tspc_0/Q vssa1 3.14fF
+C2822 divider_1/tspc_0/Z3 vssa1 2.26fF
+C2823 divider_1/tspc_0/Z2 vssa1 1.46fF
+C2824 divider_1/tspc_0/Z1 vssa1 0.99fF
+C2825 divider_1/nor_1/A vssa1 7.04fF
+C2826 divider_1/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
+C2827 divider_1/clk vssa1 5.63fF
+C2828 divider_1/prescaler_0/nand_1/z1 vssa1 0.36fF
+C2829 divider_1/prescaler_0/tspc_0/D vssa1 2.64fF
+C2830 divider_1/prescaler_0/tspc_2/Q vssa1 3.74fF
+C2831 divider_1/prescaler_0/tspc_1/Q vssa1 3.61fF
+C2832 divider_1/prescaler_0/nand_0/z1 vssa1 0.36fF
+C2833 divider_1/prescaler_0/tspc_2/D vssa1 3.12fF
+C2834 divider_1/and_0/OUT vssa1 5.62fF
+C2835 divider_1/prescaler_0/tspc_2/Z4 vssa1 0.86fF
+C2836 divider_1/prescaler_0/tspc_2/Z3 vssa1 2.26fF
+C2837 divider_1/prescaler_0/tspc_2/Z2 vssa1 1.46fF
+C2838 divider_1/prescaler_0/tspc_2/Z1 vssa1 0.99fF
+C2839 divider_1/prescaler_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2840 divider_1/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
+C2841 divider_1/prescaler_0/tspc_1/Z4 vssa1 0.86fF
+C2842 divider_1/prescaler_0/tspc_1/Z3 vssa1 2.26fF
+C2843 divider_1/prescaler_0/tspc_1/Z2 vssa1 1.48fF
+C2844 divider_1/prescaler_0/tspc_1/Z1 vssa1 0.99fF
+C2845 divider_1/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
+C2846 divider_1/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
+C2847 divider_1/prescaler_0/tspc_0/Z4 vssa1 0.86fF
+C2848 divider_1/prescaler_0/Out vssa1 4.59fF
+C2849 divider_1/prescaler_0/tspc_0/Z3 vssa1 2.26fF
+C2850 divider_1/prescaler_0/tspc_0/Z2 vssa1 1.46fF
+C2851 divider_1/prescaler_0/tspc_0/Z1 vssa1 0.99fF
+C2852 divider_1/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
+C2853 divider_1/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
+C2854 divider_1/nor_1/Z1 vssa1 1.34fF
+C2855 divider_1/nor_0/Z1 vssa1 1.34fF
+C2856 divider_1/mc2 vssa1 5.29fF
+C2857 divider_0/and_0/Z1 vssa1 0.74fF
+C2858 divider_0/and_0/B vssa1 2.25fF
+C2859 divider_0/and_0/A vssa1 2.19fF
+C2860 divider_0/and_0/out1 vssa1 2.93fF
+C2861 divider_0/tspc_2/Z4 vssa1 0.86fF
+C2862 divider_0/Out vssa1 1.60fF
+C2863 divider_0/tspc_2/Z3 vssa1 2.26fF
+C2864 divider_0/tspc_2/Z2 vssa1 1.46fF
+C2865 divider_0/tspc_2/Z1 vssa1 0.99fF
+C2866 divider_0/nor_0/B vssa1 6.33fF
+C2867 divider_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2868 divider_0/tspc_1/Z4 vssa1 0.86fF
+C2869 divider_0/tspc_1/Q vssa1 3.12fF
+C2870 divider_0/tspc_1/Z3 vssa1 2.26fF
+C2871 divider_0/tspc_1/Z2 vssa1 1.46fF
+C2872 divider_0/tspc_1/Z1 vssa1 0.99fF
+C2873 divider_0/nor_1/B vssa1 7.05fF
+C2874 divider_0/tspc_1/a_630_n680# vssa1 1.15fF **FLOATING
+C2875 divider_0/tspc_0/Z4 vssa1 0.86fF
+C2876 divider_0/tspc_0/Q vssa1 3.14fF
+C2877 divider_0/tspc_0/Z3 vssa1 2.26fF
+C2878 divider_0/tspc_0/Z2 vssa1 1.46fF
+C2879 divider_0/tspc_0/Z1 vssa1 0.99fF
+C2880 divider_0/nor_1/A vssa1 7.04fF
+C2881 divider_0/tspc_0/a_630_n680# vssa1 1.15fF **FLOATING
+C2882 divider_0/clk vssa1 5.63fF
+C2883 divider_0/prescaler_0/nand_1/z1 vssa1 0.36fF
+C2884 divider_0/prescaler_0/tspc_0/D vssa1 2.64fF
+C2885 divider_0/prescaler_0/tspc_2/Q vssa1 3.64fF
+C2886 divider_0/prescaler_0/tspc_1/Q vssa1 3.61fF
+C2887 divider_0/prescaler_0/nand_0/z1 vssa1 0.36fF
+C2888 divider_0/prescaler_0/tspc_2/D vssa1 3.12fF
+C2889 divider_0/and_0/OUT vssa1 5.62fF
+C2890 divider_0/prescaler_0/tspc_2/Z4 vssa1 0.86fF
+C2891 divider_0/prescaler_0/tspc_2/Z3 vssa1 2.26fF
+C2892 divider_0/prescaler_0/tspc_2/Z2 vssa1 1.46fF
+C2893 divider_0/prescaler_0/tspc_2/Z1 vssa1 0.99fF
+C2894 divider_0/prescaler_0/tspc_2/a_630_n680# vssa1 1.14fF **FLOATING
+C2895 divider_0/prescaler_0/tspc_2/a_740_n680# vssa1 2.11fF **FLOATING
+C2896 divider_0/prescaler_0/tspc_1/Z4 vssa1 0.86fF
+C2897 divider_0/prescaler_0/tspc_1/Z3 vssa1 2.26fF
+C2898 divider_0/prescaler_0/tspc_1/Z2 vssa1 1.48fF
+C2899 divider_0/prescaler_0/tspc_1/Z1 vssa1 0.99fF
+C2900 divider_0/prescaler_0/tspc_1/a_630_n680# vssa1 1.14fF **FLOATING
+C2901 divider_0/prescaler_0/m1_2700_2190# vssa1 4.22fF **FLOATING
+C2902 divider_0/prescaler_0/tspc_0/Z4 vssa1 0.86fF
+C2903 divider_0/prescaler_0/Out vssa1 4.59fF
+C2904 divider_0/prescaler_0/tspc_0/Z3 vssa1 2.26fF
+C2905 divider_0/prescaler_0/tspc_0/Z2 vssa1 1.46fF
+C2906 divider_0/prescaler_0/tspc_0/Z1 vssa1 0.99fF
+C2907 divider_0/prescaler_0/tspc_0/a_630_n680# vssa1 1.16fF **FLOATING
+C2908 divider_0/prescaler_0/tspc_0/a_740_n680# vssa1 2.11fF **FLOATING
+C2909 divider_0/nor_1/Z1 vssa1 1.34fF
+C2910 divider_0/nor_0/Z1 vssa1 1.34fF
+C2911 divider_0/mc2 vssa1 5.29fF
+C2912 ro_complete_buffered_0/tapered_buf_0/in vssa1 1.13fF
+C2913 ro_complete_buffered_0/tapered_buf_0/a_n10_n140# vssa1 0.06fF **FLOATING
+C2914 ro_complete_buffered_0/tapered_buf_0/a_210_n610# vssa1 588.54fF **FLOATING
+C2915 ro_complete_buffered_0/tapered_buf_0/a_160_230# vssa1 0.15fF **FLOATING
+C2916 ro_complete_buffered_0/tapered_buf_0/a_n10_230# vssa1 0.13fF **FLOATING
+C2917 ro_complete_buffered_0/tapered_buf_0/a_4670_0# vssa1 250.63fF **FLOATING
+C2918 ro_complete_buffered_0/tapered_buf_0/a_1650_0# vssa1 63.04fF **FLOATING
+C2919 ro_complete_buffered_0/tapered_buf_0/a_580_0# vssa1 16.64fF **FLOATING
+C2920 ro_complete_buffered_0/tapered_buf_0/a_160_n140# vssa1 4.00fF **FLOATING
+C2921 gnd vssa1 96.41fF
+C2922 ro_complete_buffered_0/tapered_buf_1/in vssa1 1.09fF
+C2923 ro_complete_buffered_0/tapered_buf_1/a_n10_n140# vssa1 0.06fF **FLOATING
+C2924 ro_complete_buffered_0/tapered_buf_1/a_210_n610# vssa1 376.11fF **FLOATING
+C2925 ro_complete_buffered_0/tapered_buf_1/a_160_230# vssa1 0.15fF **FLOATING
+C2926 ro_complete_buffered_0/tapered_buf_1/a_n10_230# vssa1 0.13fF **FLOATING
+C2927 ro_complete_buffered_0/tapered_buf_1/a_4670_0# vssa1 168.15fF **FLOATING
+C2928 ro_complete_buffered_0/tapered_buf_1/a_1650_0# vssa1 42.34fF **FLOATING
+C2929 ro_complete_buffered_0/tapered_buf_1/a_580_0# vssa1 10.93fF **FLOATING
+C2930 ro_complete_buffered_0/tapered_buf_1/a_160_n140# vssa1 2.66fF **FLOATING
+C2931 ro_complete_buffered_0/ro_complete_0/cbank_2/v vssa1 16.53fF
+C2932 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_5/vin vssa1 0.78fF
+C2933 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_4/vin vssa1 1.50fF
+C2934 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_2/vin vssa1 1.30fF
+C2935 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_3/vin vssa1 0.56fF
+C2936 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_1/vin vssa1 1.14fF
+C2937 ro_complete_buffered_0/ro_complete_0/cbank_2/switch_0/vin vssa1 1.02fF
+C2938 ro_complete_buffered_0/tapered_buf_6/in vssa1 23.85fF
+C2939 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_5/vin vssa1 0.78fF
+C2940 ro_complete_buffered_0/ro_complete_0/a0 vssa1 415.68fF
+C2941 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_4/vin vssa1 1.50fF
+C2942 ro_complete_buffered_0/ro_complete_0/a1 vssa1 411.44fF
+C2943 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_2/vin vssa1 1.30fF
+C2944 ro_complete_buffered_0/ro_complete_0/a3 vssa1 403.90fF
+C2945 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_3/vin vssa1 0.56fF
+C2946 ro_complete_buffered_0/ro_complete_0/a2 vssa1 407.33fF
+C2947 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_1/vin vssa1 1.14fF
+C2948 ro_complete_buffered_0/ro_complete_0/a4 vssa1 313.18fF
+C2949 ro_complete_buffered_0/ro_complete_0/cbank_1/switch_0/vin vssa1 1.02fF
+C2950 ro_complete_buffered_0/ro_complete_0/a5 vssa1 400.20fF
+C2951 ro_complete_buffered_0/ro_complete_0/cbank_0/v vssa1 15.13fF
+C2952 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_5/vin vssa1 0.78fF
+C2953 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_4/vin vssa1 1.50fF
+C2954 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_2/vin vssa1 1.30fF
+C2955 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_3/vin vssa1 0.56fF
+C2956 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_1/vin vssa1 1.14fF
+C2957 ro_complete_buffered_0/ro_complete_0/cbank_0/switch_0/vin vssa1 1.02fF
+C2958 ro_complete_buffered_0/tapered_buf_7/in vssa1 1.13fF
+C2959 ro_complete_buffered_0/tapered_buf_7/a_n10_n140# vssa1 0.06fF **FLOATING
+C2960 ro_complete_buffered_0/tapered_buf_7/a_210_n610# vssa1 614.83fF **FLOATING
+C2961 ro_complete_buffered_0/tapered_buf_7/a_160_230# vssa1 0.15fF **FLOATING
+C2962 ro_complete_buffered_0/tapered_buf_7/a_n10_230# vssa1 0.13fF **FLOATING
+C2963 ro_complete_buffered_0/tapered_buf_7/a_4670_0# vssa1 250.63fF **FLOATING
+C2964 ro_complete_buffered_0/tapered_buf_7/a_1650_0# vssa1 63.04fF **FLOATING
+C2965 ro_complete_buffered_0/tapered_buf_7/a_580_0# vssa1 16.64fF **FLOATING
+C2966 ro_complete_buffered_0/tapered_buf_7/a_160_n140# vssa1 4.00fF **FLOATING
+C2967 ro_complete_buffered_0/tapered_buf_6/out vssa1 385.11fF
+C2968 ro_complete_buffered_0/tapered_buf_6/a_n10_n140# vssa1 0.06fF **FLOATING
+C2969 ro_complete_buffered_0/tapered_buf_6/a_210_n610# vssa1 588.54fF **FLOATING
+C2970 ro_complete_buffered_0/tapered_buf_6/a_160_230# vssa1 0.15fF **FLOATING
+C2971 ro_complete_buffered_0/tapered_buf_6/a_n10_230# vssa1 0.13fF **FLOATING
+C2972 ro_complete_buffered_0/tapered_buf_6/a_4670_0# vssa1 250.63fF **FLOATING
+C2973 ro_complete_buffered_0/tapered_buf_6/a_1650_0# vssa1 63.04fF **FLOATING
+C2974 ro_complete_buffered_0/tapered_buf_6/a_580_0# vssa1 16.64fF **FLOATING
+C2975 ro_complete_buffered_0/tapered_buf_6/a_160_n140# vssa1 4.00fF **FLOATING
+C2976 ro_complete_buffered_0/tapered_buf_5/in vssa1 1.13fF
+C2977 ro_complete_buffered_0/tapered_buf_5/a_n10_n140# vssa1 0.06fF **FLOATING
+C2978 ro_complete_buffered_0/tapered_buf_5/a_210_n610# vssa1 588.54fF **FLOATING
+C2979 ro_complete_buffered_0/tapered_buf_5/a_160_230# vssa1 0.15fF **FLOATING
+C2980 ro_complete_buffered_0/tapered_buf_5/a_n10_230# vssa1 0.13fF **FLOATING
+C2981 ro_complete_buffered_0/tapered_buf_5/a_4670_0# vssa1 250.63fF **FLOATING
+C2982 ro_complete_buffered_0/tapered_buf_5/a_1650_0# vssa1 63.04fF **FLOATING
+C2983 ro_complete_buffered_0/tapered_buf_5/a_580_0# vssa1 16.64fF **FLOATING
+C2984 ro_complete_buffered_0/tapered_buf_5/a_160_n140# vssa1 4.00fF **FLOATING
+C2985 ro_complete_buffered_0/tapered_buf_4/in vssa1 1.13fF
+C2986 ro_complete_buffered_0/tapered_buf_4/a_n10_n140# vssa1 0.06fF **FLOATING
+C2987 ro_complete_buffered_0/tapered_buf_4/a_210_n610# vssa1 588.54fF **FLOATING
+C2988 ro_complete_buffered_0/tapered_buf_4/a_160_230# vssa1 0.15fF **FLOATING
+C2989 ro_complete_buffered_0/tapered_buf_4/a_n10_230# vssa1 0.13fF **FLOATING
+C2990 ro_complete_buffered_0/tapered_buf_4/a_4670_0# vssa1 250.63fF **FLOATING
+C2991 ro_complete_buffered_0/tapered_buf_4/a_1650_0# vssa1 63.04fF **FLOATING
+C2992 ro_complete_buffered_0/tapered_buf_4/a_580_0# vssa1 16.64fF **FLOATING
+C2993 ro_complete_buffered_0/tapered_buf_4/a_160_n140# vssa1 4.00fF **FLOATING
+C2994 ro_complete_buffered_0/tapered_buf_3/in vssa1 1.13fF
+C2995 ro_complete_buffered_0/tapered_buf_3/a_n10_n140# vssa1 0.06fF **FLOATING
+C2996 ro_complete_buffered_0/tapered_buf_3/a_210_n610# vssa1 588.54fF **FLOATING
+C2997 ro_complete_buffered_0/tapered_buf_3/a_160_230# vssa1 0.15fF **FLOATING
+C2998 ro_complete_buffered_0/tapered_buf_3/a_n10_230# vssa1 0.13fF **FLOATING
+C2999 ro_complete_buffered_0/tapered_buf_3/a_4670_0# vssa1 250.63fF **FLOATING
+C3000 ro_complete_buffered_0/tapered_buf_3/a_1650_0# vssa1 63.04fF **FLOATING
+C3001 ro_complete_buffered_0/tapered_buf_3/a_580_0# vssa1 16.64fF **FLOATING
+C3002 ro_complete_buffered_0/tapered_buf_3/a_160_n140# vssa1 4.00fF **FLOATING
+C3003 ro_complete_buffered_0/tapered_buf_2/in vssa1 1.13fF
+C3004 ro_complete_buffered_0/tapered_buf_2/a_n10_n140# vssa1 0.06fF **FLOATING
+C3005 ro_complete_buffered_0/tapered_buf_2/a_210_n610# vssa1 588.54fF **FLOATING
+C3006 ro_complete_buffered_0/tapered_buf_2/a_160_230# vssa1 0.15fF **FLOATING
+C3007 ro_complete_buffered_0/tapered_buf_2/a_n10_230# vssa1 0.13fF **FLOATING
+C3008 ro_complete_buffered_0/tapered_buf_2/a_4670_0# vssa1 250.63fF **FLOATING
+C3009 ro_complete_buffered_0/tapered_buf_2/a_1650_0# vssa1 63.04fF **FLOATING
+C3010 ro_complete_buffered_0/tapered_buf_2/a_580_0# vssa1 16.64fF **FLOATING
+C3011 ro_complete_buffered_0/tapered_buf_2/a_160_n140# vssa1 4.00fF **FLOATING
+C3012 ro_complete_0/cbank_2/v vssa1 16.43fF
+C3013 ro_complete_0/cbank_2/switch_5/vin vssa1 0.78fF
+C3014 ro_complete_0/cbank_2/switch_4/vin vssa1 1.50fF
+C3015 ro_complete_0/cbank_2/switch_2/vin vssa1 1.30fF
+C3016 ro_complete_0/cbank_2/switch_3/vin vssa1 0.56fF
+C3017 ro_complete_0/cbank_2/switch_1/vin vssa1 1.14fF
+C3018 ro_complete_0/cbank_2/switch_0/vin vssa1 1.02fF
+C3019 ro_complete_0/cbank_1/v vssa1 16.43fF
+C3020 ro_complete_0/cbank_1/switch_5/vin vssa1 0.78fF
+C3021 ro_complete_0/a0 vssa1 5.35fF
+C3022 ro_complete_0/cbank_1/switch_4/vin vssa1 1.50fF
+C3023 ro_complete_0/a1 vssa1 6.54fF
+C3024 ro_complete_0/cbank_1/switch_2/vin vssa1 1.30fF
+C3025 ro_complete_0/a3 vssa1 5.96fF
+C3026 ro_complete_0/cbank_1/switch_3/vin vssa1 0.56fF
+C3027 ro_complete_0/a2 vssa1 5.21fF
+C3028 ro_complete_0/cbank_1/switch_1/vin vssa1 1.14fF
+C3029 ro_complete_0/a4 vssa1 5.81fF
+C3030 ro_complete_0/cbank_1/switch_0/vin vssa1 1.02fF
+C3031 ro_complete_0/a5 vssa1 6.74fF
+C3032 ro_complete_0/cbank_0/v vssa1 15.12fF
+C3033 ro_complete_0/cbank_0/switch_5/vin vssa1 0.78fF
+C3034 ro_complete_0/cbank_0/switch_4/vin vssa1 1.50fF
+C3035 ro_complete_0/cbank_0/switch_2/vin vssa1 1.30fF
+C3036 ro_complete_0/cbank_0/switch_3/vin vssa1 0.56fF
+C3037 ro_complete_0/cbank_0/switch_1/vin vssa1 1.14fF
+C3038 ro_complete_0/cbank_0/switch_0/vin vssa1 1.02fF
+C3039 filter_0/v vssa1 110.47fF
+C3040 filter_0/a_4216_n5230# vssa1 418.47fF **FLOATING
+C3041 filter_0/a_4216_n2998# vssa1 1.03fF **FLOATING
+C3042 pd_0/UP vssa1 2.21fF
+C3043 pd_0/and_pd_0/Z1 vssa1 0.39fF
+C3044 pd_0/and_pd_0/Out1 vssa1 2.22fF
+C3045 pd_0/tspc_r_1/z5 vssa1 1.10fF
+C3046 pd_0/tspc_r_1/Z4 vssa1 1.07fF
+C3047 pd_0/R vssa1 3.05fF
+C3048 pd_0/tspc_r_1/Qbar vssa1 0.79fF
+C3049 pd_0/tspc_r_1/Z2 vssa1 1.22fF
+C3050 pd_0/tspc_r_1/Z1 vssa1 0.67fF
+C3051 pd_0/DOWN vssa1 3.08fF
+C3052 pd_0/tspc_r_1/Qbar1 vssa1 1.34fF
+C3053 pd_0/tspc_r_1/Z3 vssa1 2.12fF
+C3054 pd_0/DIV vssa1 1.82fF
+C3055 pd_0/tspc_r_0/z5 vssa1 1.10fF
+C3056 pd_0/tspc_r_0/Z4 vssa1 1.07fF
+C3057 pd_0/tspc_r_0/Qbar vssa1 0.88fF
+C3058 pd_0/tspc_r_0/Z2 vssa1 1.22fF
+C3059 pd_0/tspc_r_0/Z1 vssa1 0.67fF
+C3060 pd_0/tspc_r_0/Qbar1 vssa1 1.34fF
+C3061 pd_0/tspc_r_0/Z3 vssa1 2.12fF
+C3062 pd_0/REF vssa1 1.80fF
+C3063 cp_buffered_0/tapered_buf_0/in vssa1 1.13fF
+C3064 cp_buffered_0/tapered_buf_0/a_n10_n140# vssa1 0.06fF **FLOATING
+C3065 cp_buffered_0/tapered_buf_0/a_210_n610# vssa1 588.54fF **FLOATING
+C3066 cp_buffered_0/tapered_buf_0/a_160_230# vssa1 0.15fF **FLOATING
+C3067 cp_buffered_0/tapered_buf_0/a_n10_230# vssa1 0.13fF **FLOATING
+C3068 cp_buffered_0/tapered_buf_0/a_4670_0# vssa1 250.63fF **FLOATING
+C3069 cp_buffered_0/tapered_buf_0/a_1650_0# vssa1 63.04fF **FLOATING
+C3070 cp_buffered_0/tapered_buf_0/a_580_0# vssa1 16.64fF **FLOATING
+C3071 cp_buffered_0/tapered_buf_0/a_160_n140# vssa1 4.00fF **FLOATING
+C3072 cp_buffered_0/cp_0/out vssa1 396.39fF
+C3073 cp_buffered_0/tapered_buf_1/in vssa1 1.13fF
+C3074 cp_buffered_0/tapered_buf_1/a_n10_n140# vssa1 0.06fF **FLOATING
+C3075 cp_buffered_0/tapered_buf_1/a_210_n610# vssa1 588.54fF **FLOATING
+C3076 cp_buffered_0/tapered_buf_1/a_160_230# vssa1 0.15fF **FLOATING
+C3077 cp_buffered_0/tapered_buf_1/a_n10_230# vssa1 0.13fF **FLOATING
+C3078 cp_buffered_0/tapered_buf_1/a_4670_0# vssa1 250.63fF **FLOATING
+C3079 cp_buffered_0/tapered_buf_1/a_1650_0# vssa1 63.04fF **FLOATING
+C3080 cp_buffered_0/tapered_buf_1/a_580_0# vssa1 16.64fF **FLOATING
+C3081 cp_buffered_0/tapered_buf_1/a_160_n140# vssa1 4.00fF **FLOATING
+C3082 cp_buffered_0/cp_0/upbar vssa1 392.61fF
+C3083 cp_buffered_0/cp_0/a_7110_n2840# vssa1 0.17fF **FLOATING
+C3084 cp_buffered_0/cp_0/a_3060_n2840# vssa1 1.71fF **FLOATING
+C3085 cp_buffered_0/cp_0/a_7110_0# vssa1 0.17fF **FLOATING
+C3086 cp_buffered_0/cp_0/a_6370_0# vssa1 0.40fF **FLOATING
+C3087 cp_buffered_0/cp_0/a_3060_0# vssa1 1.65fF **FLOATING
+C3088 cp_buffered_0/cp_0/a_1710_0# vssa1 5.76fF **FLOATING
+C3089 cp_buffered_0/cp_0/a_1710_n2840# vssa1 4.89fF **FLOATING
+C3090 cp_buffered_0/cp_0/a_10_n50# vssa1 3.19fF **FLOATING
+C3091 cp_buffered_0/cp_0/down vssa1 396.37fF
+C3092 cp_buffered_0/tapered_buf_2/in vssa1 1.13fF
+C3093 cp_buffered_0/tapered_buf_2/a_n10_n140# vssa1 0.06fF **FLOATING
+C3094 cp_buffered_0/tapered_buf_2/a_210_n610# vssa1 588.54fF **FLOATING
+C3095 cp_buffered_0/tapered_buf_2/a_160_230# vssa1 0.15fF **FLOATING
+C3096 cp_buffered_0/tapered_buf_2/a_n10_230# vssa1 0.13fF **FLOATING
+C3097 cp_buffered_0/tapered_buf_2/a_4670_0# vssa1 250.63fF **FLOATING
+C3098 cp_buffered_0/tapered_buf_2/a_1650_0# vssa1 63.04fF **FLOATING
+C3099 cp_buffered_0/tapered_buf_2/a_580_0# vssa1 16.64fF **FLOATING
+C3100 cp_buffered_0/tapered_buf_2/a_160_n140# vssa1 4.00fF **FLOATING
+C3101 pd_buffered_0/tapered_buf_0/out vssa1 385.14fF
+C3102 pd_buffered_0/tapered_buf_0/a_n10_n140# vssa1 0.06fF **FLOATING
+C3103 pd_buffered_0/tapered_buf_0/a_210_n610# vssa1 588.54fF **FLOATING
+C3104 pd_buffered_0/tapered_buf_0/a_160_230# vssa1 0.15fF **FLOATING
+C3105 pd_buffered_0/tapered_buf_0/a_n10_230# vssa1 0.13fF **FLOATING
+C3106 pd_buffered_0/tapered_buf_0/a_4670_0# vssa1 250.63fF **FLOATING
+C3107 pd_buffered_0/tapered_buf_0/a_1650_0# vssa1 63.04fF **FLOATING
+C3108 pd_buffered_0/tapered_buf_0/a_580_0# vssa1 16.64fF **FLOATING
+C3109 pd_buffered_0/tapered_buf_0/a_160_n140# vssa1 4.00fF **FLOATING
+C3110 pd_buffered_0/tapered_buf_1/out vssa1 385.17fF
+C3111 pd_buffered_0/tapered_buf_1/a_n10_n140# vssa1 0.06fF **FLOATING
+C3112 pd_buffered_0/tapered_buf_1/a_210_n610# vssa1 588.54fF **FLOATING
+C3113 pd_buffered_0/tapered_buf_1/a_160_230# vssa1 0.15fF **FLOATING
+C3114 pd_buffered_0/tapered_buf_1/a_n10_230# vssa1 0.13fF **FLOATING
+C3115 pd_buffered_0/tapered_buf_1/a_4670_0# vssa1 250.63fF **FLOATING
+C3116 pd_buffered_0/tapered_buf_1/a_1650_0# vssa1 63.04fF **FLOATING
+C3117 pd_buffered_0/tapered_buf_1/a_580_0# vssa1 16.64fF **FLOATING
+C3118 pd_buffered_0/tapered_buf_1/a_160_n140# vssa1 4.00fF **FLOATING
+C3119 pd_buffered_0/pd_0/UP vssa1 5.46fF
+C3120 pd_buffered_0/pd_0/and_pd_0/Z1 vssa1 0.39fF
+C3121 pd_buffered_0/pd_0/and_pd_0/Out1 vssa1 2.22fF
+C3122 pd_buffered_0/pd_0/tspc_r_1/z5 vssa1 1.10fF
+C3123 pd_buffered_0/pd_0/tspc_r_1/Z4 vssa1 1.07fF
+C3124 pd_buffered_0/pd_0/R vssa1 3.05fF
+C3125 pd_buffered_0/pd_0/tspc_r_1/Qbar vssa1 0.79fF
+C3126 pd_buffered_0/pd_0/tspc_r_1/Z2 vssa1 1.22fF
+C3127 pd_buffered_0/pd_0/tspc_r_1/Z1 vssa1 0.67fF
+C3128 pd_buffered_0/pd_0/DOWN vssa1 9.89fF
+C3129 pd_buffered_0/pd_0/tspc_r_1/Qbar1 vssa1 1.34fF
+C3130 pd_buffered_0/pd_0/tspc_r_1/Z3 vssa1 2.12fF
+C3131 pd_buffered_0/pd_0/DIV vssa1 389.98fF
+C3132 pd_buffered_0/pd_0/tspc_r_0/z5 vssa1 1.10fF
+C3133 pd_buffered_0/pd_0/tspc_r_0/Z4 vssa1 1.07fF
+C3134 pd_buffered_0/pd_0/tspc_r_0/Qbar vssa1 0.88fF
+C3135 pd_buffered_0/pd_0/tspc_r_0/Z2 vssa1 1.22fF
+C3136 pd_buffered_0/pd_0/tspc_r_0/Z1 vssa1 0.67fF
+C3137 pd_buffered_0/pd_0/tspc_r_0/Qbar1 vssa1 1.34fF
+C3138 pd_buffered_0/pd_0/tspc_r_0/Z3 vssa1 2.12fF
+C3139 pd_buffered_0/pd_0/REF vssa1 388.35fF
+C3140 pd_buffered_0/tapered_buf_3/in vssa1 1.13fF
+C3141 pd_buffered_0/tapered_buf_3/a_n10_n140# vssa1 0.06fF **FLOATING
+C3142 pd_buffered_0/tapered_buf_3/a_210_n610# vssa1 588.54fF **FLOATING
+C3143 pd_buffered_0/tapered_buf_3/a_160_230# vssa1 0.15fF **FLOATING
+C3144 pd_buffered_0/tapered_buf_3/a_n10_230# vssa1 0.13fF **FLOATING
+C3145 pd_buffered_0/tapered_buf_3/a_4670_0# vssa1 250.63fF **FLOATING
+C3146 pd_buffered_0/tapered_buf_3/a_1650_0# vssa1 63.04fF **FLOATING
+C3147 pd_buffered_0/tapered_buf_3/a_580_0# vssa1 16.64fF **FLOATING
+C3148 pd_buffered_0/tapered_buf_3/a_160_n140# vssa1 4.00fF **FLOATING
+C3149 pd_buffered_0/tapered_buf_2/in vssa1 1.13fF
+C3150 pd_buffered_0/tapered_buf_2/a_n10_n140# vssa1 0.06fF **FLOATING
+C3151 pd_buffered_0/tapered_buf_2/a_210_n610# vssa1 588.54fF **FLOATING
+C3152 pd_buffered_0/tapered_buf_2/a_160_230# vssa1 0.15fF **FLOATING
+C3153 pd_buffered_0/tapered_buf_2/a_n10_230# vssa1 0.13fF **FLOATING
+C3154 pd_buffered_0/tapered_buf_2/a_4670_0# vssa1 250.63fF **FLOATING
+C3155 pd_buffered_0/tapered_buf_2/a_1650_0# vssa1 63.04fF **FLOATING
+C3156 pd_buffered_0/tapered_buf_2/a_580_0# vssa1 16.64fF **FLOATING
+C3157 pd_buffered_0/tapered_buf_2/a_160_n140# vssa1 4.00fF **FLOATING
 .ends