2022-03-21 19:23:40 - [INFO] - {{Project Git Info}} Repository: https://github.com/powergainer/caravel_user_project_analog_vco.git | Branch: main | Commit: 3551e302a3c3473bf6dc56694ee632a3083b2de6
2022-03-21 19:23:40 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: high_speed_vco
2022-03-21 19:23:40 - [INFO] - {{Project Type Info}} analog
2022-03-21 19:23:40 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 5f7fb78ed4148ed3ce9cfd942c980bad967b4b46
2022-03-21 19:23:41 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
2022-03-21 19:23:41 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2022-03-21 19:23:41 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'high_speed_vco/jobs/mpw_precheck/19c7e2ca-8a53-4995-9531-1f4106ea4c23/logs'
2022-03-21 19:23:41 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-03-21 19:23:41 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-03-21 19:23:42 - [INFO] - An approved LICENSE (Apache-2.0) was found in high_speed_vco.
2022-03-21 19:23:42 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-03-21 19:23:43 - [INFO] - An approved LICENSE (Apache-2.0) was found in high_speed_vco.
2022-03-21 19:23:43 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-03-21 19:23:43 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in high_speed_vco/mag/.magicrc
2022-03-21 19:23:43 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in high_speed_vco/mag/3-stage_cs-vco_dp9/.magicrc
2022-03-21 19:23:43 - [ERROR] - SPDX COMPLIANCE SYMLINK FILE NOT FOUND in high_speed_vco/openlane/Makefile
2022-03-21 19:23:43 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 315 non-compliant file(s) with the SPDX Standard.
2022-03-21 19:23:43 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['high_speed_vco/Makefile', 'high_speed_vco/docs/Makefile', 'high_speed_vco/docs/environment.yml', 'high_speed_vco/docs/source/conf.py', 'high_speed_vco/docs/source/index.rst', 'high_speed_vco/mag/3-stage_cs-vco_dp9.ext', 'high_speed_vco/mag/FD_v2.ext', 'high_speed_vco/mag/FD_v5.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_26QSQN.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_44BYND.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_8T82FM.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_B87NCT.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_EMZ8SC.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_HGTGXE_v2.ext', 'high_speed_vco/mag/sky130_fd_pr__nfet_01v8_LS30AB.ext']
2022-03-21 19:23:43 - [INFO] - For the full SPDX compliance report check: high_speed_vco/jobs/mpw_precheck/19c7e2ca-8a53-4995-9531-1f4106ea4c23/logs/spdx_compliance_report.log
2022-03-21 19:23:43 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-03-21 19:23:43 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-03-21 19:23:43 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-03-21 19:23:43 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-03-21 19:23:43 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-03-21 19:23:43 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-03-21 19:23:43 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-03-21 19:23:43 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-03-21 19:23:44 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2022-03-21 19:23:44 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
2022-03-21 19:23:44 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2022-03-21 19:23:44 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2022-03-21 19:23:44 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2022-03-21 19:23:44 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2022-03-21 19:23:44 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (5 instances). 
2022-03-21 19:23:44 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2022-03-21 19:23:44 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2022-03-21 19:23:44 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2022-03-21 19:23:44 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-03-21 19:23:44 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-03-21 19:23:47 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view high_speed_vco/jobs/mpw_precheck/19c7e2ca-8a53-4995-9531-1f4106ea4c23/outputs/user_analog_project_wrapper.xor.gds
2022-03-21 19:23:47 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-03-21 19:23:47 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-03-21 19:23:49 - [INFO] - 0 DRC violations
2022-03-21 19:23:49 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:23:49 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-03-21 19:23:52 - [INFO] - No DRC Violations found
2022-03-21 19:23:52 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:23:52 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-03-21 19:23:57 - [INFO] - No DRC Violations found
2022-03-21 19:23:57 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:23:57 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-03-21 19:23:59 - [INFO] - No DRC Violations found
2022-03-21 19:23:59 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:23:59 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-03-21 19:24:01 - [INFO] - No DRC Violations found
2022-03-21 19:24:01 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:24:01 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-03-21 19:24:02 - [INFO] - No DRC Violations found
2022-03-21 19:24:02 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:24:02 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-03-21 19:24:04 - [INFO] - No DRC Violations found
2022-03-21 19:24:04 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2022-03-21 19:24:04 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'high_speed_vco/jobs/mpw_precheck/19c7e2ca-8a53-4995-9531-1f4106ea4c23/logs'
2022-03-21 19:24:04 - [INFO] - {{SUCCESS}} All Checks Passed !!!