Project Chip ID is: 351763 | |
Setting Project Chip ID to: 00055e13 | |
Step 1: Modify Layout of the user_id_programming subcell | |
Done! | |
Step 2: Add user project ID parameter to source verilog. | |
Done! | |
Step 3: Add user project ID parameter to gate-level verilog. | |
Done! | |
Step 4: Add user project ID text to top level layout. | |
Done! |