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/root/riscduino-qcore__q0_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_axi.sv
/root/riscduino-qcore__q0_/verilog/rtl/yifive/ycr2c/tb/ycr_memory_tb_wb.sv
/root/riscduino-qcore__q0_/verilog/rtl/yifive/ycr2c/tb/ycr_top_tb_runtests.sv