2022-03-20 08:27:19 - [INFO] - {{Project Git Info}} Repository: https://github.com/dineshannayya/riscduino_dcore.git | Branch: main | Commit: 795890a177e9180478b895f4163340f69d9edc39
2022-03-20 08:27:19 - [INFO] - {{EXTRACTING FILES}} Extracting compressed files in: riscduino-dual_core__rd0_
2022-03-20 08:27:24 - [INFO] - {{Project Type Info}} digital
2022-03-20 08:27:25 - [INFO] - {{Project GDS Info}} user_project_wrapper: 197a1b97303ea5f767d1555c44fe5e5a677fa98e
2022-03-20 08:27:25 - [INFO] - {{Tools Info}} KLayout: v0.27.8 | Magic: v8.3.274
2022-03-20 08:27:25 - [INFO] - {{PDKs Info}} Open PDKs: 27ecf1c16911f7dd4428ffab96f62c1fb876ea70 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2022-03-20 08:27:25 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/logs'
2022-03-20 08:27:25 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
2022-03-20 08:27:25 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2022-03-20 08:27:26 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dual_core__rd0_.
2022-03-20 08:27:26 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2022-03-20 08:27:27 - [INFO] - An approved LICENSE (Apache-2.0) was found in riscduino-dual_core__rd0_.
2022-03-20 08:27:27 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/bfm/usb_device/core/usb1d_ctrl.v): 'utf-8' codec can't decode byte 0x96 in position 5130: invalid start byte
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/model/mt48lc8m8a2.v): 'utf-8' codec can't decode byte 0xa9 in position 1830: invalid start byte
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_sspi/.flash1.hex.swp): 'utf-8' codec can't decode byte 0xa0 in position 16: invalid start byte
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_sspi/.sspi_task.v.swp): 'utf-8' codec can't decode byte 0xae in position 16: invalid start byte
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_sspi/.user_sspi_tb.v.swp): 'utf-8' codec can't decode byte 0xe4 in position 20: invalid continuation byte
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_uart/.user_uart.c.un~): 'utf-8' codec can't decode byte 0x9f in position 3: invalid start byte
2022-03-20 08:27:29 - [ERROR] - SPDX COMPLIANCE FILE UNICODE DECODE EXCEPTION in (riscduino-dual_core__rd0_/verilog/dv/user_uart/simx.fst): 'utf-8' codec can't decode byte 0xde in position 22: invalid continuation byte
2022-03-20 08:27:29 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 447 non-compliant file(s) with the SPDX Standard.
2022-03-20 08:27:29 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['riscduino-dual_core__rd0_/Makefile', 'riscduino-dual_core__rd0_/run_regress', 'riscduino-dual_core__rd0_/gds/.magicrc', 'riscduino-dual_core__rd0_/hacks/patch/pdngen.patch', 'riscduino-dual_core__rd0_/hacks/patch/resizer.patch', 'riscduino-dual_core__rd0_/hacks/src/OpenROAD/PdnGen.tcl', 'riscduino-dual_core__rd0_/hacks/src/OpenROAD/Resizer.cc', 'riscduino-dual_core__rd0_/hacks/src/OpenSTA/network/ConcreteNetwork.cc', 'riscduino-dual_core__rd0_/hacks/src/OpenSTA/tcl/NetworkEdit.tcl', 'riscduino-dual_core__rd0_/hacks/src/OpenSTA/tcl/Sta.tcl', 'riscduino-dual_core__rd0_/hacks/src/openlane/io_place.py', 'riscduino-dual_core__rd0_/hacks/src/openlane/synth.tcl', 'riscduino-dual_core__rd0_/hacks/src/openlane/synth_top.tcl', 'riscduino-dual_core__rd0_/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib', 'riscduino-dual_core__rd0_/openlane/Makefile']
2022-03-20 08:27:29 - [INFO] - For the full SPDX compliance report check: riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/logs/spdx_compliance_report.log
2022-03-20 08:27:29 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2022-03-20 08:27:29 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2022-03-20 08:27:29 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2022-03-20 08:27:29 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2022-03-20 08:27:32 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2022-03-20 08:27:32 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2022-03-20 08:27:32 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2022-03-20 08:27:32 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2022-03-20 08:27:39 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2022-03-20 08:27:39 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
2022-03-20 08:27:39 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2022-03-20 08:27:39 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2022-03-20 08:27:39 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2022-03-20 08:27:39 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2022-03-20 08:27:39 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2022-03-20 08:27:39 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (11 instances). 
2022-03-20 08:27:39 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2022-03-20 08:27:39 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2022-03-20 08:27:39 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2022-03-20 08:27:39 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2022-03-20 08:27:39 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2022-03-20 08:27:39 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2022-03-20 08:27:39 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2022-03-20 08:30:14 - [INFO] - {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/outputs/user_project_wrapper.xor.gds
2022-03-20 08:30:14 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2022-03-20 08:30:14 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2022-03-20 08:55:13 - [INFO] - 0 DRC violations
2022-03-20 08:55:13 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 08:55:13 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2022-03-20 08:57:33 - [INFO] - No DRC Violations found
2022-03-20 08:57:33 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 08:57:33 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2022-03-20 09:14:28 - [INFO] - No DRC Violations found
2022-03-20 09:14:28 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 09:14:28 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2022-03-20 09:17:50 - [INFO] - No DRC Violations found
2022-03-20 09:17:50 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 09:17:50 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2022-03-20 09:19:17 - [INFO] - No DRC Violations found
2022-03-20 09:19:17 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 09:19:17 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2022-03-20 09:19:51 - [INFO] - No DRC Violations found
2022-03-20 09:19:51 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 09:19:51 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2022-03-20 09:20:05 - [INFO] - No DRC Violations found
2022-03-20 09:20:05 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2022-03-20 09:20:05 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'riscduino-dual_core__rd0_/jobs/mpw_precheck/c67aad4d-f15f-46c1-ad67-e0fe98739155/logs'
2022-03-20 09:20:05 - [INFO] - {{SUCCESS}} All Checks Passed !!!