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# Created by write_sdc
# Sun Nov 14 09:33:23 2021
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current_design mbist_top
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# Timing Constraints
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create_clock -name bist_clk -period 8.0000 [get_ports {bist_clk}]
create_clock -name func_clk_a -period 8.0000 [get_ports {func_clk_a}]
create_clock -name func_clk_b -period 8.0000 [get_ports {func_clk_b}]
create_generated_clock -name bist_mem_clk_a -add -source [get_ports {bist_clk}] -master_clock [get_clocks bist_clk] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
create_generated_clock -name bist_mem_clk_b -add -source [get_ports {bist_clk}] -master_clock [get_clocks bist_clk] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]

create_generated_clock -name func_mem_clk_a -add -source [get_ports {func_clk_a}] -master_clock [get_clocks func_clk_a] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a]
create_generated_clock -name func_mem_clk_b -add -source [get_ports {func_clk_b}] -master_clock [get_clocks func_clk_b] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b]

set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {bist_clk bist_mem_clk_a bist_mem_clk_b}] -group [get_clocks {func_clk_a func_mem_clk_a}] -group [get_clocks {func_clk_b func_mem_clk_b}] 

set_clock_transition 0.1500 [get_clocks {bist_clk}]
set_clock_uncertainty -setup 0.2500 bist_clk
set_clock_uncertainty -setup 0.2500 mem_clk_a
set_clock_uncertainty -setup 0.2500 mem_clk_b
set_clock_uncertainty -setup 0.2500 func_mem_clk_a
set_clock_uncertainty -setup 0.2500 func_mem_clk_b
set_clock_uncertainty -setup 0.2500 func_clk_a
set_clock_uncertainty -setup 0.2500 func_clk_b

set_clock_uncertainty -hold 0.1500 bist_clk
set_clock_uncertainty -hold 0.1500 mem_clk_a
set_clock_uncertainty -hold 0.1500 mem_clk_b
set_clock_uncertainty -hold 0.1500 func_mem_clk_a
set_clock_uncertainty -hold 0.1500 func_mem_clk_b
set_clock_uncertainty -hold 0.1500 func_clk_a
set_clock_uncertainty -hold 0.1500 func_clk_b

set_input_delay  -max 5.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {rst_n}]
set_input_delay  -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {rst_n}]

set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_correct}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_done}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[0]}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[1]}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[2]}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[3]}]
set_output_delay -max 4.5000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdo}]

set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_correct}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_done}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[0]}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[1]}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[2]}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_error_cnt[3]}]
set_output_delay -min 2.0000 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdo}]

set_false_path -from [get_ports {bist_en}]
set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_load}]
set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_run}]
set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdi}]
set_input_delay -max 4 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_shift}]

set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_en}]
set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_load}]
set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_run}]
set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_sdi}]
set_input_delay -min 2 -clock [get_clocks {bist_clk}] -add_delay [get_ports {bist_shift}]

## Functional Inputs
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[0]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[1]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[2]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[3]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[4]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[5]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[6]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[7]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[8]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_cen_a}]      

set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[0]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[1]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[2]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[3]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[4]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[5]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[6]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[7]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_addr_a[8]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_a}] -add_delay   [get_ports {func_cen_a}]      

set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[0]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[1]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[2]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[3]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[4]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[5]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[6]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[7]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[8]}]  
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_cen_b}]      

set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[0]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[1]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[2]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[3]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[4]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[5]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[6]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[7]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_addr_b[8]}]  
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_cen_b}]      

set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[0]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[10]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[11]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[12]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[13]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[14]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[15]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[16]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[17]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[18]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[19]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[1]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[20]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[21]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[22]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[23]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[24]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[25]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[26]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[27]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[28]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[29]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[2]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[30]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[31]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[3]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[4]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[5]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[6]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[7]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[8]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[9]}] 
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[0]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[1]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[2]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[3]}]
set_input_delay -max 4 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_web_b}]     

set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[0]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[10]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[11]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[12]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[13]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[14]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[15]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[16]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[17]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[18]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[19]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[1]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[20]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[21]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[22]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[23]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[24]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[25]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[26]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[27]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[28]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[29]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[2]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[30]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[31]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[3]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[4]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[5]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[6]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[7]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[8]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_din_b[9]}] 
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[0]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[1]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[2]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_mask_b[3]}]
set_input_delay -min 2 -clock [get_clocks {func_clk_b}] -add_delay   [get_ports {func_web_b}]     

set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[0]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[10]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[11]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[12]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[13]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[14]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[15]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[16]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[17]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[18]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[19]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[1]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[20]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[21]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[22]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[23]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[24]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[25]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[26]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[27]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[28]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[29]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[2]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[30]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[31]}] 
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[3]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[4]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[5]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[6]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[7]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[8]}]  
set_output_delay -max 2 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[9]}]  

set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[0]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[10]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[11]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[12]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[13]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[14]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[15]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[16]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[17]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[18]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[19]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[1]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[20]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[21]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[22]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[23]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[24]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[25]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[26]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[27]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[28]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[29]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[2]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[30]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[31]}] 
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[3]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[4]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[5]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[6]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[7]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[8]}]  
set_output_delay -min 1 -clock [get_clocks {func_clk_a}] -add_delay     [get_ports {func_dout_a[9]}]  


## Towards MEMORY from MBIST CLOCK
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]

set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]


set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]

set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]

set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]

set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]

set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]

#MEM I/F from Functional Clock
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
set_input_delay -max 4.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]

set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[0]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[10]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[11]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[12]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[13]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[14]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[15]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[16]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[17]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[18]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[19]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[1]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[20]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[21]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[22]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[23]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[24]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[25]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[26]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[27]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[28]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[29]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[2]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[30]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[31]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[3]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[4]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[5]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[6]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[7]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[8]}]
set_input_delay -min 1.0000 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_dout_a[9]}]


set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]

set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]

set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[0]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[1]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[2]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[3]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[4]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[5]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[6]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[7]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_a[8]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_a}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]

set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -max 4 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]

set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_cen_b}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[4]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[5]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[6]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[7]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[8]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[9]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[10]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[11]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[12]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[13]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[14]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[15]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[16]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[17]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[18]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[19]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[20]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[21]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[22]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[23]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[24]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[25]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[26]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[27]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[28]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[29]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[30]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_din_b[31]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_mask_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_web_b}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[0]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[1]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[2]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[3]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[4]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[5]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[6]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[7]}]
set_output_delay -min -0.5 -clock [get_clocks {func_mem_clk_a}] -add_delay [get_ports {mem_addr_b[8]}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {bist_correct}]
set_load -pin_load 0.0334 [get_ports {bist_done}]
set_load -pin_load 0.0334 [get_ports {bist_error}]
set_load -pin_load 0.0334 [get_ports {bist_sdo}]
set_load -pin_load 0.0334 [get_ports {mem_cen_a}]
set_load -pin_load 0.0334 [get_ports {mem_cen_b}]
set_load -pin_load 0.0334 [get_ports {mem_clk_a}]
set_load -pin_load 0.0334 [get_ports {mem_clk_b}]
set_load -pin_load 0.0334 [get_ports {mem_web_b}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}]
set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[31]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[30]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[29]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[28]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[27]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[26]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[25]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[24]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[23]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[22]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[21]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[20]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[19]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[18]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[17]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[16]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[15]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[14]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[13]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[12]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[11]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[10]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[9]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[8]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[7]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[6]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[5]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[4]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[3]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[2]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[1]}]
set_load -pin_load 0.0334 [get_ports {func_dout_a[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_a[0]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[8]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[7]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[6]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[5]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[4]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_addr_b[0]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[31]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[30]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[29]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[28]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[27]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[26]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[25]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[24]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[23]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[22]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[21]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[20]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[19]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[18]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[17]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[16]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[15]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[14]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[13]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[12]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[11]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[10]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[9]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[8]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[7]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[6]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[5]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[4]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_din_b[0]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[3]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[2]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[1]}]
set_load -pin_load 0.0334 [get_ports {mem_mask_b[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_cen_a}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_cen_b}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_clk_a}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_clk_b}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_web_b}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_a[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_addr_b[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_din_b[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {func_mask_b[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 4.0000 [current_design]