# Caravel User Project

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Demonstration of the fully open FABulous eFPGA using the OpenLane flow.

This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.

   <p align="center">
   <img src="./docs/source/eFPGA_ver3.png" width="50%" height="50%">
   </p>

Refer to [README](docs/source/index.rst) for this sample project documentation.