diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index 001224f..e69de29 100644
--- a/lef/user_project_wrapper.lef
+++ b/lef/user_project_wrapper.lef
@@ -1,7450 +0,0 @@
-VERSION 5.7 ;
-  NOWIREEXTENSIONATPIN ON ;
-  DIVIDERCHAR "/" ;
-  BUSBITCHARS "[]" ;
-MACRO user_project_wrapper
-  CLASS BLOCK ;
-  FOREIGN user_project_wrapper ;
-  ORIGIN 0.000 0.000 ;
-  SIZE 2920.000 BY 3520.000 ;
-  PIN analog_io[0]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1426.380 2924.800 1427.580 ;
-    END
-  END analog_io[0]
-  PIN analog_io[10]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2230.490 3517.600 2231.050 3524.800 ;
-    END
-  END analog_io[10]
-  PIN analog_io[11]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1905.730 3517.600 1906.290 3524.800 ;
-    END
-  END analog_io[11]
-  PIN analog_io[12]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1581.430 3517.600 1581.990 3524.800 ;
-    END
-  END analog_io[12]
-  PIN analog_io[13]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1257.130 3517.600 1257.690 3524.800 ;
-    END
-  END analog_io[13]
-  PIN analog_io[14]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 932.370 3517.600 932.930 3524.800 ;
-    END
-  END analog_io[14]
-  PIN analog_io[15]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 608.070 3517.600 608.630 3524.800 ;
-    END
-  END analog_io[15]
-  PIN analog_io[16]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 283.770 3517.600 284.330 3524.800 ;
-    END
-  END analog_io[16]
-  PIN analog_io[17]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3486.100 2.400 3487.300 ;
-    END
-  END analog_io[17]
-  PIN analog_io[18]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3224.980 2.400 3226.180 ;
-    END
-  END analog_io[18]
-  PIN analog_io[19]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2964.540 2.400 2965.740 ;
-    END
-  END analog_io[19]
-  PIN analog_io[1]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1692.260 2924.800 1693.460 ;
-    END
-  END analog_io[1]
-  PIN analog_io[20]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2703.420 2.400 2704.620 ;
-    END
-  END analog_io[20]
-  PIN analog_io[21]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2442.980 2.400 2444.180 ;
-    END
-  END analog_io[21]
-  PIN analog_io[22]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2182.540 2.400 2183.740 ;
-    END
-  END analog_io[22]
-  PIN analog_io[23]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1921.420 2.400 1922.620 ;
-    END
-  END analog_io[23]
-  PIN analog_io[24]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1660.980 2.400 1662.180 ;
-    END
-  END analog_io[24]
-  PIN analog_io[25]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1399.860 2.400 1401.060 ;
-    END
-  END analog_io[25]
-  PIN analog_io[26]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1139.420 2.400 1140.620 ;
-    END
-  END analog_io[26]
-  PIN analog_io[27]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 878.980 2.400 880.180 ;
-    END
-  END analog_io[27]
-  PIN analog_io[28]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 617.860 2.400 619.060 ;
-    END
-  END analog_io[28]
-  PIN analog_io[2]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1958.140 2924.800 1959.340 ;
-    END
-  END analog_io[2]
-  PIN analog_io[3]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2223.340 2924.800 2224.540 ;
-    END
-  END analog_io[3]
-  PIN analog_io[4]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2489.220 2924.800 2490.420 ;
-    END
-  END analog_io[4]
-  PIN analog_io[5]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2755.100 2924.800 2756.300 ;
-    END
-  END analog_io[5]
-  PIN analog_io[6]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3020.300 2924.800 3021.500 ;
-    END
-  END analog_io[6]
-  PIN analog_io[7]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3286.180 2924.800 3287.380 ;
-    END
-  END analog_io[7]
-  PIN analog_io[8]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2879.090 3517.600 2879.650 3524.800 ;
-    END
-  END analog_io[8]
-  PIN analog_io[9]
-    DIRECTION INOUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2554.790 3517.600 2555.350 3524.800 ;
-    END
-  END analog_io[9]
-  PIN io_in[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 32.380 2924.800 33.580 ;
-    END
-  END io_in[0]
-  PIN io_in[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2289.980 2924.800 2291.180 ;
-    END
-  END io_in[10]
-  PIN io_in[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2555.860 2924.800 2557.060 ;
-    END
-  END io_in[11]
-  PIN io_in[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2821.060 2924.800 2822.260 ;
-    END
-  END io_in[12]
-  PIN io_in[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3086.940 2924.800 3088.140 ;
-    END
-  END io_in[13]
-  PIN io_in[14]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3352.820 2924.800 3354.020 ;
-    END
-  END io_in[14]
-  PIN io_in[15]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2798.130 3517.600 2798.690 3524.800 ;
-    END
-  END io_in[15]
-  PIN io_in[16]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2473.830 3517.600 2474.390 3524.800 ;
-    END
-  END io_in[16]
-  PIN io_in[17]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2149.070 3517.600 2149.630 3524.800 ;
-    END
-  END io_in[17]
-  PIN io_in[18]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1824.770 3517.600 1825.330 3524.800 ;
-    END
-  END io_in[18]
-  PIN io_in[19]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1500.470 3517.600 1501.030 3524.800 ;
-    END
-  END io_in[19]
-  PIN io_in[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 230.940 2924.800 232.140 ;
-    END
-  END io_in[1]
-  PIN io_in[20]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1175.710 3517.600 1176.270 3524.800 ;
-    END
-  END io_in[20]
-  PIN io_in[21]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 851.410 3517.600 851.970 3524.800 ;
-    END
-  END io_in[21]
-  PIN io_in[22]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 527.110 3517.600 527.670 3524.800 ;
-    END
-  END io_in[22]
-  PIN io_in[23]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 202.350 3517.600 202.910 3524.800 ;
-    END
-  END io_in[23]
-  PIN io_in[24]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3420.820 2.400 3422.020 ;
-    END
-  END io_in[24]
-  PIN io_in[25]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3159.700 2.400 3160.900 ;
-    END
-  END io_in[25]
-  PIN io_in[26]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2899.260 2.400 2900.460 ;
-    END
-  END io_in[26]
-  PIN io_in[27]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2638.820 2.400 2640.020 ;
-    END
-  END io_in[27]
-  PIN io_in[28]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2377.700 2.400 2378.900 ;
-    END
-  END io_in[28]
-  PIN io_in[29]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2117.260 2.400 2118.460 ;
-    END
-  END io_in[29]
-  PIN io_in[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 430.180 2924.800 431.380 ;
-    END
-  END io_in[2]
-  PIN io_in[30]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1856.140 2.400 1857.340 ;
-    END
-  END io_in[30]
-  PIN io_in[31]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1595.700 2.400 1596.900 ;
-    END
-  END io_in[31]
-  PIN io_in[32]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1335.260 2.400 1336.460 ;
-    END
-  END io_in[32]
-  PIN io_in[33]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1074.140 2.400 1075.340 ;
-    END
-  END io_in[33]
-  PIN io_in[34]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 813.700 2.400 814.900 ;
-    END
-  END io_in[34]
-  PIN io_in[35]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 552.580 2.400 553.780 ;
-    END
-  END io_in[35]
-  PIN io_in[36]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 357.420 2.400 358.620 ;
-    END
-  END io_in[36]
-  PIN io_in[37]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 161.580 2.400 162.780 ;
-    END
-  END io_in[37]
-  PIN io_in[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 629.420 2924.800 630.620 ;
-    END
-  END io_in[3]
-  PIN io_in[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 828.660 2924.800 829.860 ;
-    END
-  END io_in[4]
-  PIN io_in[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1027.900 2924.800 1029.100 ;
-    END
-  END io_in[5]
-  PIN io_in[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1227.140 2924.800 1228.340 ;
-    END
-  END io_in[6]
-  PIN io_in[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1493.020 2924.800 1494.220 ;
-    END
-  END io_in[7]
-  PIN io_in[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1758.900 2924.800 1760.100 ;
-    END
-  END io_in[8]
-  PIN io_in[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2024.100 2924.800 2025.300 ;
-    END
-  END io_in[9]
-  PIN io_oeb[0]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 164.980 2924.800 166.180 ;
-    END
-  END io_oeb[0]
-  PIN io_oeb[10]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2422.580 2924.800 2423.780 ;
-    END
-  END io_oeb[10]
-  PIN io_oeb[11]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2688.460 2924.800 2689.660 ;
-    END
-  END io_oeb[11]
-  PIN io_oeb[12]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2954.340 2924.800 2955.540 ;
-    END
-  END io_oeb[12]
-  PIN io_oeb[13]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3219.540 2924.800 3220.740 ;
-    END
-  END io_oeb[13]
-  PIN io_oeb[14]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3485.420 2924.800 3486.620 ;
-    END
-  END io_oeb[14]
-  PIN io_oeb[15]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2635.750 3517.600 2636.310 3524.800 ;
-    END
-  END io_oeb[15]
-  PIN io_oeb[16]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2311.450 3517.600 2312.010 3524.800 ;
-    END
-  END io_oeb[16]
-  PIN io_oeb[17]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1987.150 3517.600 1987.710 3524.800 ;
-    END
-  END io_oeb[17]
-  PIN io_oeb[18]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1662.390 3517.600 1662.950 3524.800 ;
-    END
-  END io_oeb[18]
-  PIN io_oeb[19]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1338.090 3517.600 1338.650 3524.800 ;
-    END
-  END io_oeb[19]
-  PIN io_oeb[1]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 364.220 2924.800 365.420 ;
-    END
-  END io_oeb[1]
-  PIN io_oeb[20]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1013.790 3517.600 1014.350 3524.800 ;
-    END
-  END io_oeb[20]
-  PIN io_oeb[21]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 689.030 3517.600 689.590 3524.800 ;
-    END
-  END io_oeb[21]
-  PIN io_oeb[22]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 364.730 3517.600 365.290 3524.800 ;
-    END
-  END io_oeb[22]
-  PIN io_oeb[23]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 40.430 3517.600 40.990 3524.800 ;
-    END
-  END io_oeb[23]
-  PIN io_oeb[24]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3290.260 2.400 3291.460 ;
-    END
-  END io_oeb[24]
-  PIN io_oeb[25]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3029.820 2.400 3031.020 ;
-    END
-  END io_oeb[25]
-  PIN io_oeb[26]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2768.700 2.400 2769.900 ;
-    END
-  END io_oeb[26]
-  PIN io_oeb[27]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2508.260 2.400 2509.460 ;
-    END
-  END io_oeb[27]
-  PIN io_oeb[28]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2247.140 2.400 2248.340 ;
-    END
-  END io_oeb[28]
-  PIN io_oeb[29]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1986.700 2.400 1987.900 ;
-    END
-  END io_oeb[29]
-  PIN io_oeb[2]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 563.460 2924.800 564.660 ;
-    END
-  END io_oeb[2]
-  PIN io_oeb[30]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1726.260 2.400 1727.460 ;
-    END
-  END io_oeb[30]
-  PIN io_oeb[31]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1465.140 2.400 1466.340 ;
-    END
-  END io_oeb[31]
-  PIN io_oeb[32]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1204.700 2.400 1205.900 ;
-    END
-  END io_oeb[32]
-  PIN io_oeb[33]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 943.580 2.400 944.780 ;
-    END
-  END io_oeb[33]
-  PIN io_oeb[34]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 683.140 2.400 684.340 ;
-    END
-  END io_oeb[34]
-  PIN io_oeb[35]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 422.700 2.400 423.900 ;
-    END
-  END io_oeb[35]
-  PIN io_oeb[36]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 226.860 2.400 228.060 ;
-    END
-  END io_oeb[36]
-  PIN io_oeb[37]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 31.700 2.400 32.900 ;
-    END
-  END io_oeb[37]
-  PIN io_oeb[3]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 762.700 2924.800 763.900 ;
-    END
-  END io_oeb[3]
-  PIN io_oeb[4]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 961.940 2924.800 963.140 ;
-    END
-  END io_oeb[4]
-  PIN io_oeb[5]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1161.180 2924.800 1162.380 ;
-    END
-  END io_oeb[5]
-  PIN io_oeb[6]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1360.420 2924.800 1361.620 ;
-    END
-  END io_oeb[6]
-  PIN io_oeb[7]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1625.620 2924.800 1626.820 ;
-    END
-  END io_oeb[7]
-  PIN io_oeb[8]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1891.500 2924.800 1892.700 ;
-    END
-  END io_oeb[8]
-  PIN io_oeb[9]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2157.380 2924.800 2158.580 ;
-    END
-  END io_oeb[9]
-  PIN io_out[0]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 98.340 2924.800 99.540 ;
-    END
-  END io_out[0]
-  PIN io_out[10]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2356.620 2924.800 2357.820 ;
-    END
-  END io_out[10]
-  PIN io_out[11]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2621.820 2924.800 2623.020 ;
-    END
-  END io_out[11]
-  PIN io_out[12]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2887.700 2924.800 2888.900 ;
-    END
-  END io_out[12]
-  PIN io_out[13]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3153.580 2924.800 3154.780 ;
-    END
-  END io_out[13]
-  PIN io_out[14]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 3418.780 2924.800 3419.980 ;
-    END
-  END io_out[14]
-  PIN io_out[15]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2717.170 3517.600 2717.730 3524.800 ;
-    END
-  END io_out[15]
-  PIN io_out[16]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2392.410 3517.600 2392.970 3524.800 ;
-    END
-  END io_out[16]
-  PIN io_out[17]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2068.110 3517.600 2068.670 3524.800 ;
-    END
-  END io_out[17]
-  PIN io_out[18]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1743.810 3517.600 1744.370 3524.800 ;
-    END
-  END io_out[18]
-  PIN io_out[19]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1419.050 3517.600 1419.610 3524.800 ;
-    END
-  END io_out[19]
-  PIN io_out[1]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 297.580 2924.800 298.780 ;
-    END
-  END io_out[1]
-  PIN io_out[20]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1094.750 3517.600 1095.310 3524.800 ;
-    END
-  END io_out[20]
-  PIN io_out[21]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 770.450 3517.600 771.010 3524.800 ;
-    END
-  END io_out[21]
-  PIN io_out[22]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 445.690 3517.600 446.250 3524.800 ;
-    END
-  END io_out[22]
-  PIN io_out[23]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 121.390 3517.600 121.950 3524.800 ;
-    END
-  END io_out[23]
-  PIN io_out[24]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3355.540 2.400 3356.740 ;
-    END
-  END io_out[24]
-  PIN io_out[25]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 3095.100 2.400 3096.300 ;
-    END
-  END io_out[25]
-  PIN io_out[26]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2833.980 2.400 2835.180 ;
-    END
-  END io_out[26]
-  PIN io_out[27]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2573.540 2.400 2574.740 ;
-    END
-  END io_out[27]
-  PIN io_out[28]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2312.420 2.400 2313.620 ;
-    END
-  END io_out[28]
-  PIN io_out[29]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 2051.980 2.400 2053.180 ;
-    END
-  END io_out[29]
-  PIN io_out[2]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 496.820 2924.800 498.020 ;
-    END
-  END io_out[2]
-  PIN io_out[30]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1791.540 2.400 1792.740 ;
-    END
-  END io_out[30]
-  PIN io_out[31]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1530.420 2.400 1531.620 ;
-    END
-  END io_out[31]
-  PIN io_out[32]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1269.980 2.400 1271.180 ;
-    END
-  END io_out[32]
-  PIN io_out[33]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 1008.860 2.400 1010.060 ;
-    END
-  END io_out[33]
-  PIN io_out[34]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 748.420 2.400 749.620 ;
-    END
-  END io_out[34]
-  PIN io_out[35]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 487.300 2.400 488.500 ;
-    END
-  END io_out[35]
-  PIN io_out[36]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 292.140 2.400 293.340 ;
-    END
-  END io_out[36]
-  PIN io_out[37]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT -4.800 96.300 2.400 97.500 ;
-    END
-  END io_out[37]
-  PIN io_out[3]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 696.060 2924.800 697.260 ;
-    END
-  END io_out[3]
-  PIN io_out[4]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 895.300 2924.800 896.500 ;
-    END
-  END io_out[4]
-  PIN io_out[5]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1094.540 2924.800 1095.740 ;
-    END
-  END io_out[5]
-  PIN io_out[6]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1293.780 2924.800 1294.980 ;
-    END
-  END io_out[6]
-  PIN io_out[7]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1559.660 2924.800 1560.860 ;
-    END
-  END io_out[7]
-  PIN io_out[8]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 1824.860 2924.800 1826.060 ;
-    END
-  END io_out[8]
-  PIN io_out[9]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met3 ;
-        RECT 2917.600 2090.740 2924.800 2091.940 ;
-    END
-  END io_out[9]
-  PIN la_data_in[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 629.230 -4.800 629.790 2.400 ;
-    END
-  END la_data_in[0]
-  PIN la_data_in[100]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2402.530 -4.800 2403.090 2.400 ;
-    END
-  END la_data_in[100]
-  PIN la_data_in[101]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2420.010 -4.800 2420.570 2.400 ;
-    END
-  END la_data_in[101]
-  PIN la_data_in[102]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2437.950 -4.800 2438.510 2.400 ;
-    END
-  END la_data_in[102]
-  PIN la_data_in[103]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2455.430 -4.800 2455.990 2.400 ;
-    END
-  END la_data_in[103]
-  PIN la_data_in[104]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2473.370 -4.800 2473.930 2.400 ;
-    END
-  END la_data_in[104]
-  PIN la_data_in[105]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2490.850 -4.800 2491.410 2.400 ;
-    END
-  END la_data_in[105]
-  PIN la_data_in[106]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2508.790 -4.800 2509.350 2.400 ;
-    END
-  END la_data_in[106]
-  PIN la_data_in[107]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2526.730 -4.800 2527.290 2.400 ;
-    END
-  END la_data_in[107]
-  PIN la_data_in[108]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2544.210 -4.800 2544.770 2.400 ;
-    END
-  END la_data_in[108]
-  PIN la_data_in[109]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2562.150 -4.800 2562.710 2.400 ;
-    END
-  END la_data_in[109]
-  PIN la_data_in[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 806.330 -4.800 806.890 2.400 ;
-    END
-  END la_data_in[10]
-  PIN la_data_in[110]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2579.630 -4.800 2580.190 2.400 ;
-    END
-  END la_data_in[110]
-  PIN la_data_in[111]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2597.570 -4.800 2598.130 2.400 ;
-    END
-  END la_data_in[111]
-  PIN la_data_in[112]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2615.050 -4.800 2615.610 2.400 ;
-    END
-  END la_data_in[112]
-  PIN la_data_in[113]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2632.990 -4.800 2633.550 2.400 ;
-    END
-  END la_data_in[113]
-  PIN la_data_in[114]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2650.470 -4.800 2651.030 2.400 ;
-    END
-  END la_data_in[114]
-  PIN la_data_in[115]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2668.410 -4.800 2668.970 2.400 ;
-    END
-  END la_data_in[115]
-  PIN la_data_in[116]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2685.890 -4.800 2686.450 2.400 ;
-    END
-  END la_data_in[116]
-  PIN la_data_in[117]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2703.830 -4.800 2704.390 2.400 ;
-    END
-  END la_data_in[117]
-  PIN la_data_in[118]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2721.770 -4.800 2722.330 2.400 ;
-    END
-  END la_data_in[118]
-  PIN la_data_in[119]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2739.250 -4.800 2739.810 2.400 ;
-    END
-  END la_data_in[119]
-  PIN la_data_in[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 824.270 -4.800 824.830 2.400 ;
-    END
-  END la_data_in[11]
-  PIN la_data_in[120]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2757.190 -4.800 2757.750 2.400 ;
-    END
-  END la_data_in[120]
-  PIN la_data_in[121]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2774.670 -4.800 2775.230 2.400 ;
-    END
-  END la_data_in[121]
-  PIN la_data_in[122]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2792.610 -4.800 2793.170 2.400 ;
-    END
-  END la_data_in[122]
-  PIN la_data_in[123]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2810.090 -4.800 2810.650 2.400 ;
-    END
-  END la_data_in[123]
-  PIN la_data_in[124]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2828.030 -4.800 2828.590 2.400 ;
-    END
-  END la_data_in[124]
-  PIN la_data_in[125]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2845.510 -4.800 2846.070 2.400 ;
-    END
-  END la_data_in[125]
-  PIN la_data_in[126]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2863.450 -4.800 2864.010 2.400 ;
-    END
-  END la_data_in[126]
-  PIN la_data_in[127]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2881.390 -4.800 2881.950 2.400 ;
-    END
-  END la_data_in[127]
-  PIN la_data_in[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 841.750 -4.800 842.310 2.400 ;
-    END
-  END la_data_in[12]
-  PIN la_data_in[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 859.690 -4.800 860.250 2.400 ;
-    END
-  END la_data_in[13]
-  PIN la_data_in[14]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 877.170 -4.800 877.730 2.400 ;
-    END
-  END la_data_in[14]
-  PIN la_data_in[15]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 895.110 -4.800 895.670 2.400 ;
-    END
-  END la_data_in[15]
-  PIN la_data_in[16]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 912.590 -4.800 913.150 2.400 ;
-    END
-  END la_data_in[16]
-  PIN la_data_in[17]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 930.530 -4.800 931.090 2.400 ;
-    END
-  END la_data_in[17]
-  PIN la_data_in[18]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 948.470 -4.800 949.030 2.400 ;
-    END
-  END la_data_in[18]
-  PIN la_data_in[19]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 965.950 -4.800 966.510 2.400 ;
-    END
-  END la_data_in[19]
-  PIN la_data_in[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 646.710 -4.800 647.270 2.400 ;
-    END
-  END la_data_in[1]
-  PIN la_data_in[20]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 983.890 -4.800 984.450 2.400 ;
-    END
-  END la_data_in[20]
-  PIN la_data_in[21]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1001.370 -4.800 1001.930 2.400 ;
-    END
-  END la_data_in[21]
-  PIN la_data_in[22]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1019.310 -4.800 1019.870 2.400 ;
-    END
-  END la_data_in[22]
-  PIN la_data_in[23]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1036.790 -4.800 1037.350 2.400 ;
-    END
-  END la_data_in[23]
-  PIN la_data_in[24]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1054.730 -4.800 1055.290 2.400 ;
-    END
-  END la_data_in[24]
-  PIN la_data_in[25]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1072.210 -4.800 1072.770 2.400 ;
-    END
-  END la_data_in[25]
-  PIN la_data_in[26]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1090.150 -4.800 1090.710 2.400 ;
-    END
-  END la_data_in[26]
-  PIN la_data_in[27]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1107.630 -4.800 1108.190 2.400 ;
-    END
-  END la_data_in[27]
-  PIN la_data_in[28]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1125.570 -4.800 1126.130 2.400 ;
-    END
-  END la_data_in[28]
-  PIN la_data_in[29]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1143.510 -4.800 1144.070 2.400 ;
-    END
-  END la_data_in[29]
-  PIN la_data_in[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 664.650 -4.800 665.210 2.400 ;
-    END
-  END la_data_in[2]
-  PIN la_data_in[30]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1160.990 -4.800 1161.550 2.400 ;
-    END
-  END la_data_in[30]
-  PIN la_data_in[31]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1178.930 -4.800 1179.490 2.400 ;
-    END
-  END la_data_in[31]
-  PIN la_data_in[32]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1196.410 -4.800 1196.970 2.400 ;
-    END
-  END la_data_in[32]
-  PIN la_data_in[33]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1214.350 -4.800 1214.910 2.400 ;
-    END
-  END la_data_in[33]
-  PIN la_data_in[34]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1231.830 -4.800 1232.390 2.400 ;
-    END
-  END la_data_in[34]
-  PIN la_data_in[35]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1249.770 -4.800 1250.330 2.400 ;
-    END
-  END la_data_in[35]
-  PIN la_data_in[36]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1267.250 -4.800 1267.810 2.400 ;
-    END
-  END la_data_in[36]
-  PIN la_data_in[37]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1285.190 -4.800 1285.750 2.400 ;
-    END
-  END la_data_in[37]
-  PIN la_data_in[38]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1303.130 -4.800 1303.690 2.400 ;
-    END
-  END la_data_in[38]
-  PIN la_data_in[39]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1320.610 -4.800 1321.170 2.400 ;
-    END
-  END la_data_in[39]
-  PIN la_data_in[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 682.130 -4.800 682.690 2.400 ;
-    END
-  END la_data_in[3]
-  PIN la_data_in[40]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1338.550 -4.800 1339.110 2.400 ;
-    END
-  END la_data_in[40]
-  PIN la_data_in[41]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1356.030 -4.800 1356.590 2.400 ;
-    END
-  END la_data_in[41]
-  PIN la_data_in[42]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1373.970 -4.800 1374.530 2.400 ;
-    END
-  END la_data_in[42]
-  PIN la_data_in[43]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1391.450 -4.800 1392.010 2.400 ;
-    END
-  END la_data_in[43]
-  PIN la_data_in[44]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1409.390 -4.800 1409.950 2.400 ;
-    END
-  END la_data_in[44]
-  PIN la_data_in[45]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1426.870 -4.800 1427.430 2.400 ;
-    END
-  END la_data_in[45]
-  PIN la_data_in[46]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1444.810 -4.800 1445.370 2.400 ;
-    END
-  END la_data_in[46]
-  PIN la_data_in[47]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1462.750 -4.800 1463.310 2.400 ;
-    END
-  END la_data_in[47]
-  PIN la_data_in[48]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1480.230 -4.800 1480.790 2.400 ;
-    END
-  END la_data_in[48]
-  PIN la_data_in[49]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1498.170 -4.800 1498.730 2.400 ;
-    END
-  END la_data_in[49]
-  PIN la_data_in[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 700.070 -4.800 700.630 2.400 ;
-    END
-  END la_data_in[4]
-  PIN la_data_in[50]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1515.650 -4.800 1516.210 2.400 ;
-    END
-  END la_data_in[50]
-  PIN la_data_in[51]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1533.590 -4.800 1534.150 2.400 ;
-    END
-  END la_data_in[51]
-  PIN la_data_in[52]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1551.070 -4.800 1551.630 2.400 ;
-    END
-  END la_data_in[52]
-  PIN la_data_in[53]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1569.010 -4.800 1569.570 2.400 ;
-    END
-  END la_data_in[53]
-  PIN la_data_in[54]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1586.490 -4.800 1587.050 2.400 ;
-    END
-  END la_data_in[54]
-  PIN la_data_in[55]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1604.430 -4.800 1604.990 2.400 ;
-    END
-  END la_data_in[55]
-  PIN la_data_in[56]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1621.910 -4.800 1622.470 2.400 ;
-    END
-  END la_data_in[56]
-  PIN la_data_in[57]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1639.850 -4.800 1640.410 2.400 ;
-    END
-  END la_data_in[57]
-  PIN la_data_in[58]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1657.790 -4.800 1658.350 2.400 ;
-    END
-  END la_data_in[58]
-  PIN la_data_in[59]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1675.270 -4.800 1675.830 2.400 ;
-    END
-  END la_data_in[59]
-  PIN la_data_in[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 717.550 -4.800 718.110 2.400 ;
-    END
-  END la_data_in[5]
-  PIN la_data_in[60]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1693.210 -4.800 1693.770 2.400 ;
-    END
-  END la_data_in[60]
-  PIN la_data_in[61]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1710.690 -4.800 1711.250 2.400 ;
-    END
-  END la_data_in[61]
-  PIN la_data_in[62]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1728.630 -4.800 1729.190 2.400 ;
-    END
-  END la_data_in[62]
-  PIN la_data_in[63]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1746.110 -4.800 1746.670 2.400 ;
-    END
-  END la_data_in[63]
-  PIN la_data_in[64]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1764.050 -4.800 1764.610 2.400 ;
-    END
-  END la_data_in[64]
-  PIN la_data_in[65]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1781.530 -4.800 1782.090 2.400 ;
-    END
-  END la_data_in[65]
-  PIN la_data_in[66]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1799.470 -4.800 1800.030 2.400 ;
-    END
-  END la_data_in[66]
-  PIN la_data_in[67]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1817.410 -4.800 1817.970 2.400 ;
-    END
-  END la_data_in[67]
-  PIN la_data_in[68]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1834.890 -4.800 1835.450 2.400 ;
-    END
-  END la_data_in[68]
-  PIN la_data_in[69]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1852.830 -4.800 1853.390 2.400 ;
-    END
-  END la_data_in[69]
-  PIN la_data_in[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 735.490 -4.800 736.050 2.400 ;
-    END
-  END la_data_in[6]
-  PIN la_data_in[70]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1870.310 -4.800 1870.870 2.400 ;
-    END
-  END la_data_in[70]
-  PIN la_data_in[71]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1888.250 -4.800 1888.810 2.400 ;
-    END
-  END la_data_in[71]
-  PIN la_data_in[72]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1905.730 -4.800 1906.290 2.400 ;
-    END
-  END la_data_in[72]
-  PIN la_data_in[73]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1923.670 -4.800 1924.230 2.400 ;
-    END
-  END la_data_in[73]
-  PIN la_data_in[74]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1941.150 -4.800 1941.710 2.400 ;
-    END
-  END la_data_in[74]
-  PIN la_data_in[75]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1959.090 -4.800 1959.650 2.400 ;
-    END
-  END la_data_in[75]
-  PIN la_data_in[76]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1976.570 -4.800 1977.130 2.400 ;
-    END
-  END la_data_in[76]
-  PIN la_data_in[77]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1994.510 -4.800 1995.070 2.400 ;
-    END
-  END la_data_in[77]
-  PIN la_data_in[78]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2012.450 -4.800 2013.010 2.400 ;
-    END
-  END la_data_in[78]
-  PIN la_data_in[79]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2029.930 -4.800 2030.490 2.400 ;
-    END
-  END la_data_in[79]
-  PIN la_data_in[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 752.970 -4.800 753.530 2.400 ;
-    END
-  END la_data_in[7]
-  PIN la_data_in[80]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2047.870 -4.800 2048.430 2.400 ;
-    END
-  END la_data_in[80]
-  PIN la_data_in[81]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2065.350 -4.800 2065.910 2.400 ;
-    END
-  END la_data_in[81]
-  PIN la_data_in[82]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2083.290 -4.800 2083.850 2.400 ;
-    END
-  END la_data_in[82]
-  PIN la_data_in[83]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2100.770 -4.800 2101.330 2.400 ;
-    END
-  END la_data_in[83]
-  PIN la_data_in[84]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2118.710 -4.800 2119.270 2.400 ;
-    END
-  END la_data_in[84]
-  PIN la_data_in[85]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2136.190 -4.800 2136.750 2.400 ;
-    END
-  END la_data_in[85]
-  PIN la_data_in[86]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2154.130 -4.800 2154.690 2.400 ;
-    END
-  END la_data_in[86]
-  PIN la_data_in[87]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2172.070 -4.800 2172.630 2.400 ;
-    END
-  END la_data_in[87]
-  PIN la_data_in[88]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2189.550 -4.800 2190.110 2.400 ;
-    END
-  END la_data_in[88]
-  PIN la_data_in[89]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2207.490 -4.800 2208.050 2.400 ;
-    END
-  END la_data_in[89]
-  PIN la_data_in[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 770.910 -4.800 771.470 2.400 ;
-    END
-  END la_data_in[8]
-  PIN la_data_in[90]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2224.970 -4.800 2225.530 2.400 ;
-    END
-  END la_data_in[90]
-  PIN la_data_in[91]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2242.910 -4.800 2243.470 2.400 ;
-    END
-  END la_data_in[91]
-  PIN la_data_in[92]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2260.390 -4.800 2260.950 2.400 ;
-    END
-  END la_data_in[92]
-  PIN la_data_in[93]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2278.330 -4.800 2278.890 2.400 ;
-    END
-  END la_data_in[93]
-  PIN la_data_in[94]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2295.810 -4.800 2296.370 2.400 ;
-    END
-  END la_data_in[94]
-  PIN la_data_in[95]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2313.750 -4.800 2314.310 2.400 ;
-    END
-  END la_data_in[95]
-  PIN la_data_in[96]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2331.230 -4.800 2331.790 2.400 ;
-    END
-  END la_data_in[96]
-  PIN la_data_in[97]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2349.170 -4.800 2349.730 2.400 ;
-    END
-  END la_data_in[97]
-  PIN la_data_in[98]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2367.110 -4.800 2367.670 2.400 ;
-    END
-  END la_data_in[98]
-  PIN la_data_in[99]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2384.590 -4.800 2385.150 2.400 ;
-    END
-  END la_data_in[99]
-  PIN la_data_in[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 788.850 -4.800 789.410 2.400 ;
-    END
-  END la_data_in[9]
-  PIN la_data_out[0]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 634.750 -4.800 635.310 2.400 ;
-    END
-  END la_data_out[0]
-  PIN la_data_out[100]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2408.510 -4.800 2409.070 2.400 ;
-    END
-  END la_data_out[100]
-  PIN la_data_out[101]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2425.990 -4.800 2426.550 2.400 ;
-    END
-  END la_data_out[101]
-  PIN la_data_out[102]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2443.930 -4.800 2444.490 2.400 ;
-    END
-  END la_data_out[102]
-  PIN la_data_out[103]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2461.410 -4.800 2461.970 2.400 ;
-    END
-  END la_data_out[103]
-  PIN la_data_out[104]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2479.350 -4.800 2479.910 2.400 ;
-    END
-  END la_data_out[104]
-  PIN la_data_out[105]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2496.830 -4.800 2497.390 2.400 ;
-    END
-  END la_data_out[105]
-  PIN la_data_out[106]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2514.770 -4.800 2515.330 2.400 ;
-    END
-  END la_data_out[106]
-  PIN la_data_out[107]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2532.250 -4.800 2532.810 2.400 ;
-    END
-  END la_data_out[107]
-  PIN la_data_out[108]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2550.190 -4.800 2550.750 2.400 ;
-    END
-  END la_data_out[108]
-  PIN la_data_out[109]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2567.670 -4.800 2568.230 2.400 ;
-    END
-  END la_data_out[109]
-  PIN la_data_out[10]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 812.310 -4.800 812.870 2.400 ;
-    END
-  END la_data_out[10]
-  PIN la_data_out[110]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2585.610 -4.800 2586.170 2.400 ;
-    END
-  END la_data_out[110]
-  PIN la_data_out[111]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2603.550 -4.800 2604.110 2.400 ;
-    END
-  END la_data_out[111]
-  PIN la_data_out[112]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2621.030 -4.800 2621.590 2.400 ;
-    END
-  END la_data_out[112]
-  PIN la_data_out[113]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2638.970 -4.800 2639.530 2.400 ;
-    END
-  END la_data_out[113]
-  PIN la_data_out[114]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2656.450 -4.800 2657.010 2.400 ;
-    END
-  END la_data_out[114]
-  PIN la_data_out[115]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2674.390 -4.800 2674.950 2.400 ;
-    END
-  END la_data_out[115]
-  PIN la_data_out[116]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2691.870 -4.800 2692.430 2.400 ;
-    END
-  END la_data_out[116]
-  PIN la_data_out[117]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2709.810 -4.800 2710.370 2.400 ;
-    END
-  END la_data_out[117]
-  PIN la_data_out[118]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2727.290 -4.800 2727.850 2.400 ;
-    END
-  END la_data_out[118]
-  PIN la_data_out[119]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2745.230 -4.800 2745.790 2.400 ;
-    END
-  END la_data_out[119]
-  PIN la_data_out[11]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 830.250 -4.800 830.810 2.400 ;
-    END
-  END la_data_out[11]
-  PIN la_data_out[120]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2763.170 -4.800 2763.730 2.400 ;
-    END
-  END la_data_out[120]
-  PIN la_data_out[121]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2780.650 -4.800 2781.210 2.400 ;
-    END
-  END la_data_out[121]
-  PIN la_data_out[122]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2798.590 -4.800 2799.150 2.400 ;
-    END
-  END la_data_out[122]
-  PIN la_data_out[123]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2816.070 -4.800 2816.630 2.400 ;
-    END
-  END la_data_out[123]
-  PIN la_data_out[124]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2834.010 -4.800 2834.570 2.400 ;
-    END
-  END la_data_out[124]
-  PIN la_data_out[125]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2851.490 -4.800 2852.050 2.400 ;
-    END
-  END la_data_out[125]
-  PIN la_data_out[126]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2869.430 -4.800 2869.990 2.400 ;
-    END
-  END la_data_out[126]
-  PIN la_data_out[127]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2886.910 -4.800 2887.470 2.400 ;
-    END
-  END la_data_out[127]
-  PIN la_data_out[12]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 847.730 -4.800 848.290 2.400 ;
-    END
-  END la_data_out[12]
-  PIN la_data_out[13]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 865.670 -4.800 866.230 2.400 ;
-    END
-  END la_data_out[13]
-  PIN la_data_out[14]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 883.150 -4.800 883.710 2.400 ;
-    END
-  END la_data_out[14]
-  PIN la_data_out[15]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 901.090 -4.800 901.650 2.400 ;
-    END
-  END la_data_out[15]
-  PIN la_data_out[16]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 918.570 -4.800 919.130 2.400 ;
-    END
-  END la_data_out[16]
-  PIN la_data_out[17]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 936.510 -4.800 937.070 2.400 ;
-    END
-  END la_data_out[17]
-  PIN la_data_out[18]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 953.990 -4.800 954.550 2.400 ;
-    END
-  END la_data_out[18]
-  PIN la_data_out[19]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 971.930 -4.800 972.490 2.400 ;
-    END
-  END la_data_out[19]
-  PIN la_data_out[1]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 652.690 -4.800 653.250 2.400 ;
-    END
-  END la_data_out[1]
-  PIN la_data_out[20]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 989.410 -4.800 989.970 2.400 ;
-    END
-  END la_data_out[20]
-  PIN la_data_out[21]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1007.350 -4.800 1007.910 2.400 ;
-    END
-  END la_data_out[21]
-  PIN la_data_out[22]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1025.290 -4.800 1025.850 2.400 ;
-    END
-  END la_data_out[22]
-  PIN la_data_out[23]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1042.770 -4.800 1043.330 2.400 ;
-    END
-  END la_data_out[23]
-  PIN la_data_out[24]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1060.710 -4.800 1061.270 2.400 ;
-    END
-  END la_data_out[24]
-  PIN la_data_out[25]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1078.190 -4.800 1078.750 2.400 ;
-    END
-  END la_data_out[25]
-  PIN la_data_out[26]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1096.130 -4.800 1096.690 2.400 ;
-    END
-  END la_data_out[26]
-  PIN la_data_out[27]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1113.610 -4.800 1114.170 2.400 ;
-    END
-  END la_data_out[27]
-  PIN la_data_out[28]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1131.550 -4.800 1132.110 2.400 ;
-    END
-  END la_data_out[28]
-  PIN la_data_out[29]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1149.030 -4.800 1149.590 2.400 ;
-    END
-  END la_data_out[29]
-  PIN la_data_out[2]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 670.630 -4.800 671.190 2.400 ;
-    END
-  END la_data_out[2]
-  PIN la_data_out[30]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1166.970 -4.800 1167.530 2.400 ;
-    END
-  END la_data_out[30]
-  PIN la_data_out[31]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1184.910 -4.800 1185.470 2.400 ;
-    END
-  END la_data_out[31]
-  PIN la_data_out[32]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1202.390 -4.800 1202.950 2.400 ;
-    END
-  END la_data_out[32]
-  PIN la_data_out[33]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1220.330 -4.800 1220.890 2.400 ;
-    END
-  END la_data_out[33]
-  PIN la_data_out[34]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1237.810 -4.800 1238.370 2.400 ;
-    END
-  END la_data_out[34]
-  PIN la_data_out[35]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1255.750 -4.800 1256.310 2.400 ;
-    END
-  END la_data_out[35]
-  PIN la_data_out[36]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1273.230 -4.800 1273.790 2.400 ;
-    END
-  END la_data_out[36]
-  PIN la_data_out[37]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1291.170 -4.800 1291.730 2.400 ;
-    END
-  END la_data_out[37]
-  PIN la_data_out[38]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1308.650 -4.800 1309.210 2.400 ;
-    END
-  END la_data_out[38]
-  PIN la_data_out[39]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1326.590 -4.800 1327.150 2.400 ;
-    END
-  END la_data_out[39]
-  PIN la_data_out[3]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 688.110 -4.800 688.670 2.400 ;
-    END
-  END la_data_out[3]
-  PIN la_data_out[40]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1344.070 -4.800 1344.630 2.400 ;
-    END
-  END la_data_out[40]
-  PIN la_data_out[41]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1362.010 -4.800 1362.570 2.400 ;
-    END
-  END la_data_out[41]
-  PIN la_data_out[42]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1379.950 -4.800 1380.510 2.400 ;
-    END
-  END la_data_out[42]
-  PIN la_data_out[43]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1397.430 -4.800 1397.990 2.400 ;
-    END
-  END la_data_out[43]
-  PIN la_data_out[44]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1415.370 -4.800 1415.930 2.400 ;
-    END
-  END la_data_out[44]
-  PIN la_data_out[45]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1432.850 -4.800 1433.410 2.400 ;
-    END
-  END la_data_out[45]
-  PIN la_data_out[46]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1450.790 -4.800 1451.350 2.400 ;
-    END
-  END la_data_out[46]
-  PIN la_data_out[47]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1468.270 -4.800 1468.830 2.400 ;
-    END
-  END la_data_out[47]
-  PIN la_data_out[48]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1486.210 -4.800 1486.770 2.400 ;
-    END
-  END la_data_out[48]
-  PIN la_data_out[49]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1503.690 -4.800 1504.250 2.400 ;
-    END
-  END la_data_out[49]
-  PIN la_data_out[4]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 706.050 -4.800 706.610 2.400 ;
-    END
-  END la_data_out[4]
-  PIN la_data_out[50]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1521.630 -4.800 1522.190 2.400 ;
-    END
-  END la_data_out[50]
-  PIN la_data_out[51]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1539.570 -4.800 1540.130 2.400 ;
-    END
-  END la_data_out[51]
-  PIN la_data_out[52]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1557.050 -4.800 1557.610 2.400 ;
-    END
-  END la_data_out[52]
-  PIN la_data_out[53]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1574.990 -4.800 1575.550 2.400 ;
-    END
-  END la_data_out[53]
-  PIN la_data_out[54]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1592.470 -4.800 1593.030 2.400 ;
-    END
-  END la_data_out[54]
-  PIN la_data_out[55]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1610.410 -4.800 1610.970 2.400 ;
-    END
-  END la_data_out[55]
-  PIN la_data_out[56]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1627.890 -4.800 1628.450 2.400 ;
-    END
-  END la_data_out[56]
-  PIN la_data_out[57]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1645.830 -4.800 1646.390 2.400 ;
-    END
-  END la_data_out[57]
-  PIN la_data_out[58]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1663.310 -4.800 1663.870 2.400 ;
-    END
-  END la_data_out[58]
-  PIN la_data_out[59]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1681.250 -4.800 1681.810 2.400 ;
-    END
-  END la_data_out[59]
-  PIN la_data_out[5]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 723.530 -4.800 724.090 2.400 ;
-    END
-  END la_data_out[5]
-  PIN la_data_out[60]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1699.190 -4.800 1699.750 2.400 ;
-    END
-  END la_data_out[60]
-  PIN la_data_out[61]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1716.670 -4.800 1717.230 2.400 ;
-    END
-  END la_data_out[61]
-  PIN la_data_out[62]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1734.610 -4.800 1735.170 2.400 ;
-    END
-  END la_data_out[62]
-  PIN la_data_out[63]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1752.090 -4.800 1752.650 2.400 ;
-    END
-  END la_data_out[63]
-  PIN la_data_out[64]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1770.030 -4.800 1770.590 2.400 ;
-    END
-  END la_data_out[64]
-  PIN la_data_out[65]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1787.510 -4.800 1788.070 2.400 ;
-    END
-  END la_data_out[65]
-  PIN la_data_out[66]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1805.450 -4.800 1806.010 2.400 ;
-    END
-  END la_data_out[66]
-  PIN la_data_out[67]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1822.930 -4.800 1823.490 2.400 ;
-    END
-  END la_data_out[67]
-  PIN la_data_out[68]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1840.870 -4.800 1841.430 2.400 ;
-    END
-  END la_data_out[68]
-  PIN la_data_out[69]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1858.350 -4.800 1858.910 2.400 ;
-    END
-  END la_data_out[69]
-  PIN la_data_out[6]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 741.470 -4.800 742.030 2.400 ;
-    END
-  END la_data_out[6]
-  PIN la_data_out[70]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1876.290 -4.800 1876.850 2.400 ;
-    END
-  END la_data_out[70]
-  PIN la_data_out[71]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1894.230 -4.800 1894.790 2.400 ;
-    END
-  END la_data_out[71]
-  PIN la_data_out[72]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1911.710 -4.800 1912.270 2.400 ;
-    END
-  END la_data_out[72]
-  PIN la_data_out[73]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1929.650 -4.800 1930.210 2.400 ;
-    END
-  END la_data_out[73]
-  PIN la_data_out[74]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1947.130 -4.800 1947.690 2.400 ;
-    END
-  END la_data_out[74]
-  PIN la_data_out[75]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1965.070 -4.800 1965.630 2.400 ;
-    END
-  END la_data_out[75]
-  PIN la_data_out[76]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1982.550 -4.800 1983.110 2.400 ;
-    END
-  END la_data_out[76]
-  PIN la_data_out[77]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2000.490 -4.800 2001.050 2.400 ;
-    END
-  END la_data_out[77]
-  PIN la_data_out[78]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2017.970 -4.800 2018.530 2.400 ;
-    END
-  END la_data_out[78]
-  PIN la_data_out[79]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2035.910 -4.800 2036.470 2.400 ;
-    END
-  END la_data_out[79]
-  PIN la_data_out[7]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 758.950 -4.800 759.510 2.400 ;
-    END
-  END la_data_out[7]
-  PIN la_data_out[80]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2053.850 -4.800 2054.410 2.400 ;
-    END
-  END la_data_out[80]
-  PIN la_data_out[81]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2071.330 -4.800 2071.890 2.400 ;
-    END
-  END la_data_out[81]
-  PIN la_data_out[82]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2089.270 -4.800 2089.830 2.400 ;
-    END
-  END la_data_out[82]
-  PIN la_data_out[83]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2106.750 -4.800 2107.310 2.400 ;
-    END
-  END la_data_out[83]
-  PIN la_data_out[84]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2124.690 -4.800 2125.250 2.400 ;
-    END
-  END la_data_out[84]
-  PIN la_data_out[85]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2142.170 -4.800 2142.730 2.400 ;
-    END
-  END la_data_out[85]
-  PIN la_data_out[86]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2160.110 -4.800 2160.670 2.400 ;
-    END
-  END la_data_out[86]
-  PIN la_data_out[87]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2177.590 -4.800 2178.150 2.400 ;
-    END
-  END la_data_out[87]
-  PIN la_data_out[88]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2195.530 -4.800 2196.090 2.400 ;
-    END
-  END la_data_out[88]
-  PIN la_data_out[89]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2213.010 -4.800 2213.570 2.400 ;
-    END
-  END la_data_out[89]
-  PIN la_data_out[8]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 776.890 -4.800 777.450 2.400 ;
-    END
-  END la_data_out[8]
-  PIN la_data_out[90]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2230.950 -4.800 2231.510 2.400 ;
-    END
-  END la_data_out[90]
-  PIN la_data_out[91]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2248.890 -4.800 2249.450 2.400 ;
-    END
-  END la_data_out[91]
-  PIN la_data_out[92]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2266.370 -4.800 2266.930 2.400 ;
-    END
-  END la_data_out[92]
-  PIN la_data_out[93]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2284.310 -4.800 2284.870 2.400 ;
-    END
-  END la_data_out[93]
-  PIN la_data_out[94]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2301.790 -4.800 2302.350 2.400 ;
-    END
-  END la_data_out[94]
-  PIN la_data_out[95]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2319.730 -4.800 2320.290 2.400 ;
-    END
-  END la_data_out[95]
-  PIN la_data_out[96]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2337.210 -4.800 2337.770 2.400 ;
-    END
-  END la_data_out[96]
-  PIN la_data_out[97]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2355.150 -4.800 2355.710 2.400 ;
-    END
-  END la_data_out[97]
-  PIN la_data_out[98]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2372.630 -4.800 2373.190 2.400 ;
-    END
-  END la_data_out[98]
-  PIN la_data_out[99]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2390.570 -4.800 2391.130 2.400 ;
-    END
-  END la_data_out[99]
-  PIN la_data_out[9]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 794.370 -4.800 794.930 2.400 ;
-    END
-  END la_data_out[9]
-  PIN la_oenb[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 640.730 -4.800 641.290 2.400 ;
-    END
-  END la_oenb[0]
-  PIN la_oenb[100]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2414.030 -4.800 2414.590 2.400 ;
-    END
-  END la_oenb[100]
-  PIN la_oenb[101]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2431.970 -4.800 2432.530 2.400 ;
-    END
-  END la_oenb[101]
-  PIN la_oenb[102]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2449.450 -4.800 2450.010 2.400 ;
-    END
-  END la_oenb[102]
-  PIN la_oenb[103]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2467.390 -4.800 2467.950 2.400 ;
-    END
-  END la_oenb[103]
-  PIN la_oenb[104]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2485.330 -4.800 2485.890 2.400 ;
-    END
-  END la_oenb[104]
-  PIN la_oenb[105]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2502.810 -4.800 2503.370 2.400 ;
-    END
-  END la_oenb[105]
-  PIN la_oenb[106]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2520.750 -4.800 2521.310 2.400 ;
-    END
-  END la_oenb[106]
-  PIN la_oenb[107]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2538.230 -4.800 2538.790 2.400 ;
-    END
-  END la_oenb[107]
-  PIN la_oenb[108]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2556.170 -4.800 2556.730 2.400 ;
-    END
-  END la_oenb[108]
-  PIN la_oenb[109]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2573.650 -4.800 2574.210 2.400 ;
-    END
-  END la_oenb[109]
-  PIN la_oenb[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 818.290 -4.800 818.850 2.400 ;
-    END
-  END la_oenb[10]
-  PIN la_oenb[110]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2591.590 -4.800 2592.150 2.400 ;
-    END
-  END la_oenb[110]
-  PIN la_oenb[111]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2609.070 -4.800 2609.630 2.400 ;
-    END
-  END la_oenb[111]
-  PIN la_oenb[112]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2627.010 -4.800 2627.570 2.400 ;
-    END
-  END la_oenb[112]
-  PIN la_oenb[113]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2644.950 -4.800 2645.510 2.400 ;
-    END
-  END la_oenb[113]
-  PIN la_oenb[114]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2662.430 -4.800 2662.990 2.400 ;
-    END
-  END la_oenb[114]
-  PIN la_oenb[115]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2680.370 -4.800 2680.930 2.400 ;
-    END
-  END la_oenb[115]
-  PIN la_oenb[116]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2697.850 -4.800 2698.410 2.400 ;
-    END
-  END la_oenb[116]
-  PIN la_oenb[117]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2715.790 -4.800 2716.350 2.400 ;
-    END
-  END la_oenb[117]
-  PIN la_oenb[118]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2733.270 -4.800 2733.830 2.400 ;
-    END
-  END la_oenb[118]
-  PIN la_oenb[119]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2751.210 -4.800 2751.770 2.400 ;
-    END
-  END la_oenb[119]
-  PIN la_oenb[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 835.770 -4.800 836.330 2.400 ;
-    END
-  END la_oenb[11]
-  PIN la_oenb[120]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2768.690 -4.800 2769.250 2.400 ;
-    END
-  END la_oenb[120]
-  PIN la_oenb[121]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2786.630 -4.800 2787.190 2.400 ;
-    END
-  END la_oenb[121]
-  PIN la_oenb[122]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2804.110 -4.800 2804.670 2.400 ;
-    END
-  END la_oenb[122]
-  PIN la_oenb[123]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2822.050 -4.800 2822.610 2.400 ;
-    END
-  END la_oenb[123]
-  PIN la_oenb[124]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2839.990 -4.800 2840.550 2.400 ;
-    END
-  END la_oenb[124]
-  PIN la_oenb[125]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2857.470 -4.800 2858.030 2.400 ;
-    END
-  END la_oenb[125]
-  PIN la_oenb[126]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2875.410 -4.800 2875.970 2.400 ;
-    END
-  END la_oenb[126]
-  PIN la_oenb[127]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2892.890 -4.800 2893.450 2.400 ;
-    END
-  END la_oenb[127]
-  PIN la_oenb[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 853.710 -4.800 854.270 2.400 ;
-    END
-  END la_oenb[12]
-  PIN la_oenb[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 871.190 -4.800 871.750 2.400 ;
-    END
-  END la_oenb[13]
-  PIN la_oenb[14]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 889.130 -4.800 889.690 2.400 ;
-    END
-  END la_oenb[14]
-  PIN la_oenb[15]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 907.070 -4.800 907.630 2.400 ;
-    END
-  END la_oenb[15]
-  PIN la_oenb[16]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 924.550 -4.800 925.110 2.400 ;
-    END
-  END la_oenb[16]
-  PIN la_oenb[17]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 942.490 -4.800 943.050 2.400 ;
-    END
-  END la_oenb[17]
-  PIN la_oenb[18]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 959.970 -4.800 960.530 2.400 ;
-    END
-  END la_oenb[18]
-  PIN la_oenb[19]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 977.910 -4.800 978.470 2.400 ;
-    END
-  END la_oenb[19]
-  PIN la_oenb[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 658.670 -4.800 659.230 2.400 ;
-    END
-  END la_oenb[1]
-  PIN la_oenb[20]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 995.390 -4.800 995.950 2.400 ;
-    END
-  END la_oenb[20]
-  PIN la_oenb[21]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1013.330 -4.800 1013.890 2.400 ;
-    END
-  END la_oenb[21]
-  PIN la_oenb[22]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1030.810 -4.800 1031.370 2.400 ;
-    END
-  END la_oenb[22]
-  PIN la_oenb[23]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1048.750 -4.800 1049.310 2.400 ;
-    END
-  END la_oenb[23]
-  PIN la_oenb[24]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1066.690 -4.800 1067.250 2.400 ;
-    END
-  END la_oenb[24]
-  PIN la_oenb[25]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1084.170 -4.800 1084.730 2.400 ;
-    END
-  END la_oenb[25]
-  PIN la_oenb[26]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1102.110 -4.800 1102.670 2.400 ;
-    END
-  END la_oenb[26]
-  PIN la_oenb[27]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1119.590 -4.800 1120.150 2.400 ;
-    END
-  END la_oenb[27]
-  PIN la_oenb[28]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1137.530 -4.800 1138.090 2.400 ;
-    END
-  END la_oenb[28]
-  PIN la_oenb[29]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1155.010 -4.800 1155.570 2.400 ;
-    END
-  END la_oenb[29]
-  PIN la_oenb[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 676.150 -4.800 676.710 2.400 ;
-    END
-  END la_oenb[2]
-  PIN la_oenb[30]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1172.950 -4.800 1173.510 2.400 ;
-    END
-  END la_oenb[30]
-  PIN la_oenb[31]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1190.430 -4.800 1190.990 2.400 ;
-    END
-  END la_oenb[31]
-  PIN la_oenb[32]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1208.370 -4.800 1208.930 2.400 ;
-    END
-  END la_oenb[32]
-  PIN la_oenb[33]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1225.850 -4.800 1226.410 2.400 ;
-    END
-  END la_oenb[33]
-  PIN la_oenb[34]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1243.790 -4.800 1244.350 2.400 ;
-    END
-  END la_oenb[34]
-  PIN la_oenb[35]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1261.730 -4.800 1262.290 2.400 ;
-    END
-  END la_oenb[35]
-  PIN la_oenb[36]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1279.210 -4.800 1279.770 2.400 ;
-    END
-  END la_oenb[36]
-  PIN la_oenb[37]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1297.150 -4.800 1297.710 2.400 ;
-    END
-  END la_oenb[37]
-  PIN la_oenb[38]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1314.630 -4.800 1315.190 2.400 ;
-    END
-  END la_oenb[38]
-  PIN la_oenb[39]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1332.570 -4.800 1333.130 2.400 ;
-    END
-  END la_oenb[39]
-  PIN la_oenb[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 694.090 -4.800 694.650 2.400 ;
-    END
-  END la_oenb[3]
-  PIN la_oenb[40]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1350.050 -4.800 1350.610 2.400 ;
-    END
-  END la_oenb[40]
-  PIN la_oenb[41]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1367.990 -4.800 1368.550 2.400 ;
-    END
-  END la_oenb[41]
-  PIN la_oenb[42]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1385.470 -4.800 1386.030 2.400 ;
-    END
-  END la_oenb[42]
-  PIN la_oenb[43]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1403.410 -4.800 1403.970 2.400 ;
-    END
-  END la_oenb[43]
-  PIN la_oenb[44]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1421.350 -4.800 1421.910 2.400 ;
-    END
-  END la_oenb[44]
-  PIN la_oenb[45]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1438.830 -4.800 1439.390 2.400 ;
-    END
-  END la_oenb[45]
-  PIN la_oenb[46]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1456.770 -4.800 1457.330 2.400 ;
-    END
-  END la_oenb[46]
-  PIN la_oenb[47]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1474.250 -4.800 1474.810 2.400 ;
-    END
-  END la_oenb[47]
-  PIN la_oenb[48]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1492.190 -4.800 1492.750 2.400 ;
-    END
-  END la_oenb[48]
-  PIN la_oenb[49]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1509.670 -4.800 1510.230 2.400 ;
-    END
-  END la_oenb[49]
-  PIN la_oenb[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 712.030 -4.800 712.590 2.400 ;
-    END
-  END la_oenb[4]
-  PIN la_oenb[50]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1527.610 -4.800 1528.170 2.400 ;
-    END
-  END la_oenb[50]
-  PIN la_oenb[51]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1545.090 -4.800 1545.650 2.400 ;
-    END
-  END la_oenb[51]
-  PIN la_oenb[52]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1563.030 -4.800 1563.590 2.400 ;
-    END
-  END la_oenb[52]
-  PIN la_oenb[53]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1580.970 -4.800 1581.530 2.400 ;
-    END
-  END la_oenb[53]
-  PIN la_oenb[54]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1598.450 -4.800 1599.010 2.400 ;
-    END
-  END la_oenb[54]
-  PIN la_oenb[55]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1616.390 -4.800 1616.950 2.400 ;
-    END
-  END la_oenb[55]
-  PIN la_oenb[56]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1633.870 -4.800 1634.430 2.400 ;
-    END
-  END la_oenb[56]
-  PIN la_oenb[57]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1651.810 -4.800 1652.370 2.400 ;
-    END
-  END la_oenb[57]
-  PIN la_oenb[58]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1669.290 -4.800 1669.850 2.400 ;
-    END
-  END la_oenb[58]
-  PIN la_oenb[59]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1687.230 -4.800 1687.790 2.400 ;
-    END
-  END la_oenb[59]
-  PIN la_oenb[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 729.510 -4.800 730.070 2.400 ;
-    END
-  END la_oenb[5]
-  PIN la_oenb[60]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1704.710 -4.800 1705.270 2.400 ;
-    END
-  END la_oenb[60]
-  PIN la_oenb[61]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1722.650 -4.800 1723.210 2.400 ;
-    END
-  END la_oenb[61]
-  PIN la_oenb[62]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1740.130 -4.800 1740.690 2.400 ;
-    END
-  END la_oenb[62]
-  PIN la_oenb[63]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1758.070 -4.800 1758.630 2.400 ;
-    END
-  END la_oenb[63]
-  PIN la_oenb[64]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1776.010 -4.800 1776.570 2.400 ;
-    END
-  END la_oenb[64]
-  PIN la_oenb[65]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1793.490 -4.800 1794.050 2.400 ;
-    END
-  END la_oenb[65]
-  PIN la_oenb[66]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1811.430 -4.800 1811.990 2.400 ;
-    END
-  END la_oenb[66]
-  PIN la_oenb[67]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1828.910 -4.800 1829.470 2.400 ;
-    END
-  END la_oenb[67]
-  PIN la_oenb[68]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1846.850 -4.800 1847.410 2.400 ;
-    END
-  END la_oenb[68]
-  PIN la_oenb[69]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1864.330 -4.800 1864.890 2.400 ;
-    END
-  END la_oenb[69]
-  PIN la_oenb[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 747.450 -4.800 748.010 2.400 ;
-    END
-  END la_oenb[6]
-  PIN la_oenb[70]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1882.270 -4.800 1882.830 2.400 ;
-    END
-  END la_oenb[70]
-  PIN la_oenb[71]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1899.750 -4.800 1900.310 2.400 ;
-    END
-  END la_oenb[71]
-  PIN la_oenb[72]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1917.690 -4.800 1918.250 2.400 ;
-    END
-  END la_oenb[72]
-  PIN la_oenb[73]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1935.630 -4.800 1936.190 2.400 ;
-    END
-  END la_oenb[73]
-  PIN la_oenb[74]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1953.110 -4.800 1953.670 2.400 ;
-    END
-  END la_oenb[74]
-  PIN la_oenb[75]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1971.050 -4.800 1971.610 2.400 ;
-    END
-  END la_oenb[75]
-  PIN la_oenb[76]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 1988.530 -4.800 1989.090 2.400 ;
-    END
-  END la_oenb[76]
-  PIN la_oenb[77]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2006.470 -4.800 2007.030 2.400 ;
-    END
-  END la_oenb[77]
-  PIN la_oenb[78]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2023.950 -4.800 2024.510 2.400 ;
-    END
-  END la_oenb[78]
-  PIN la_oenb[79]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2041.890 -4.800 2042.450 2.400 ;
-    END
-  END la_oenb[79]
-  PIN la_oenb[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 764.930 -4.800 765.490 2.400 ;
-    END
-  END la_oenb[7]
-  PIN la_oenb[80]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2059.370 -4.800 2059.930 2.400 ;
-    END
-  END la_oenb[80]
-  PIN la_oenb[81]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2077.310 -4.800 2077.870 2.400 ;
-    END
-  END la_oenb[81]
-  PIN la_oenb[82]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2094.790 -4.800 2095.350 2.400 ;
-    END
-  END la_oenb[82]
-  PIN la_oenb[83]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2112.730 -4.800 2113.290 2.400 ;
-    END
-  END la_oenb[83]
-  PIN la_oenb[84]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2130.670 -4.800 2131.230 2.400 ;
-    END
-  END la_oenb[84]
-  PIN la_oenb[85]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2148.150 -4.800 2148.710 2.400 ;
-    END
-  END la_oenb[85]
-  PIN la_oenb[86]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2166.090 -4.800 2166.650 2.400 ;
-    END
-  END la_oenb[86]
-  PIN la_oenb[87]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2183.570 -4.800 2184.130 2.400 ;
-    END
-  END la_oenb[87]
-  PIN la_oenb[88]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2201.510 -4.800 2202.070 2.400 ;
-    END
-  END la_oenb[88]
-  PIN la_oenb[89]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2218.990 -4.800 2219.550 2.400 ;
-    END
-  END la_oenb[89]
-  PIN la_oenb[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 782.870 -4.800 783.430 2.400 ;
-    END
-  END la_oenb[8]
-  PIN la_oenb[90]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2236.930 -4.800 2237.490 2.400 ;
-    END
-  END la_oenb[90]
-  PIN la_oenb[91]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2254.410 -4.800 2254.970 2.400 ;
-    END
-  END la_oenb[91]
-  PIN la_oenb[92]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2272.350 -4.800 2272.910 2.400 ;
-    END
-  END la_oenb[92]
-  PIN la_oenb[93]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2290.290 -4.800 2290.850 2.400 ;
-    END
-  END la_oenb[93]
-  PIN la_oenb[94]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2307.770 -4.800 2308.330 2.400 ;
-    END
-  END la_oenb[94]
-  PIN la_oenb[95]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2325.710 -4.800 2326.270 2.400 ;
-    END
-  END la_oenb[95]
-  PIN la_oenb[96]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2343.190 -4.800 2343.750 2.400 ;
-    END
-  END la_oenb[96]
-  PIN la_oenb[97]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2361.130 -4.800 2361.690 2.400 ;
-    END
-  END la_oenb[97]
-  PIN la_oenb[98]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2378.610 -4.800 2379.170 2.400 ;
-    END
-  END la_oenb[98]
-  PIN la_oenb[99]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2396.550 -4.800 2397.110 2.400 ;
-    END
-  END la_oenb[99]
-  PIN la_oenb[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 800.350 -4.800 800.910 2.400 ;
-    END
-  END la_oenb[9]
-  PIN user_clock2
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2898.870 -4.800 2899.430 2.400 ;
-    END
-  END user_clock2
-  PIN user_irq[0]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2904.850 -4.800 2905.410 2.400 ;
-    END
-  END user_irq[0]
-  PIN user_irq[1]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2910.830 -4.800 2911.390 2.400 ;
-    END
-  END user_irq[1]
-  PIN user_irq[2]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2916.810 -4.800 2917.370 2.400 ;
-    END
-  END user_irq[2]
-  PIN vccd1
-    DIRECTION INPUT ;
-    USE POWER ;
-    PORT
-      LAYER met5 ;
-        RECT -10.030 -4.670 2929.650 -1.570 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 14.330 2934.450 17.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 194.330 2934.450 197.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 374.330 2934.450 377.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 554.330 2934.450 557.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 734.330 2934.450 737.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 914.330 2934.450 917.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1094.330 2934.450 1097.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1274.330 2934.450 1277.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1454.330 2934.450 1457.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1634.330 2934.450 1637.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1814.330 2934.450 1817.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1994.330 2934.450 1997.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 2174.330 2934.450 2177.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 2354.330 2934.450 2357.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 2534.330 2934.450 2537.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 2714.330 2934.450 2717.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 2894.330 2934.450 2897.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3074.330 2934.450 3077.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3254.330 2934.450 3257.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3434.330 2934.450 3437.430 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -10.030 3521.250 2929.650 3524.350 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1268.970 -9.470 1272.070 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1448.970 -9.470 1452.070 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1628.970 -9.470 1632.070 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1808.970 -9.470 1812.070 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1988.970 -9.470 1992.070 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT -10.030 -4.670 -6.930 3524.350 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2926.550 -4.670 2929.650 3524.350 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 8.970 -9.470 12.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 188.970 -9.470 192.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 368.970 -9.470 372.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 548.970 -9.470 552.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 728.970 -9.470 732.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 908.970 -9.470 912.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1088.970 -9.470 1092.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1268.970 2300.000 1272.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1448.970 2300.000 1452.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1628.970 2300.000 1632.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1808.970 2300.000 1812.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1988.970 2300.000 1992.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2168.970 -9.470 2172.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2348.970 -9.470 2352.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2528.970 -9.470 2532.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2708.970 -9.470 2712.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2888.970 -9.470 2892.070 3529.150 ;
-    END
-  END vccd1
-  PIN vccd2
-    DIRECTION INPUT ;
-    USE POWER ;
-    PORT
-      LAYER met5 ;
-        RECT -19.630 -14.270 2939.250 -11.170 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 32.930 2944.050 36.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 212.930 2944.050 216.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 392.930 2944.050 396.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 572.930 2944.050 576.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 752.930 2944.050 756.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 932.930 2944.050 936.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1112.930 2944.050 1116.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1292.930 2944.050 1296.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1472.930 2944.050 1476.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1652.930 2944.050 1656.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1832.930 2944.050 1836.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2012.930 2944.050 2016.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2192.930 2944.050 2196.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2372.930 2944.050 2376.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2552.930 2944.050 2556.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2732.930 2944.050 2736.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2912.930 2944.050 2916.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3092.930 2944.050 3096.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3272.930 2944.050 3276.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3452.930 2944.050 3456.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -19.630 3530.850 2939.250 3533.950 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1287.570 -19.070 1290.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1467.570 -19.070 1470.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1647.570 -19.070 1650.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1827.570 -19.070 1830.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2007.570 -19.070 2010.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT -19.630 -14.270 -16.530 3533.950 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2936.150 -14.270 2939.250 3533.950 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 27.570 -19.070 30.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 207.570 -19.070 210.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 387.570 -19.070 390.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 567.570 -19.070 570.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 747.570 -19.070 750.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 927.570 -19.070 930.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1107.570 -19.070 1110.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1287.570 2300.000 1290.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1467.570 2300.000 1470.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1647.570 2300.000 1650.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1827.570 2300.000 1830.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2007.570 2300.000 2010.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2187.570 -19.070 2190.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2367.570 -19.070 2370.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2547.570 -19.070 2550.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2727.570 -19.070 2730.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2907.570 -19.070 2910.670 3538.750 ;
-    END
-  END vccd2
-  PIN vdda1
-    DIRECTION INPUT ;
-    USE POWER ;
-    PORT
-      LAYER met5 ;
-        RECT -29.230 -23.870 2948.850 -20.770 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 51.530 2953.650 54.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 231.530 2953.650 234.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 411.530 2953.650 414.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 591.530 2953.650 594.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 771.530 2953.650 774.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 951.530 2953.650 954.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 1131.530 2953.650 1134.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 1311.530 2953.650 1314.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 1491.530 2953.650 1494.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 1671.530 2953.650 1674.630 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -34.030 1851.530 2953.650 1854.630 ;
-    END
-    PORT
-      LAYER met5 ;
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-    END
-    PORT
-      LAYER met4 ;
-        RECT 818.970 -9.470 822.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 998.970 -9.470 1002.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1178.970 2300.000 1182.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1358.970 2300.000 1362.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1538.970 2300.000 1542.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1718.970 2300.000 1722.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1898.970 2300.000 1902.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2078.970 2300.000 2082.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2258.970 -9.470 2262.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2438.970 -9.470 2442.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2618.970 -9.470 2622.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2798.970 -9.470 2802.070 3529.150 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2931.350 -9.470 2934.450 3529.150 ;
-    END
-  END vssd1
-  PIN vssd2
-    DIRECTION INPUT ;
-    USE GROUND ;
-    PORT
-      LAYER met5 ;
-        RECT -24.430 -19.070 2944.050 -15.970 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 122.930 2944.050 126.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 302.930 2944.050 306.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 482.930 2944.050 486.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 662.930 2944.050 666.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 842.930 2944.050 846.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1022.930 2944.050 1026.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1202.930 2944.050 1206.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1382.930 2944.050 1386.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1562.930 2944.050 1566.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1742.930 2944.050 1746.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 1922.930 2944.050 1926.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2102.930 2944.050 2106.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2282.930 2944.050 2286.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2462.930 2944.050 2466.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2642.930 2944.050 2646.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 2822.930 2944.050 2826.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3002.930 2944.050 3006.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3182.930 2944.050 3186.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3362.930 2944.050 3366.030 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -24.430 3535.650 2944.050 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1197.570 -19.070 1200.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1377.570 -19.070 1380.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1557.570 -19.070 1560.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1737.570 -19.070 1740.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1917.570 -19.070 1920.670 1680.000 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT -24.430 -19.070 -21.330 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 117.570 -19.070 120.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 297.570 -19.070 300.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 477.570 -19.070 480.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 657.570 -19.070 660.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 837.570 -19.070 840.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1017.570 -19.070 1020.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1197.570 2300.000 1200.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1377.570 2300.000 1380.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1557.570 2300.000 1560.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1737.570 2300.000 1740.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 1917.570 2300.000 1920.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2097.570 -19.070 2100.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2277.570 -19.070 2280.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2457.570 -19.070 2460.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2637.570 -19.070 2640.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2817.570 -19.070 2820.670 3538.750 ;
-    END
-    PORT
-      LAYER met4 ;
-        RECT 2940.950 -19.070 2944.050 3538.750 ;
-    END
-  END vssd2
-  PIN wb_clk_i
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 2.710 -4.800 3.270 2.400 ;
-    END
-  END wb_clk_i
-  PIN wb_rst_i
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 8.230 -4.800 8.790 2.400 ;
-    END
-  END wb_rst_i
-  PIN wbs_ack_o
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 14.210 -4.800 14.770 2.400 ;
-    END
-  END wbs_ack_o
-  PIN wbs_adr_i[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 38.130 -4.800 38.690 2.400 ;
-    END
-  END wbs_adr_i[0]
-  PIN wbs_adr_i[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 239.150 -4.800 239.710 2.400 ;
-    END
-  END wbs_adr_i[10]
-  PIN wbs_adr_i[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 256.630 -4.800 257.190 2.400 ;
-    END
-  END wbs_adr_i[11]
-  PIN wbs_adr_i[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 274.570 -4.800 275.130 2.400 ;
-    END
-  END wbs_adr_i[12]
-  PIN wbs_adr_i[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 292.050 -4.800 292.610 2.400 ;
-    END
-  END wbs_adr_i[13]
-  PIN wbs_adr_i[14]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 309.990 -4.800 310.550 2.400 ;
-    END
-  END wbs_adr_i[14]
-  PIN wbs_adr_i[15]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 327.470 -4.800 328.030 2.400 ;
-    END
-  END wbs_adr_i[15]
-  PIN wbs_adr_i[16]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 345.410 -4.800 345.970 2.400 ;
-    END
-  END wbs_adr_i[16]
-  PIN wbs_adr_i[17]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 362.890 -4.800 363.450 2.400 ;
-    END
-  END wbs_adr_i[17]
-  PIN wbs_adr_i[18]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 380.830 -4.800 381.390 2.400 ;
-    END
-  END wbs_adr_i[18]
-  PIN wbs_adr_i[19]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 398.310 -4.800 398.870 2.400 ;
-    END
-  END wbs_adr_i[19]
-  PIN wbs_adr_i[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 61.590 -4.800 62.150 2.400 ;
-    END
-  END wbs_adr_i[1]
-  PIN wbs_adr_i[20]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 416.250 -4.800 416.810 2.400 ;
-    END
-  END wbs_adr_i[20]
-  PIN wbs_adr_i[21]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 434.190 -4.800 434.750 2.400 ;
-    END
-  END wbs_adr_i[21]
-  PIN wbs_adr_i[22]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 451.670 -4.800 452.230 2.400 ;
-    END
-  END wbs_adr_i[22]
-  PIN wbs_adr_i[23]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 469.610 -4.800 470.170 2.400 ;
-    END
-  END wbs_adr_i[23]
-  PIN wbs_adr_i[24]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 487.090 -4.800 487.650 2.400 ;
-    END
-  END wbs_adr_i[24]
-  PIN wbs_adr_i[25]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 505.030 -4.800 505.590 2.400 ;
-    END
-  END wbs_adr_i[25]
-  PIN wbs_adr_i[26]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 522.510 -4.800 523.070 2.400 ;
-    END
-  END wbs_adr_i[26]
-  PIN wbs_adr_i[27]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 540.450 -4.800 541.010 2.400 ;
-    END
-  END wbs_adr_i[27]
-  PIN wbs_adr_i[28]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 557.930 -4.800 558.490 2.400 ;
-    END
-  END wbs_adr_i[28]
-  PIN wbs_adr_i[29]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 575.870 -4.800 576.430 2.400 ;
-    END
-  END wbs_adr_i[29]
-  PIN wbs_adr_i[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 85.050 -4.800 85.610 2.400 ;
-    END
-  END wbs_adr_i[2]
-  PIN wbs_adr_i[30]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 593.810 -4.800 594.370 2.400 ;
-    END
-  END wbs_adr_i[30]
-  PIN wbs_adr_i[31]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 611.290 -4.800 611.850 2.400 ;
-    END
-  END wbs_adr_i[31]
-  PIN wbs_adr_i[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 108.970 -4.800 109.530 2.400 ;
-    END
-  END wbs_adr_i[3]
-  PIN wbs_adr_i[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 132.430 -4.800 132.990 2.400 ;
-    END
-  END wbs_adr_i[4]
-  PIN wbs_adr_i[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 150.370 -4.800 150.930 2.400 ;
-    END
-  END wbs_adr_i[5]
-  PIN wbs_adr_i[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 167.850 -4.800 168.410 2.400 ;
-    END
-  END wbs_adr_i[6]
-  PIN wbs_adr_i[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 185.790 -4.800 186.350 2.400 ;
-    END
-  END wbs_adr_i[7]
-  PIN wbs_adr_i[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 203.270 -4.800 203.830 2.400 ;
-    END
-  END wbs_adr_i[8]
-  PIN wbs_adr_i[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 221.210 -4.800 221.770 2.400 ;
-    END
-  END wbs_adr_i[9]
-  PIN wbs_cyc_i
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 20.190 -4.800 20.750 2.400 ;
-    END
-  END wbs_cyc_i
-  PIN wbs_dat_i[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 43.650 -4.800 44.210 2.400 ;
-    END
-  END wbs_dat_i[0]
-  PIN wbs_dat_i[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 244.670 -4.800 245.230 2.400 ;
-    END
-  END wbs_dat_i[10]
-  PIN wbs_dat_i[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 262.610 -4.800 263.170 2.400 ;
-    END
-  END wbs_dat_i[11]
-  PIN wbs_dat_i[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 280.090 -4.800 280.650 2.400 ;
-    END
-  END wbs_dat_i[12]
-  PIN wbs_dat_i[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 298.030 -4.800 298.590 2.400 ;
-    END
-  END wbs_dat_i[13]
-  PIN wbs_dat_i[14]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 315.970 -4.800 316.530 2.400 ;
-    END
-  END wbs_dat_i[14]
-  PIN wbs_dat_i[15]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 333.450 -4.800 334.010 2.400 ;
-    END
-  END wbs_dat_i[15]
-  PIN wbs_dat_i[16]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 351.390 -4.800 351.950 2.400 ;
-    END
-  END wbs_dat_i[16]
-  PIN wbs_dat_i[17]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 368.870 -4.800 369.430 2.400 ;
-    END
-  END wbs_dat_i[17]
-  PIN wbs_dat_i[18]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 386.810 -4.800 387.370 2.400 ;
-    END
-  END wbs_dat_i[18]
-  PIN wbs_dat_i[19]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 404.290 -4.800 404.850 2.400 ;
-    END
-  END wbs_dat_i[19]
-  PIN wbs_dat_i[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 67.570 -4.800 68.130 2.400 ;
-    END
-  END wbs_dat_i[1]
-  PIN wbs_dat_i[20]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 422.230 -4.800 422.790 2.400 ;
-    END
-  END wbs_dat_i[20]
-  PIN wbs_dat_i[21]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 439.710 -4.800 440.270 2.400 ;
-    END
-  END wbs_dat_i[21]
-  PIN wbs_dat_i[22]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 457.650 -4.800 458.210 2.400 ;
-    END
-  END wbs_dat_i[22]
-  PIN wbs_dat_i[23]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 475.590 -4.800 476.150 2.400 ;
-    END
-  END wbs_dat_i[23]
-  PIN wbs_dat_i[24]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 493.070 -4.800 493.630 2.400 ;
-    END
-  END wbs_dat_i[24]
-  PIN wbs_dat_i[25]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 511.010 -4.800 511.570 2.400 ;
-    END
-  END wbs_dat_i[25]
-  PIN wbs_dat_i[26]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 528.490 -4.800 529.050 2.400 ;
-    END
-  END wbs_dat_i[26]
-  PIN wbs_dat_i[27]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 546.430 -4.800 546.990 2.400 ;
-    END
-  END wbs_dat_i[27]
-  PIN wbs_dat_i[28]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 563.910 -4.800 564.470 2.400 ;
-    END
-  END wbs_dat_i[28]
-  PIN wbs_dat_i[29]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 581.850 -4.800 582.410 2.400 ;
-    END
-  END wbs_dat_i[29]
-  PIN wbs_dat_i[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 91.030 -4.800 91.590 2.400 ;
-    END
-  END wbs_dat_i[2]
-  PIN wbs_dat_i[30]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 599.330 -4.800 599.890 2.400 ;
-    END
-  END wbs_dat_i[30]
-  PIN wbs_dat_i[31]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 617.270 -4.800 617.830 2.400 ;
-    END
-  END wbs_dat_i[31]
-  PIN wbs_dat_i[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 114.950 -4.800 115.510 2.400 ;
-    END
-  END wbs_dat_i[3]
-  PIN wbs_dat_i[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 138.410 -4.800 138.970 2.400 ;
-    END
-  END wbs_dat_i[4]
-  PIN wbs_dat_i[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 156.350 -4.800 156.910 2.400 ;
-    END
-  END wbs_dat_i[5]
-  PIN wbs_dat_i[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 173.830 -4.800 174.390 2.400 ;
-    END
-  END wbs_dat_i[6]
-  PIN wbs_dat_i[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 191.770 -4.800 192.330 2.400 ;
-    END
-  END wbs_dat_i[7]
-  PIN wbs_dat_i[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 209.250 -4.800 209.810 2.400 ;
-    END
-  END wbs_dat_i[8]
-  PIN wbs_dat_i[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 227.190 -4.800 227.750 2.400 ;
-    END
-  END wbs_dat_i[9]
-  PIN wbs_dat_o[0]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 49.630 -4.800 50.190 2.400 ;
-    END
-  END wbs_dat_o[0]
-  PIN wbs_dat_o[10]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 250.650 -4.800 251.210 2.400 ;
-    END
-  END wbs_dat_o[10]
-  PIN wbs_dat_o[11]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 268.590 -4.800 269.150 2.400 ;
-    END
-  END wbs_dat_o[11]
-  PIN wbs_dat_o[12]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 286.070 -4.800 286.630 2.400 ;
-    END
-  END wbs_dat_o[12]
-  PIN wbs_dat_o[13]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 304.010 -4.800 304.570 2.400 ;
-    END
-  END wbs_dat_o[13]
-  PIN wbs_dat_o[14]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 321.490 -4.800 322.050 2.400 ;
-    END
-  END wbs_dat_o[14]
-  PIN wbs_dat_o[15]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 339.430 -4.800 339.990 2.400 ;
-    END
-  END wbs_dat_o[15]
-  PIN wbs_dat_o[16]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 357.370 -4.800 357.930 2.400 ;
-    END
-  END wbs_dat_o[16]
-  PIN wbs_dat_o[17]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 374.850 -4.800 375.410 2.400 ;
-    END
-  END wbs_dat_o[17]
-  PIN wbs_dat_o[18]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 392.790 -4.800 393.350 2.400 ;
-    END
-  END wbs_dat_o[18]
-  PIN wbs_dat_o[19]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 410.270 -4.800 410.830 2.400 ;
-    END
-  END wbs_dat_o[19]
-  PIN wbs_dat_o[1]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 73.550 -4.800 74.110 2.400 ;
-    END
-  END wbs_dat_o[1]
-  PIN wbs_dat_o[20]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 428.210 -4.800 428.770 2.400 ;
-    END
-  END wbs_dat_o[20]
-  PIN wbs_dat_o[21]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 445.690 -4.800 446.250 2.400 ;
-    END
-  END wbs_dat_o[21]
-  PIN wbs_dat_o[22]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 463.630 -4.800 464.190 2.400 ;
-    END
-  END wbs_dat_o[22]
-  PIN wbs_dat_o[23]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 481.110 -4.800 481.670 2.400 ;
-    END
-  END wbs_dat_o[23]
-  PIN wbs_dat_o[24]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 499.050 -4.800 499.610 2.400 ;
-    END
-  END wbs_dat_o[24]
-  PIN wbs_dat_o[25]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 516.530 -4.800 517.090 2.400 ;
-    END
-  END wbs_dat_o[25]
-  PIN wbs_dat_o[26]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 534.470 -4.800 535.030 2.400 ;
-    END
-  END wbs_dat_o[26]
-  PIN wbs_dat_o[27]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 552.410 -4.800 552.970 2.400 ;
-    END
-  END wbs_dat_o[27]
-  PIN wbs_dat_o[28]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 569.890 -4.800 570.450 2.400 ;
-    END
-  END wbs_dat_o[28]
-  PIN wbs_dat_o[29]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 587.830 -4.800 588.390 2.400 ;
-    END
-  END wbs_dat_o[29]
-  PIN wbs_dat_o[2]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 97.010 -4.800 97.570 2.400 ;
-    END
-  END wbs_dat_o[2]
-  PIN wbs_dat_o[30]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 605.310 -4.800 605.870 2.400 ;
-    END
-  END wbs_dat_o[30]
-  PIN wbs_dat_o[31]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 623.250 -4.800 623.810 2.400 ;
-    END
-  END wbs_dat_o[31]
-  PIN wbs_dat_o[3]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 120.930 -4.800 121.490 2.400 ;
-    END
-  END wbs_dat_o[3]
-  PIN wbs_dat_o[4]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 144.390 -4.800 144.950 2.400 ;
-    END
-  END wbs_dat_o[4]
-  PIN wbs_dat_o[5]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 161.870 -4.800 162.430 2.400 ;
-    END
-  END wbs_dat_o[5]
-  PIN wbs_dat_o[6]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 179.810 -4.800 180.370 2.400 ;
-    END
-  END wbs_dat_o[6]
-  PIN wbs_dat_o[7]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 197.750 -4.800 198.310 2.400 ;
-    END
-  END wbs_dat_o[7]
-  PIN wbs_dat_o[8]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 215.230 -4.800 215.790 2.400 ;
-    END
-  END wbs_dat_o[8]
-  PIN wbs_dat_o[9]
-    DIRECTION OUTPUT TRISTATE ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 233.170 -4.800 233.730 2.400 ;
-    END
-  END wbs_dat_o[9]
-  PIN wbs_sel_i[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 55.610 -4.800 56.170 2.400 ;
-    END
-  END wbs_sel_i[0]
-  PIN wbs_sel_i[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 79.530 -4.800 80.090 2.400 ;
-    END
-  END wbs_sel_i[1]
-  PIN wbs_sel_i[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 102.990 -4.800 103.550 2.400 ;
-    END
-  END wbs_sel_i[2]
-  PIN wbs_sel_i[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 126.450 -4.800 127.010 2.400 ;
-    END
-  END wbs_sel_i[3]
-  PIN wbs_stb_i
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 26.170 -4.800 26.730 2.400 ;
-    END
-  END wbs_stb_i
-  PIN wbs_we_i
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT
-      LAYER met2 ;
-        RECT 32.150 -4.800 32.710 2.400 ;
-    END
-  END wbs_we_i
-  OBS
-      LAYER li1 ;
-        RECT 1180.520 1700.795 2069.240 2277.605 ;
-      LAYER met1 ;
-        RECT 8.350 14.320 2917.250 3505.020 ;
-      LAYER met2 ;
-        RECT 2.850 3517.320 40.150 3518.050 ;
-        RECT 41.270 3517.320 121.110 3518.050 ;
-        RECT 122.230 3517.320 202.070 3518.050 ;
-        RECT 203.190 3517.320 283.490 3518.050 ;
-        RECT 284.610 3517.320 364.450 3518.050 ;
-        RECT 365.570 3517.320 445.410 3518.050 ;
-        RECT 446.530 3517.320 526.830 3518.050 ;
-        RECT 527.950 3517.320 607.790 3518.050 ;
-        RECT 608.910 3517.320 688.750 3518.050 ;
-        RECT 689.870 3517.320 770.170 3518.050 ;
-        RECT 771.290 3517.320 851.130 3518.050 ;
-        RECT 852.250 3517.320 932.090 3518.050 ;
-        RECT 933.210 3517.320 1013.510 3518.050 ;
-        RECT 1014.630 3517.320 1094.470 3518.050 ;
-        RECT 1095.590 3517.320 1175.430 3518.050 ;
-        RECT 1176.550 3517.320 1256.850 3518.050 ;
-        RECT 1257.970 3517.320 1337.810 3518.050 ;
-        RECT 1338.930 3517.320 1418.770 3518.050 ;
-        RECT 1419.890 3517.320 1500.190 3518.050 ;
-        RECT 1501.310 3517.320 1581.150 3518.050 ;
-        RECT 1582.270 3517.320 1662.110 3518.050 ;
-        RECT 1663.230 3517.320 1743.530 3518.050 ;
-        RECT 1744.650 3517.320 1824.490 3518.050 ;
-        RECT 1825.610 3517.320 1905.450 3518.050 ;
-        RECT 1906.570 3517.320 1986.870 3518.050 ;
-        RECT 1987.990 3517.320 2067.830 3518.050 ;
-        RECT 2068.950 3517.320 2148.790 3518.050 ;
-        RECT 2149.910 3517.320 2230.210 3518.050 ;
-        RECT 2231.330 3517.320 2311.170 3518.050 ;
-        RECT 2312.290 3517.320 2392.130 3518.050 ;
-        RECT 2393.250 3517.320 2473.550 3518.050 ;
-        RECT 2474.670 3517.320 2554.510 3518.050 ;
-        RECT 2555.630 3517.320 2635.470 3518.050 ;
-        RECT 2636.590 3517.320 2716.890 3518.050 ;
-        RECT 2718.010 3517.320 2797.850 3518.050 ;
-        RECT 2798.970 3517.320 2878.810 3518.050 ;
-        RECT 2879.930 3517.320 2917.220 3518.050 ;
-        RECT 2.850 2.680 2917.220 3517.320 ;
-        RECT 3.550 1.630 7.950 2.680 ;
-        RECT 9.070 1.630 13.930 2.680 ;
-        RECT 15.050 1.630 19.910 2.680 ;
-        RECT 21.030 1.630 25.890 2.680 ;
-        RECT 27.010 1.630 31.870 2.680 ;
-        RECT 32.990 1.630 37.850 2.680 ;
-        RECT 38.970 1.630 43.370 2.680 ;
-        RECT 44.490 1.630 49.350 2.680 ;
-        RECT 50.470 1.630 55.330 2.680 ;
-        RECT 56.450 1.630 61.310 2.680 ;
-        RECT 62.430 1.630 67.290 2.680 ;
-        RECT 68.410 1.630 73.270 2.680 ;
-        RECT 74.390 1.630 79.250 2.680 ;
-        RECT 80.370 1.630 84.770 2.680 ;
-        RECT 85.890 1.630 90.750 2.680 ;
-        RECT 91.870 1.630 96.730 2.680 ;
-        RECT 97.850 1.630 102.710 2.680 ;
-        RECT 103.830 1.630 108.690 2.680 ;
-        RECT 109.810 1.630 114.670 2.680 ;
-        RECT 115.790 1.630 120.650 2.680 ;
-        RECT 121.770 1.630 126.170 2.680 ;
-        RECT 127.290 1.630 132.150 2.680 ;
-        RECT 133.270 1.630 138.130 2.680 ;
-        RECT 139.250 1.630 144.110 2.680 ;
-        RECT 145.230 1.630 150.090 2.680 ;
-        RECT 151.210 1.630 156.070 2.680 ;
-        RECT 157.190 1.630 161.590 2.680 ;
-        RECT 162.710 1.630 167.570 2.680 ;
-        RECT 168.690 1.630 173.550 2.680 ;
-        RECT 174.670 1.630 179.530 2.680 ;
-        RECT 180.650 1.630 185.510 2.680 ;
-        RECT 186.630 1.630 191.490 2.680 ;
-        RECT 192.610 1.630 197.470 2.680 ;
-        RECT 198.590 1.630 202.990 2.680 ;
-        RECT 204.110 1.630 208.970 2.680 ;
-        RECT 210.090 1.630 214.950 2.680 ;
-        RECT 216.070 1.630 220.930 2.680 ;
-        RECT 222.050 1.630 226.910 2.680 ;
-        RECT 228.030 1.630 232.890 2.680 ;
-        RECT 234.010 1.630 238.870 2.680 ;
-        RECT 239.990 1.630 244.390 2.680 ;
-        RECT 245.510 1.630 250.370 2.680 ;
-        RECT 251.490 1.630 256.350 2.680 ;
-        RECT 257.470 1.630 262.330 2.680 ;
-        RECT 263.450 1.630 268.310 2.680 ;
-        RECT 269.430 1.630 274.290 2.680 ;
-        RECT 275.410 1.630 279.810 2.680 ;
-        RECT 280.930 1.630 285.790 2.680 ;
-        RECT 286.910 1.630 291.770 2.680 ;
-        RECT 292.890 1.630 297.750 2.680 ;
-        RECT 298.870 1.630 303.730 2.680 ;
-        RECT 304.850 1.630 309.710 2.680 ;
-        RECT 310.830 1.630 315.690 2.680 ;
-        RECT 316.810 1.630 321.210 2.680 ;
-        RECT 322.330 1.630 327.190 2.680 ;
-        RECT 328.310 1.630 333.170 2.680 ;
-        RECT 334.290 1.630 339.150 2.680 ;
-        RECT 340.270 1.630 345.130 2.680 ;
-        RECT 346.250 1.630 351.110 2.680 ;
-        RECT 352.230 1.630 357.090 2.680 ;
-        RECT 358.210 1.630 362.610 2.680 ;
-        RECT 363.730 1.630 368.590 2.680 ;
-        RECT 369.710 1.630 374.570 2.680 ;
-        RECT 375.690 1.630 380.550 2.680 ;
-        RECT 381.670 1.630 386.530 2.680 ;
-        RECT 387.650 1.630 392.510 2.680 ;
-        RECT 393.630 1.630 398.030 2.680 ;
-        RECT 399.150 1.630 404.010 2.680 ;
-        RECT 405.130 1.630 409.990 2.680 ;
-        RECT 411.110 1.630 415.970 2.680 ;
-        RECT 417.090 1.630 421.950 2.680 ;
-        RECT 423.070 1.630 427.930 2.680 ;
-        RECT 429.050 1.630 433.910 2.680 ;
-        RECT 435.030 1.630 439.430 2.680 ;
-        RECT 440.550 1.630 445.410 2.680 ;
-        RECT 446.530 1.630 451.390 2.680 ;
-        RECT 452.510 1.630 457.370 2.680 ;
-        RECT 458.490 1.630 463.350 2.680 ;
-        RECT 464.470 1.630 469.330 2.680 ;
-        RECT 470.450 1.630 475.310 2.680 ;
-        RECT 476.430 1.630 480.830 2.680 ;
-        RECT 481.950 1.630 486.810 2.680 ;
-        RECT 487.930 1.630 492.790 2.680 ;
-        RECT 493.910 1.630 498.770 2.680 ;
-        RECT 499.890 1.630 504.750 2.680 ;
-        RECT 505.870 1.630 510.730 2.680 ;
-        RECT 511.850 1.630 516.250 2.680 ;
-        RECT 517.370 1.630 522.230 2.680 ;
-        RECT 523.350 1.630 528.210 2.680 ;
-        RECT 529.330 1.630 534.190 2.680 ;
-        RECT 535.310 1.630 540.170 2.680 ;
-        RECT 541.290 1.630 546.150 2.680 ;
-        RECT 547.270 1.630 552.130 2.680 ;
-        RECT 553.250 1.630 557.650 2.680 ;
-        RECT 558.770 1.630 563.630 2.680 ;
-        RECT 564.750 1.630 569.610 2.680 ;
-        RECT 570.730 1.630 575.590 2.680 ;
-        RECT 576.710 1.630 581.570 2.680 ;
-        RECT 582.690 1.630 587.550 2.680 ;
-        RECT 588.670 1.630 593.530 2.680 ;
-        RECT 594.650 1.630 599.050 2.680 ;
-        RECT 600.170 1.630 605.030 2.680 ;
-        RECT 606.150 1.630 611.010 2.680 ;
-        RECT 612.130 1.630 616.990 2.680 ;
-        RECT 618.110 1.630 622.970 2.680 ;
-        RECT 624.090 1.630 628.950 2.680 ;
-        RECT 630.070 1.630 634.470 2.680 ;
-        RECT 635.590 1.630 640.450 2.680 ;
-        RECT 641.570 1.630 646.430 2.680 ;
-        RECT 647.550 1.630 652.410 2.680 ;
-        RECT 653.530 1.630 658.390 2.680 ;
-        RECT 659.510 1.630 664.370 2.680 ;
-        RECT 665.490 1.630 670.350 2.680 ;
-        RECT 671.470 1.630 675.870 2.680 ;
-        RECT 676.990 1.630 681.850 2.680 ;
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-        RECT 724.370 1.630 729.230 2.680 ;
-        RECT 730.350 1.630 735.210 2.680 ;
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-        RECT 748.290 1.630 752.690 2.680 ;
-        RECT 753.810 1.630 758.670 2.680 ;
-        RECT 759.790 1.630 764.650 2.680 ;
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-        RECT 771.750 1.630 776.610 2.680 ;
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-        RECT 783.710 1.630 788.570 2.680 ;
-        RECT 789.690 1.630 794.090 2.680 ;
-        RECT 795.210 1.630 800.070 2.680 ;
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-        RECT 1114.450 1.630 1119.310 2.680 ;
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-  END
-END user_project_wrapper
-END LIBRARY
-
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index e89b608..16018c6 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1645741056
+timestamp 1646996710
 << obsli1 >>
 rect 236104 340159 413848 455521
 << obsm1 >>
@@ -3872,7 +3872,7 @@
 string LEFclass BLOCK
 string LEFview TRUE
 string GDS_END 10274330
-string GDS_FILE /home/marwan/mpw-5c/caravel_example/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.magic.gds
+string GDS_FILE /home/nguyendao/SKY130/gg-mpw5-2022/open_eFPGA/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.magic.gds
 string GDS_START 8544082
 << end >>
 
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index d653ce6..cf733c1 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -16,8 +16,6 @@
 set script_dir [file dirname [file normalize [info script]]]
 source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl
 source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl
-#source $script_dir/fixed_wrapper_cfgs.tcl
-#source $script_dir/default_wrapper_cfgs.tcl
 
 set ::env(DESIGN_NAME) user_project_wrapper
 
@@ -83,52 +81,19 @@
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(VERILOG_FILES) [glob $script_dir/../../verilog/rtl/defines.v $script_dir/../../../verilog/rtl/*.v ]
-#set ::env(VERILOG_FILES) "\
-#	$script_dir/../../verilog/rtl/defines.v \
-#	$script_dir/../../verilog/rtl/user_project_wrapper.v"
 
 ## Internal Macros
-
 ### Macro Placement
 set ::env(MACRO_PLACEMENT_CFG) "$script_dir/../../../openlane/user_project_wrapper/macros/placements/macro_placement.cfg"
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) [glob $script_dir/../../../verilog/rtl/BB/*.v]
 
-#set ::env(VERILOG_FILES_BLACKBOX) "\
-#	$script_dir/../../verilog/rtl/defines.v \
-#	$script_dir/../../verilog/rtl/eFPGA_top.v"
-
 set ::env(EXTRA_LEFS) [glob $script_dir/../../../openlane/user_project_wrapper/macros/lef/*.lef]
-#set ::env(EXTRA_LEFS) "\
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/BRAM.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/cus_tg_mux41_buf.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/DSP.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/E_CPU_IO_bot.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/E_CPU_IO.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/flexbex_ibex_core.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/ibex_core.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/ibex_top.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/LUT4AB.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/N_term_DSP.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/N_term_RAM_IO.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/N_term_single2.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/N_term_single.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/RAM_IO.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/RegFile.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/S_term_DSP.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/S_term_RAM_IO.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/S_term_single2.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/S_term_single.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/W_CPU_IO_bot.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/W_CPU_IO.lef \
-#			$script_dir/../../../openlane/user_project_wrapper/macros/lef/W_IO.lef "
 
 set ::env(EXTRA_GDS_FILES) [glob $script_dir/../../../openlane/user_project_wrapper/macros/gds/*.gds]
 
 ### Macro PDN Connections
-#set ::env(FP_PDN_MACRO_HOOKS) "\
-#	inst_eFPGA_top vccd1 vssd1"
 set ::env(FP_PDN_MACRO_HOOKS) "\
         inst_eFPGA_top.Inst_eFPGA.Tile_X0Y1_W_IO vccd1 vssd1 \
         inst_eFPGA_top.Inst_eFPGA.Tile_X0Y2_W_IO vccd1 vssd1 \
@@ -269,29 +234,3 @@
         inst_eFPGA_top.Inst_BlockRAM_1 vccd1 vssd1 \
         inst_eFPGA_top.Inst_BlockRAM_0 vccd1 vssd1 "
 
-
-
-## The following is because there are no std cells in the example wrapper project.
-
-#set ::env(SYNTH_TOP_LEVEL) 1
-#set ::env(PL_RANDOM_GLB_PLACEMENT) 1
-#
-#set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
-#set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
-#set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
-#set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
-#
-#set ::env(FP_PDN_ENABLE_RAILS) 0
-#
-##set ::env(DIODE_INSERTION_STRATEGY) 0
-#set ::env(FILL_INSERTION) 0
-#set ::env(TAP_DECAP_INSERTION) 0
-#set ::env(CLOCK_TREE_SYNTH) 0
-#
-#set ::env(MAGIC_DRC_USE_GDS) 0
-#set ::env(ROUTING_CORES) 12
-#set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
-#set ::env(VDD_PIN) "vccd1"
-#set ::env(GND_PIN) "vssd1"
-#set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
-#
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
deleted file mode 100644
index bf1f324..0000000
--- a/openlane/user_project_wrapper/macro.cfg
+++ /dev/null
@@ -1 +0,0 @@
-inst_eFPGA_top 75 150 R0
diff --git a/openlane/user_project_wrapper/macros/macros_innovus_mpw4.csh b/openlane/user_project_wrapper/macros/macros_innovus_mpw4.csh
deleted file mode 100755
index 0a7523a..0000000
--- a/openlane/user_project_wrapper/macros/macros_innovus_mpw4.csh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/csh
-cp ~/SKY130/gg-mpw4-2021/Innovus/common/gds/*.gds ./gds
-cp ~/SKY130/gg-mpw4-2021/Innovus/common/lef/*.lef ./lef
-cp ~/SKY130/gg-mpw4-2021/Innovus/common/lib/*.lib ./lib
diff --git a/openlane/user_project_wrapper/macros/old_macro.csh b/openlane/user_project_wrapper/macros/old_macro.csh
deleted file mode 100755
index 85ba144..0000000
--- a/openlane/user_project_wrapper/macros/old_macro.csh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/csh
-cp ~/SKY130/eFPGA_v2/Innovus/CLB2/OUTPUTs/LUT4AB.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/DSP/OUTPUTs/DSP.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/RegFile/OUTPUTs/RegFile.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/W_IO/OUTPUTs/W_IO.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/RAM_IO/OUTPUTs/RAM_IO.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_single/OUTPUTs/N_term_single.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_single2/OUTPUTs/N_term_single2.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_RAM_IO/OUTPUTs/N_term_RAM_IO.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_RAM_IO/OUTPUTs/S_term_RAM_IO.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_single2/OUTPUTs/S_term_single2.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_single/OUTPUTs/S_term_single.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_DSP/OUTPUTs/S_term_DSP.lef ./lef
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_DSP/OUTPUTs/N_term_DSP.lef ./lef
-cp ~//SKY130/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.lef ./lef
-
-cp ~/SKY130/eFPGA_v2/Innovus/CLB2/OUTPUTs/LUT4AB.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/DSP/OUTPUTs/DSP.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/RegFile/OUTPUTs/RegFile.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/W_IO/OUTPUTs/W_IO.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/RAM_IO/OUTPUTs/RAM_IO.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_single/OUTPUTs/N_term_single.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_single2/OUTPUTs/N_term_single2.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_RAM_IO/OUTPUTs/N_term_RAM_IO.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_RAM_IO/OUTPUTs/S_term_RAM_IO.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_single2/OUTPUTs/S_term_single2.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_single/OUTPUTs/S_term_single.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_DSP/OUTPUTs/S_term_DSP.gds ./gds
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_DSP/OUTPUTs/N_term_DSP.gds ./gds
-cp ~//SKY130/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.gds ./gds
-
-cp ~/SKY130/eFPGA_v2/Innovus/CLB2/OUTPUTs/LUT4AB.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/DSP/OUTPUTs/DSP.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/RegFile/OUTPUTs/RegFile.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/W_IO/OUTPUTs/W_IO.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/RAM_IO/OUTPUTs/RAM_IO.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_single/OUTPUTs/N_term_single.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_single2/OUTPUTs/N_term_single2.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_RAM_IO/OUTPUTs/N_term_RAM_IO.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_RAM_IO/OUTPUTs/S_term_RAM_IO.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_single2/OUTPUTs/S_term_single2.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_single/OUTPUTs/S_term_single.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/S_term_DSP/OUTPUTs/S_term_DSP.lib ./lib
-cp ~/SKY130/eFPGA_v2/Innovus/N_term_DSP/OUTPUTs/N_term_DSP.lib ./lib
diff --git a/openlane/user_project_wrapper/macros/placements/Old_v2/fabric_params.py b/openlane/user_project_wrapper/macros/placements/Old_v2/fabric_params.py
deleted file mode 100644
index 81aa253..0000000
--- a/openlane/user_project_wrapper/macros/placements/Old_v2/fabric_params.py
+++ /dev/null
@@ -1,21 +0,0 @@
-col = 12
-row = 12
-regfile_col = [4]
-DSP_col = [8]
-LUT4AB_size = [210, 220]
-DSP_size = [210, 445]
-RegFile_size = [240, 220]
-W_IO_size = [70, 220]
-RAM_IO_size = [100, 220]
-N_term_single_size = [210, 30]
-N_term_DSP_size = [210, 30]
-N_term_single2_size = [240, 30]
-N_term_RAM_IO_size = [100, 30]
-S_term_single_size = [210, 30]
-S_term_DSP_size = [210, 30]
-S_term_single2_size = [240, 30]
-S_term_RAM_IO_size = [100, 30]
-Space = 5
-Offset_WL = 100
-Offset_WR = 20
-Offset_H = 40
diff --git a/openlane/user_project_wrapper/macros/placements/Old_v2/fabric_params.pyc b/openlane/user_project_wrapper/macros/placements/Old_v2/fabric_params.pyc
deleted file mode 100644
index 37a450f..0000000
--- a/openlane/user_project_wrapper/macros/placements/Old_v2/fabric_params.pyc
+++ /dev/null
Binary files differ
diff --git a/openlane/user_project_wrapper/macros/placements/Old_v2/gen_placement.py b/openlane/user_project_wrapper/macros/placements/Old_v2/gen_placement.py
deleted file mode 100644
index a93d82e..0000000
--- a/openlane/user_project_wrapper/macros/placements/Old_v2/gen_placement.py
+++ /dev/null
@@ -1,129 +0,0 @@
-import re
-from array import *
-import fileinput
-import sys, getopt
-import csv
-import fabric_params
-
-COL = fabric_params.col
-ROW = fabric_params.row
-REGFILE = fabric_params.regfile_col
-DSP = fabric_params.DSP_col
-
-LUT4AB_size = fabric_params.LUT4AB_size 
-DSP_size = fabric_params.DSP_size
-RegFile_size = fabric_params.RegFile_size
-W_IO_size = fabric_params.W_IO_size 
-RAM_IO_size = fabric_params.RAM_IO_size 
-N_term_single_size = fabric_params.N_term_single_size 
-N_term_single2_size = fabric_params.N_term_single2_size
-N_term_RAM_IO_size = fabric_params.N_term_RAM_IO_size 
-S_term_single_size = fabric_params.S_term_single_size 
-S_term_single2_size = fabric_params.S_term_single2_size
-S_term_RAM_IO_size = fabric_params.S_term_RAM_IO_size 
-Space = fabric_params.Space
-offset_WL = fabric_params.Offset_WL
-offset_WR = fabric_params.Offset_WR
-offset_H = fabric_params.Offset_H
-
-LUT4AB_W = LUT4AB_size[0]
-LUT4AB_H = LUT4AB_size[1]
-DSP_W = DSP_size[0]
-DSP_H = DSP_size[1]
-RegFile_W = RegFile_size[0]
-RegFile_H = RegFile_size[1]
-N_term_H = N_term_single_size[1]
-S_term_H = S_term_single_size[1]
-W_IO_W = W_IO_size[0]
-W_IO_H = W_IO_size[1]
-RAM_IO_W = RAM_IO_size[0]
-RAM_IO_H = RAM_IO_size[1]
-
-#offset = 10
-x_co = 0
-y_co = 0
-reg_count = 0
-placement = ""
-Tile_H = W_IO_H
-if REGFILE[0] == 0:
-   No_RegFile_col = 0
-else:
-   No_RegFile_col = len(REGFILE)
-if DSP[0] == 0:
-   No_DSP_col = 0
-else:
-   No_DSP_col = len(DSP)
-No_LUT4AB_col = COL - No_RegFile_col - No_DSP_col
-
-core_H = ROW*Tile_H + (ROW-1)*Space
-core_W = No_LUT4AB_col*LUT4AB_W + No_DSP_col*DSP_W + No_RegFile_col*RegFile_W + (COL-1)*Space 
-fabric_H = N_term_H + core_H + S_term_H + 2*Space + 2*offset_H
-fabric_W = W_IO_W + core_W + RAM_IO_W + 2*Space + offset_WL + offset_WR
-
-print ('column = ', COL)
-print ('row = ', ROW)
-print ('LUT4AB col = ', No_LUT4AB_col, 'DSP_col = ',No_DSP_col,'regfile col = ',No_RegFile_col)
-print ('fabric_H = ', core_H)
-print ('fabric_W = ', core_W)
-print ('AREA (XY) = {} x {}'.format(fabric_W, fabric_H))
-
-#try:
-#    with open("sdc_template.sdc", 'r') as file :
-#        placement = file.read()
-#except IOError:
-#    print("sdc_template.sdc is not accesstable")
-
-for x in range(COL+2):
-    if x==0:
-         x_co = offset_WL
-    else:
-         x_co = offset_WL + W_IO_W + (x-reg_count-1)*LUT4AB_W + reg_count*RegFile_W + x*Space
-         #print('x - reg_col -1 =',x-reg_count-1,'reg_count = ',reg_count)
-    if REGFILE.count(x) == 1:
-         reg_count += 1
-         #print('reg col =',x,'reg_count = ',reg_count)
-
-    for y in range(ROW+2):
-         Tile = 'Inst_eFPGA.Tile_X'+str(x)+'Y'+str(y)
-         if y==0: 
-             y_co = fabric_H - N_term_H - offset_H
-         elif y==ROW+1:
-             y_co = fabric_H - N_term_H - core_H - 2*Space - S_term_H - offset_H
-         else:
-             y_co = fabric_H - N_term_H - y*Tile_H - y*Space - offset_H
-
-         if x == 0 and y != 0 and y  <= ROW:
-             placement += str(Tile)+'_W_IO '+str(x_co)+' '+str(y_co)+' N\n'
-         if y == 0 and x != 0 and x <= COL:
-             if REGFILE.count(x) == 1:
-                 placement += str(Tile)+'_N_term_single2 '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) == 1:
-                 placement += str(Tile)+'_N_term_DSP '+str(x_co)+' '+str(y_co)+' N\n'
-             else:
-                 placement += str(Tile)+'_N_term_single '+str(x_co)+' '+str(y_co)+' N\n'
-         if x >= 1 and y >= 1 and x <= COL and y <= ROW: 
-             if REGFILE.count(x) == 1:
-                 placement += str(Tile)+'_RegFile '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) == 1 and y%2 == 0:
-                 Tile = 'Inst_eFPGA.Tile_X'+str(x)+'Y'+str(y-1)+'_X'+str(x)+'Y'+str(y)
-                 placement += str(Tile)+'_DSP_tile '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) != 1:
-                 placement += str(Tile)+'_LUT4AB '+str(x_co)+' '+str(y_co)+' N\n'
-         if y == ROW+1 and x != 0 and x <= COL:
-             if REGFILE.count(x) == 1:
-                 placement += str(Tile)+'_S_term_single2 '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) == 1:
-                 placement += str(Tile)+'_S_term_DSP '+str(x_co)+' '+str(y_co)+' N\n'
-             else:
-                 placement += str(Tile)+'_S_term_single '+str(x_co)+' '+str(y_co)+' N\n'
-         if x == COL+1 and y == 0:
-             placement += str(Tile)+'_N_term_RAM_IO '+str(x_co)+' '+str(y_co)+' N\n'
-         if x == COL+1 and y >= 1 and y <= ROW: 
-             placement += str(Tile)+'_RAM_IO '+str(x_co)+' '+str(y_co)+' N\n'
-         if x == COL+1 and y == ROW+1: 
-             placement += str(Tile)+'_S_term_RAM_IO '+str(x_co)+' '+str(y_co)+' N\n'
-     
-if placement:
-   with open("./macro_placement.cfg", 'w') as file:
-        file.write(placement) 
-
diff --git a/openlane/user_project_wrapper/macros/placements/Old_v2/inst_list.txt b/openlane/user_project_wrapper/macros/placements/Old_v2/inst_list.txt
deleted file mode 100644
index 9481f97..0000000
--- a/openlane/user_project_wrapper/macros/placements/Old_v2/inst_list.txt
+++ /dev/null
@@ -1,287 +0,0 @@
-Tile_X1Y0_N_term_single
-Tile_X2Y0_N_term_single
-Tile_X3Y0_N_term_single
-Tile_X4Y0_N_term_single2
-Tile_X5Y0_N_term_single
-Tile_X6Y0_N_term_single
-Tile_X7Y0_N_term_single
-Tile_X8Y0_N_term_single2
-Tile_X9Y0_N_term_single
-Tile_X10Y0_N_term_single
-Tile_X11Y0_N_term_single
-Tile_X12Y0_N_term_single2
-Tile_X13Y0_N_term_single
-Tile_X14Y0_N_term_single
-Tile_X15Y0_N_term_single
-Tile_X16Y0_N_term_RAM_IO
-Tile_X0Y1_W_IO
-Tile_X1Y1_LUT4AB
-Tile_X2Y1_LUT4AB
-Tile_X3Y1_LUT4AB
-Tile_X4Y1_RegFile
-Tile_X5Y1_LUT4AB
-Tile_X6Y1_LUT4AB
-Tile_X7Y1_LUT4AB
-Tile_X8Y1_RegFile
-Tile_X9Y1_LUT4AB
-Tile_X10Y1_LUT4AB
-Tile_X11Y1_LUT4AB
-Tile_X12Y1_RegFile
-Tile_X13Y1_LUT4AB
-Tile_X14Y1_LUT4AB
-Tile_X15Y1_LUT4AB
-Tile_X16Y1_RAM_IO
-Tile_X0Y2_W_IO
-Tile_X1Y2_LUT4AB
-Tile_X2Y2_LUT4AB
-Tile_X3Y2_LUT4AB
-Tile_X4Y2_RegFile
-Tile_X5Y2_LUT4AB
-Tile_X6Y2_LUT4AB
-Tile_X7Y2_LUT4AB
-Tile_X8Y2_RegFile
-Tile_X9Y2_LUT4AB
-Tile_X10Y2_LUT4AB
-Tile_X11Y2_LUT4AB
-Tile_X12Y2_RegFile
-Tile_X13Y2_LUT4AB
-Tile_X14Y2_LUT4AB
-Tile_X15Y2_LUT4AB
-Tile_X16Y2_RAM_IO
-Tile_X0Y3_W_IO
-Tile_X1Y3_LUT4AB
-Tile_X2Y3_LUT4AB
-Tile_X3Y3_LUT4AB
-Tile_X4Y3_RegFile
-Tile_X5Y3_LUT4AB
-Tile_X6Y3_LUT4AB
-Tile_X7Y3_LUT4AB
-Tile_X8Y3_RegFile
-Tile_X9Y3_LUT4AB
-Tile_X10Y3_LUT4AB
-Tile_X11Y3_LUT4AB
-Tile_X12Y3_RegFile
-Tile_X13Y3_LUT4AB
-Tile_X14Y3_LUT4AB
-Tile_X15Y3_LUT4AB
-Tile_X16Y3_RAM_IO
-Tile_X0Y4_W_IO
-Tile_X1Y4_LUT4AB
-Tile_X2Y4_LUT4AB
-Tile_X3Y4_LUT4AB
-Tile_X4Y4_RegFile
-Tile_X5Y4_LUT4AB
-Tile_X6Y4_LUT4AB
-Tile_X7Y4_LUT4AB
-Tile_X8Y4_RegFile
-Tile_X9Y4_LUT4AB
-Tile_X10Y4_LUT4AB
-Tile_X11Y4_LUT4AB
-Tile_X12Y4_RegFile
-Tile_X13Y4_LUT4AB
-Tile_X14Y4_LUT4AB
-Tile_X15Y4_LUT4AB
-Tile_X16Y4_RAM_IO
-Tile_X0Y5_W_IO
-Tile_X1Y5_LUT4AB
-Tile_X2Y5_LUT4AB
-Tile_X3Y5_LUT4AB
-Tile_X4Y5_RegFile
-Tile_X5Y5_LUT4AB
-Tile_X6Y5_LUT4AB
-Tile_X7Y5_LUT4AB
-Tile_X8Y5_RegFile
-Tile_X9Y5_LUT4AB
-Tile_X10Y5_LUT4AB
-Tile_X11Y5_LUT4AB
-Tile_X12Y5_RegFile
-Tile_X13Y5_LUT4AB
-Tile_X14Y5_LUT4AB
-Tile_X15Y5_LUT4AB
-Tile_X16Y5_RAM_IO
-Tile_X0Y6_W_IO
-Tile_X1Y6_LUT4AB
-Tile_X2Y6_LUT4AB
-Tile_X3Y6_LUT4AB
-Tile_X4Y6_RegFile
-Tile_X5Y6_LUT4AB
-Tile_X6Y6_LUT4AB
-Tile_X7Y6_LUT4AB
-Tile_X8Y6_RegFile
-Tile_X9Y6_LUT4AB
-Tile_X10Y6_LUT4AB
-Tile_X11Y6_LUT4AB
-Tile_X12Y6_RegFile
-Tile_X13Y6_LUT4AB
-Tile_X14Y6_LUT4AB
-Tile_X15Y6_LUT4AB
-Tile_X16Y6_RAM_IO
-Tile_X0Y7_W_IO
-Tile_X1Y7_LUT4AB
-Tile_X2Y7_LUT4AB
-Tile_X3Y7_LUT4AB
-Tile_X4Y7_RegFile
-Tile_X5Y7_LUT4AB
-Tile_X6Y7_LUT4AB
-Tile_X7Y7_LUT4AB
-Tile_X8Y7_RegFile
-Tile_X9Y7_LUT4AB
-Tile_X10Y7_LUT4AB
-Tile_X11Y7_LUT4AB
-Tile_X12Y7_RegFile
-Tile_X13Y7_LUT4AB
-Tile_X14Y7_LUT4AB
-Tile_X15Y7_LUT4AB
-Tile_X16Y7_RAM_IO
-Tile_X0Y8_W_IO
-Tile_X1Y8_LUT4AB
-Tile_X2Y8_LUT4AB
-Tile_X3Y8_LUT4AB
-Tile_X4Y8_RegFile
-Tile_X5Y8_LUT4AB
-Tile_X6Y8_LUT4AB
-Tile_X7Y8_LUT4AB
-Tile_X8Y8_RegFile
-Tile_X9Y8_LUT4AB
-Tile_X10Y8_LUT4AB
-Tile_X11Y8_LUT4AB
-Tile_X12Y8_RegFile
-Tile_X13Y8_LUT4AB
-Tile_X14Y8_LUT4AB
-Tile_X15Y8_LUT4AB
-Tile_X16Y8_RAM_IO
-Tile_X0Y9_W_IO
-Tile_X1Y9_LUT4AB
-Tile_X2Y9_LUT4AB
-Tile_X3Y9_LUT4AB
-Tile_X4Y9_RegFile
-Tile_X5Y9_LUT4AB
-Tile_X6Y9_LUT4AB
-Tile_X7Y9_LUT4AB
-Tile_X8Y9_RegFile
-Tile_X9Y9_LUT4AB
-Tile_X10Y9_LUT4AB
-Tile_X11Y9_LUT4AB
-Tile_X12Y9_RegFile
-Tile_X13Y9_LUT4AB
-Tile_X14Y9_LUT4AB
-Tile_X15Y9_LUT4AB
-Tile_X16Y9_RAM_IO
-Tile_X0Y10_W_IO
-Tile_X1Y10_LUT4AB
-Tile_X2Y10_LUT4AB
-Tile_X3Y10_LUT4AB
-Tile_X4Y10_RegFile
-Tile_X5Y10_LUT4AB
-Tile_X6Y10_LUT4AB
-Tile_X7Y10_LUT4AB
-Tile_X8Y10_RegFile
-Tile_X9Y10_LUT4AB
-Tile_X10Y10_LUT4AB
-Tile_X11Y10_LUT4AB
-Tile_X12Y10_RegFile
-Tile_X13Y10_LUT4AB
-Tile_X14Y10_LUT4AB
-Tile_X15Y10_LUT4AB
-Tile_X16Y10_RAM_IO
-Tile_X0Y11_W_IO
-Tile_X1Y11_LUT4AB
-Tile_X2Y11_LUT4AB
-Tile_X3Y11_LUT4AB
-Tile_X4Y11_RegFile
-Tile_X5Y11_LUT4AB
-Tile_X6Y11_LUT4AB
-Tile_X7Y11_LUT4AB
-Tile_X8Y11_RegFile
-Tile_X9Y11_LUT4AB
-Tile_X10Y11_LUT4AB
-Tile_X11Y11_LUT4AB
-Tile_X12Y11_RegFile
-Tile_X13Y11_LUT4AB
-Tile_X14Y11_LUT4AB
-Tile_X15Y11_LUT4AB
-Tile_X16Y11_RAM_IO
-Tile_X0Y12_W_IO
-Tile_X1Y12_LUT4AB
-Tile_X2Y12_LUT4AB
-Tile_X3Y12_LUT4AB
-Tile_X4Y12_RegFile
-Tile_X5Y12_LUT4AB
-Tile_X6Y12_LUT4AB
-Tile_X7Y12_LUT4AB
-Tile_X8Y12_RegFile
-Tile_X9Y12_LUT4AB
-Tile_X10Y12_LUT4AB
-Tile_X11Y12_LUT4AB
-Tile_X12Y12_RegFile
-Tile_X13Y12_LUT4AB
-Tile_X14Y12_LUT4AB
-Tile_X15Y12_LUT4AB
-Tile_X16Y12_RAM_IO
-Tile_X0Y13_W_IO
-Tile_X1Y13_LUT4AB
-Tile_X2Y13_LUT4AB
-Tile_X3Y13_LUT4AB
-Tile_X4Y13_RegFile
-Tile_X5Y13_LUT4AB
-Tile_X6Y13_LUT4AB
-Tile_X7Y13_LUT4AB
-Tile_X8Y13_RegFile
-Tile_X9Y13_LUT4AB
-Tile_X10Y13_LUT4AB
-Tile_X11Y13_LUT4AB
-Tile_X12Y13_RegFile
-Tile_X13Y13_LUT4AB
-Tile_X14Y13_LUT4AB
-Tile_X15Y13_LUT4AB
-Tile_X16Y13_RAM_IO
-Tile_X0Y14_W_IO
-Tile_X1Y14_LUT4AB
-Tile_X2Y14_LUT4AB
-Tile_X3Y14_LUT4AB
-Tile_X4Y14_RegFile
-Tile_X5Y14_LUT4AB
-Tile_X6Y14_LUT4AB
-Tile_X7Y14_LUT4AB
-Tile_X8Y14_RegFile
-Tile_X9Y14_LUT4AB
-Tile_X10Y14_LUT4AB
-Tile_X11Y14_LUT4AB
-Tile_X12Y14_RegFile
-Tile_X13Y14_LUT4AB
-Tile_X14Y14_LUT4AB
-Tile_X15Y14_LUT4AB
-Tile_X16Y14_RAM_IO
-Tile_X0Y15_W_IO
-Tile_X1Y15_LUT4AB
-Tile_X2Y15_LUT4AB
-Tile_X3Y15_LUT4AB
-Tile_X4Y15_RegFile
-Tile_X5Y15_LUT4AB
-Tile_X6Y15_LUT4AB
-Tile_X7Y15_LUT4AB
-Tile_X8Y15_RegFile
-Tile_X9Y15_LUT4AB
-Tile_X10Y15_LUT4AB
-Tile_X11Y15_LUT4AB
-Tile_X12Y15_RegFile
-Tile_X13Y15_LUT4AB
-Tile_X14Y15_LUT4AB
-Tile_X15Y15_LUT4AB
-Tile_X16Y15_RAM_IO
-Tile_X1Y16_S_term_single
-Tile_X2Y16_S_term_single
-Tile_X3Y16_S_term_single
-Tile_X4Y16_S_term_single2
-Tile_X5Y16_S_term_single
-Tile_X6Y16_S_term_single
-Tile_X7Y16_S_term_single
-Tile_X8Y16_S_term_single2
-Tile_X9Y16_S_term_single
-Tile_X10Y16_S_term_single
-Tile_X11Y16_S_term_single
-Tile_X12Y16_S_term_single2
-Tile_X13Y16_S_term_single
-Tile_X14Y16_S_term_single
-Tile_X15Y16_S_term_single
-Tile_X16Y16_S_term_RAM_IO
diff --git a/openlane/user_project_wrapper/macros/placements/Old_v2/macro_placement.cfg b/openlane/user_project_wrapper/macros/placements/Old_v2/macro_placement.cfg
deleted file mode 100644
index 7d91af0..0000000
--- a/openlane/user_project_wrapper/macros/placements/Old_v2/macro_placement.cfg
+++ /dev/null
@@ -1,192 +0,0 @@
-Inst_eFPGA.Tile_X0Y1_W_IO 100 2550 N
-Inst_eFPGA.Tile_X0Y2_W_IO 100 2325 N
-Inst_eFPGA.Tile_X0Y3_W_IO 100 2100 N
-Inst_eFPGA.Tile_X0Y4_W_IO 100 1875 N
-Inst_eFPGA.Tile_X0Y5_W_IO 100 1650 N
-Inst_eFPGA.Tile_X0Y6_W_IO 100 1425 N
-Inst_eFPGA.Tile_X0Y7_W_IO 100 1200 N
-Inst_eFPGA.Tile_X0Y8_W_IO 100 975 N
-Inst_eFPGA.Tile_X0Y9_W_IO 100 750 N
-Inst_eFPGA.Tile_X0Y10_W_IO 100 525 N
-Inst_eFPGA.Tile_X0Y11_W_IO 100 300 N
-Inst_eFPGA.Tile_X0Y12_W_IO 100 75 N
-Inst_eFPGA.Tile_X1Y0_N_term_single 175 2775 N
-Inst_eFPGA.Tile_X1Y1_LUT4AB 175 2550 N
-Inst_eFPGA.Tile_X1Y2_LUT4AB 175 2325 N
-Inst_eFPGA.Tile_X1Y3_LUT4AB 175 2100 N
-Inst_eFPGA.Tile_X1Y4_LUT4AB 175 1875 N
-Inst_eFPGA.Tile_X1Y5_LUT4AB 175 1650 N
-Inst_eFPGA.Tile_X1Y6_LUT4AB 175 1425 N
-Inst_eFPGA.Tile_X1Y7_LUT4AB 175 1200 N
-Inst_eFPGA.Tile_X1Y8_LUT4AB 175 975 N
-Inst_eFPGA.Tile_X1Y9_LUT4AB 175 750 N
-Inst_eFPGA.Tile_X1Y10_LUT4AB 175 525 N
-Inst_eFPGA.Tile_X1Y11_LUT4AB 175 300 N
-Inst_eFPGA.Tile_X1Y12_LUT4AB 175 75 N
-Inst_eFPGA.Tile_X1Y13_S_term_single 175 40 N
-Inst_eFPGA.Tile_X2Y0_N_term_single 390 2775 N
-Inst_eFPGA.Tile_X2Y1_LUT4AB 390 2550 N
-Inst_eFPGA.Tile_X2Y2_LUT4AB 390 2325 N
-Inst_eFPGA.Tile_X2Y3_LUT4AB 390 2100 N
-Inst_eFPGA.Tile_X2Y4_LUT4AB 390 1875 N
-Inst_eFPGA.Tile_X2Y5_LUT4AB 390 1650 N
-Inst_eFPGA.Tile_X2Y6_LUT4AB 390 1425 N
-Inst_eFPGA.Tile_X2Y7_LUT4AB 390 1200 N
-Inst_eFPGA.Tile_X2Y8_LUT4AB 390 975 N
-Inst_eFPGA.Tile_X2Y9_LUT4AB 390 750 N
-Inst_eFPGA.Tile_X2Y10_LUT4AB 390 525 N
-Inst_eFPGA.Tile_X2Y11_LUT4AB 390 300 N
-Inst_eFPGA.Tile_X2Y12_LUT4AB 390 75 N
-Inst_eFPGA.Tile_X2Y13_S_term_single 390 40 N
-Inst_eFPGA.Tile_X3Y0_N_term_single 605 2775 N
-Inst_eFPGA.Tile_X3Y1_LUT4AB 605 2550 N
-Inst_eFPGA.Tile_X3Y2_LUT4AB 605 2325 N
-Inst_eFPGA.Tile_X3Y3_LUT4AB 605 2100 N
-Inst_eFPGA.Tile_X3Y4_LUT4AB 605 1875 N
-Inst_eFPGA.Tile_X3Y5_LUT4AB 605 1650 N
-Inst_eFPGA.Tile_X3Y6_LUT4AB 605 1425 N
-Inst_eFPGA.Tile_X3Y7_LUT4AB 605 1200 N
-Inst_eFPGA.Tile_X3Y8_LUT4AB 605 975 N
-Inst_eFPGA.Tile_X3Y9_LUT4AB 605 750 N
-Inst_eFPGA.Tile_X3Y10_LUT4AB 605 525 N
-Inst_eFPGA.Tile_X3Y11_LUT4AB 605 300 N
-Inst_eFPGA.Tile_X3Y12_LUT4AB 605 75 N
-Inst_eFPGA.Tile_X3Y13_S_term_single 605 40 N
-Inst_eFPGA.Tile_X4Y0_N_term_single2 820 2775 N
-Inst_eFPGA.Tile_X4Y1_RegFile 820 2550 N
-Inst_eFPGA.Tile_X4Y2_RegFile 820 2325 N
-Inst_eFPGA.Tile_X4Y3_RegFile 820 2100 N
-Inst_eFPGA.Tile_X4Y4_RegFile 820 1875 N
-Inst_eFPGA.Tile_X4Y5_RegFile 820 1650 N
-Inst_eFPGA.Tile_X4Y6_RegFile 820 1425 N
-Inst_eFPGA.Tile_X4Y7_RegFile 820 1200 N
-Inst_eFPGA.Tile_X4Y8_RegFile 820 975 N
-Inst_eFPGA.Tile_X4Y9_RegFile 820 750 N
-Inst_eFPGA.Tile_X4Y10_RegFile 820 525 N
-Inst_eFPGA.Tile_X4Y11_RegFile 820 300 N
-Inst_eFPGA.Tile_X4Y12_RegFile 820 75 N
-Inst_eFPGA.Tile_X4Y13_S_term_single2 820 40 N
-Inst_eFPGA.Tile_X5Y0_N_term_single 1065 2775 N
-Inst_eFPGA.Tile_X5Y1_LUT4AB 1065 2550 N
-Inst_eFPGA.Tile_X5Y2_LUT4AB 1065 2325 N
-Inst_eFPGA.Tile_X5Y3_LUT4AB 1065 2100 N
-Inst_eFPGA.Tile_X5Y4_LUT4AB 1065 1875 N
-Inst_eFPGA.Tile_X5Y5_LUT4AB 1065 1650 N
-Inst_eFPGA.Tile_X5Y6_LUT4AB 1065 1425 N
-Inst_eFPGA.Tile_X5Y7_LUT4AB 1065 1200 N
-Inst_eFPGA.Tile_X5Y8_LUT4AB 1065 975 N
-Inst_eFPGA.Tile_X5Y9_LUT4AB 1065 750 N
-Inst_eFPGA.Tile_X5Y10_LUT4AB 1065 525 N
-Inst_eFPGA.Tile_X5Y11_LUT4AB 1065 300 N
-Inst_eFPGA.Tile_X5Y12_LUT4AB 1065 75 N
-Inst_eFPGA.Tile_X5Y13_S_term_single 1065 40 N
-Inst_eFPGA.Tile_X6Y0_N_term_single 1280 2775 N
-Inst_eFPGA.Tile_X6Y1_LUT4AB 1280 2550 N
-Inst_eFPGA.Tile_X6Y2_LUT4AB 1280 2325 N
-Inst_eFPGA.Tile_X6Y3_LUT4AB 1280 2100 N
-Inst_eFPGA.Tile_X6Y4_LUT4AB 1280 1875 N
-Inst_eFPGA.Tile_X6Y5_LUT4AB 1280 1650 N
-Inst_eFPGA.Tile_X6Y6_LUT4AB 1280 1425 N
-Inst_eFPGA.Tile_X6Y7_LUT4AB 1280 1200 N
-Inst_eFPGA.Tile_X6Y8_LUT4AB 1280 975 N
-Inst_eFPGA.Tile_X6Y9_LUT4AB 1280 750 N
-Inst_eFPGA.Tile_X6Y10_LUT4AB 1280 525 N
-Inst_eFPGA.Tile_X6Y11_LUT4AB 1280 300 N
-Inst_eFPGA.Tile_X6Y12_LUT4AB 1280 75 N
-Inst_eFPGA.Tile_X6Y13_S_term_single 1280 40 N
-Inst_eFPGA.Tile_X7Y0_N_term_single 1495 2775 N
-Inst_eFPGA.Tile_X7Y1_LUT4AB 1495 2550 N
-Inst_eFPGA.Tile_X7Y2_LUT4AB 1495 2325 N
-Inst_eFPGA.Tile_X7Y3_LUT4AB 1495 2100 N
-Inst_eFPGA.Tile_X7Y4_LUT4AB 1495 1875 N
-Inst_eFPGA.Tile_X7Y5_LUT4AB 1495 1650 N
-Inst_eFPGA.Tile_X7Y6_LUT4AB 1495 1425 N
-Inst_eFPGA.Tile_X7Y7_LUT4AB 1495 1200 N
-Inst_eFPGA.Tile_X7Y8_LUT4AB 1495 975 N
-Inst_eFPGA.Tile_X7Y9_LUT4AB 1495 750 N
-Inst_eFPGA.Tile_X7Y10_LUT4AB 1495 525 N
-Inst_eFPGA.Tile_X7Y11_LUT4AB 1495 300 N
-Inst_eFPGA.Tile_X7Y12_LUT4AB 1495 75 N
-Inst_eFPGA.Tile_X7Y13_S_term_single 1495 40 N
-Inst_eFPGA.Tile_X8Y0_N_term_DSP 1710 2775 N
-Inst_eFPGA.Tile_X8Y1_X8Y2_DSP_tile 1710 2325 N
-Inst_eFPGA.Tile_X8Y3_X8Y4_DSP_tile 1710 1875 N
-Inst_eFPGA.Tile_X8Y5_X8Y6_DSP_tile 1710 1425 N
-Inst_eFPGA.Tile_X8Y7_X8Y8_DSP_tile 1710 975 N
-Inst_eFPGA.Tile_X8Y9_X8Y10_DSP_tile 1710 525 N
-Inst_eFPGA.Tile_X8Y11_X8Y12_DSP_tile 1710 75 N
-Inst_eFPGA.Tile_X8Y13_S_term_DSP 1710 40 N
-Inst_eFPGA.Tile_X9Y0_N_term_single 1925 2775 N
-Inst_eFPGA.Tile_X9Y1_LUT4AB 1925 2550 N
-Inst_eFPGA.Tile_X9Y2_LUT4AB 1925 2325 N
-Inst_eFPGA.Tile_X9Y3_LUT4AB 1925 2100 N
-Inst_eFPGA.Tile_X9Y4_LUT4AB 1925 1875 N
-Inst_eFPGA.Tile_X9Y5_LUT4AB 1925 1650 N
-Inst_eFPGA.Tile_X9Y6_LUT4AB 1925 1425 N
-Inst_eFPGA.Tile_X9Y7_LUT4AB 1925 1200 N
-Inst_eFPGA.Tile_X9Y8_LUT4AB 1925 975 N
-Inst_eFPGA.Tile_X9Y9_LUT4AB 1925 750 N
-Inst_eFPGA.Tile_X9Y10_LUT4AB 1925 525 N
-Inst_eFPGA.Tile_X9Y11_LUT4AB 1925 300 N
-Inst_eFPGA.Tile_X9Y12_LUT4AB 1925 75 N
-Inst_eFPGA.Tile_X9Y13_S_term_single 1925 40 N
-Inst_eFPGA.Tile_X10Y0_N_term_single 2140 2775 N
-Inst_eFPGA.Tile_X10Y1_LUT4AB 2140 2550 N
-Inst_eFPGA.Tile_X10Y2_LUT4AB 2140 2325 N
-Inst_eFPGA.Tile_X10Y3_LUT4AB 2140 2100 N
-Inst_eFPGA.Tile_X10Y4_LUT4AB 2140 1875 N
-Inst_eFPGA.Tile_X10Y5_LUT4AB 2140 1650 N
-Inst_eFPGA.Tile_X10Y6_LUT4AB 2140 1425 N
-Inst_eFPGA.Tile_X10Y7_LUT4AB 2140 1200 N
-Inst_eFPGA.Tile_X10Y8_LUT4AB 2140 975 N
-Inst_eFPGA.Tile_X10Y9_LUT4AB 2140 750 N
-Inst_eFPGA.Tile_X10Y10_LUT4AB 2140 525 N
-Inst_eFPGA.Tile_X10Y11_LUT4AB 2140 300 N
-Inst_eFPGA.Tile_X10Y12_LUT4AB 2140 75 N
-Inst_eFPGA.Tile_X10Y13_S_term_single 2140 40 N
-Inst_eFPGA.Tile_X11Y0_N_term_single 2355 2775 N
-Inst_eFPGA.Tile_X11Y1_LUT4AB 2355 2550 N
-Inst_eFPGA.Tile_X11Y2_LUT4AB 2355 2325 N
-Inst_eFPGA.Tile_X11Y3_LUT4AB 2355 2100 N
-Inst_eFPGA.Tile_X11Y4_LUT4AB 2355 1875 N
-Inst_eFPGA.Tile_X11Y5_LUT4AB 2355 1650 N
-Inst_eFPGA.Tile_X11Y6_LUT4AB 2355 1425 N
-Inst_eFPGA.Tile_X11Y7_LUT4AB 2355 1200 N
-Inst_eFPGA.Tile_X11Y8_LUT4AB 2355 975 N
-Inst_eFPGA.Tile_X11Y9_LUT4AB 2355 750 N
-Inst_eFPGA.Tile_X11Y10_LUT4AB 2355 525 N
-Inst_eFPGA.Tile_X11Y11_LUT4AB 2355 300 N
-Inst_eFPGA.Tile_X11Y12_LUT4AB 2355 75 N
-Inst_eFPGA.Tile_X11Y13_S_term_single 2355 40 N
-Inst_eFPGA.Tile_X12Y0_N_term_single 2570 2775 N
-Inst_eFPGA.Tile_X12Y1_LUT4AB 2570 2550 N
-Inst_eFPGA.Tile_X12Y2_LUT4AB 2570 2325 N
-Inst_eFPGA.Tile_X12Y3_LUT4AB 2570 2100 N
-Inst_eFPGA.Tile_X12Y4_LUT4AB 2570 1875 N
-Inst_eFPGA.Tile_X12Y5_LUT4AB 2570 1650 N
-Inst_eFPGA.Tile_X12Y6_LUT4AB 2570 1425 N
-Inst_eFPGA.Tile_X12Y7_LUT4AB 2570 1200 N
-Inst_eFPGA.Tile_X12Y8_LUT4AB 2570 975 N
-Inst_eFPGA.Tile_X12Y9_LUT4AB 2570 750 N
-Inst_eFPGA.Tile_X12Y10_LUT4AB 2570 525 N
-Inst_eFPGA.Tile_X12Y11_LUT4AB 2570 300 N
-Inst_eFPGA.Tile_X12Y12_LUT4AB 2570 75 N
-Inst_eFPGA.Tile_X12Y13_S_term_single 2570 40 N
-Inst_eFPGA.Tile_X13Y0_N_term_RAM_IO 2785 2775 N
-Inst_eFPGA.Tile_X13Y1_RAM_IO 2785 2550 N
-Inst_eFPGA.Tile_X13Y2_RAM_IO 2785 2325 N
-Inst_eFPGA.Tile_X13Y3_RAM_IO 2785 2100 N
-Inst_eFPGA.Tile_X13Y4_RAM_IO 2785 1875 N
-Inst_eFPGA.Tile_X13Y5_RAM_IO 2785 1650 N
-Inst_eFPGA.Tile_X13Y6_RAM_IO 2785 1425 N
-Inst_eFPGA.Tile_X13Y7_RAM_IO 2785 1200 N
-Inst_eFPGA.Tile_X13Y8_RAM_IO 2785 975 N
-Inst_eFPGA.Tile_X13Y9_RAM_IO 2785 750 N
-Inst_eFPGA.Tile_X13Y10_RAM_IO 2785 525 N
-Inst_eFPGA.Tile_X13Y11_RAM_IO 2785 300 N
-Inst_eFPGA.Tile_X13Y12_RAM_IO 2785 75 N
-Inst_eFPGA.Tile_X13Y13_S_term_RAM_IO 2785 40 N
-Inst_BlockRAM_0.memory_cell 2900 70 R90
-Inst_BlockRAM_1.memory_cell 2900 750 R90
-Inst_BlockRAM_2.memory_cell 2900 1430 R90
-Inst_BlockRAM_3.memory_cell 2900 2110 R90
diff --git a/openlane/user_project_wrapper/macros/placements/Old_v2/macro_placement.cfg.old b/openlane/user_project_wrapper/macros/placements/Old_v2/macro_placement.cfg.old
deleted file mode 100644
index cb86efc..0000000
--- a/openlane/user_project_wrapper/macros/placements/Old_v2/macro_placement.cfg.old
+++ /dev/null
@@ -1,192 +0,0 @@
-Inst_eFPGA.Tile_X0Y1_W_IO 20 2530 N
-Inst_eFPGA.Tile_X0Y2_W_IO 20 2305 N
-Inst_eFPGA.Tile_X0Y3_W_IO 20 2080 N
-Inst_eFPGA.Tile_X0Y4_W_IO 20 1855 N
-Inst_eFPGA.Tile_X0Y5_W_IO 20 1630 N
-Inst_eFPGA.Tile_X0Y6_W_IO 20 1405 N
-Inst_eFPGA.Tile_X0Y7_W_IO 20 1180 N
-Inst_eFPGA.Tile_X0Y8_W_IO 20 955 N
-Inst_eFPGA.Tile_X0Y9_W_IO 20 730 N
-Inst_eFPGA.Tile_X0Y10_W_IO 20 505 N
-Inst_eFPGA.Tile_X0Y11_W_IO 20 280 N
-Inst_eFPGA.Tile_X0Y12_W_IO 20 55 N
-Inst_eFPGA.Tile_X1Y0_N_term_single 95 2755 N
-Inst_eFPGA.Tile_X1Y1_LUT4AB 95 2530 N
-Inst_eFPGA.Tile_X1Y2_LUT4AB 95 2305 N
-Inst_eFPGA.Tile_X1Y3_LUT4AB 95 2080 N
-Inst_eFPGA.Tile_X1Y4_LUT4AB 95 1855 N
-Inst_eFPGA.Tile_X1Y5_LUT4AB 95 1630 N
-Inst_eFPGA.Tile_X1Y6_LUT4AB 95 1405 N
-Inst_eFPGA.Tile_X1Y7_LUT4AB 95 1180 N
-Inst_eFPGA.Tile_X1Y8_LUT4AB 95 955 N
-Inst_eFPGA.Tile_X1Y9_LUT4AB 95 730 N
-Inst_eFPGA.Tile_X1Y10_LUT4AB 95 505 N
-Inst_eFPGA.Tile_X1Y11_LUT4AB 95 280 N
-Inst_eFPGA.Tile_X1Y12_LUT4AB 95 55 N
-Inst_eFPGA.Tile_X1Y13_S_term_single 95 20 N
-Inst_eFPGA.Tile_X2Y0_N_term_single 310 2755 N
-Inst_eFPGA.Tile_X2Y1_LUT4AB 310 2530 N
-Inst_eFPGA.Tile_X2Y2_LUT4AB 310 2305 N
-Inst_eFPGA.Tile_X2Y3_LUT4AB 310 2080 N
-Inst_eFPGA.Tile_X2Y4_LUT4AB 310 1855 N
-Inst_eFPGA.Tile_X2Y5_LUT4AB 310 1630 N
-Inst_eFPGA.Tile_X2Y6_LUT4AB 310 1405 N
-Inst_eFPGA.Tile_X2Y7_LUT4AB 310 1180 N
-Inst_eFPGA.Tile_X2Y8_LUT4AB 310 955 N
-Inst_eFPGA.Tile_X2Y9_LUT4AB 310 730 N
-Inst_eFPGA.Tile_X2Y10_LUT4AB 310 505 N
-Inst_eFPGA.Tile_X2Y11_LUT4AB 310 280 N
-Inst_eFPGA.Tile_X2Y12_LUT4AB 310 55 N
-Inst_eFPGA.Tile_X2Y13_S_term_single 310 20 N
-Inst_eFPGA.Tile_X3Y0_N_term_single 525 2755 N
-Inst_eFPGA.Tile_X3Y1_LUT4AB 525 2530 N
-Inst_eFPGA.Tile_X3Y2_LUT4AB 525 2305 N
-Inst_eFPGA.Tile_X3Y3_LUT4AB 525 2080 N
-Inst_eFPGA.Tile_X3Y4_LUT4AB 525 1855 N
-Inst_eFPGA.Tile_X3Y5_LUT4AB 525 1630 N
-Inst_eFPGA.Tile_X3Y6_LUT4AB 525 1405 N
-Inst_eFPGA.Tile_X3Y7_LUT4AB 525 1180 N
-Inst_eFPGA.Tile_X3Y8_LUT4AB 525 955 N
-Inst_eFPGA.Tile_X3Y9_LUT4AB 525 730 N
-Inst_eFPGA.Tile_X3Y10_LUT4AB 525 505 N
-Inst_eFPGA.Tile_X3Y11_LUT4AB 525 280 N
-Inst_eFPGA.Tile_X3Y12_LUT4AB 525 55 N
-Inst_eFPGA.Tile_X3Y13_S_term_single 525 20 N
-Inst_eFPGA.Tile_X4Y0_N_term_single2 740 2755 N
-Inst_eFPGA.Tile_X4Y1_RegFile 740 2530 N
-Inst_eFPGA.Tile_X4Y2_RegFile 740 2305 N
-Inst_eFPGA.Tile_X4Y3_RegFile 740 2080 N
-Inst_eFPGA.Tile_X4Y4_RegFile 740 1855 N
-Inst_eFPGA.Tile_X4Y5_RegFile 740 1630 N
-Inst_eFPGA.Tile_X4Y6_RegFile 740 1405 N
-Inst_eFPGA.Tile_X4Y7_RegFile 740 1180 N
-Inst_eFPGA.Tile_X4Y8_RegFile 740 955 N
-Inst_eFPGA.Tile_X4Y9_RegFile 740 730 N
-Inst_eFPGA.Tile_X4Y10_RegFile 740 505 N
-Inst_eFPGA.Tile_X4Y11_RegFile 740 280 N
-Inst_eFPGA.Tile_X4Y12_RegFile 740 55 N
-Inst_eFPGA.Tile_X4Y13_S_term_single2 740 20 N
-Inst_eFPGA.Tile_X5Y0_N_term_single 985 2755 N
-Inst_eFPGA.Tile_X5Y1_LUT4AB 985 2530 N
-Inst_eFPGA.Tile_X5Y2_LUT4AB 985 2305 N
-Inst_eFPGA.Tile_X5Y3_LUT4AB 985 2080 N
-Inst_eFPGA.Tile_X5Y4_LUT4AB 985 1855 N
-Inst_eFPGA.Tile_X5Y5_LUT4AB 985 1630 N
-Inst_eFPGA.Tile_X5Y6_LUT4AB 985 1405 N
-Inst_eFPGA.Tile_X5Y7_LUT4AB 985 1180 N
-Inst_eFPGA.Tile_X5Y8_LUT4AB 985 955 N
-Inst_eFPGA.Tile_X5Y9_LUT4AB 985 730 N
-Inst_eFPGA.Tile_X5Y10_LUT4AB 985 505 N
-Inst_eFPGA.Tile_X5Y11_LUT4AB 985 280 N
-Inst_eFPGA.Tile_X5Y12_LUT4AB 985 55 N
-Inst_eFPGA.Tile_X5Y13_S_term_single 985 20 N
-Inst_eFPGA.Tile_X6Y0_N_term_single 1200 2755 N
-Inst_eFPGA.Tile_X6Y1_LUT4AB 1200 2530 N
-Inst_eFPGA.Tile_X6Y2_LUT4AB 1200 2305 N
-Inst_eFPGA.Tile_X6Y3_LUT4AB 1200 2080 N
-Inst_eFPGA.Tile_X6Y4_LUT4AB 1200 1855 N
-Inst_eFPGA.Tile_X6Y5_LUT4AB 1200 1630 N
-Inst_eFPGA.Tile_X6Y6_LUT4AB 1200 1405 N
-Inst_eFPGA.Tile_X6Y7_LUT4AB 1200 1180 N
-Inst_eFPGA.Tile_X6Y8_LUT4AB 1200 955 N
-Inst_eFPGA.Tile_X6Y9_LUT4AB 1200 730 N
-Inst_eFPGA.Tile_X6Y10_LUT4AB 1200 505 N
-Inst_eFPGA.Tile_X6Y11_LUT4AB 1200 280 N
-Inst_eFPGA.Tile_X6Y12_LUT4AB 1200 55 N
-Inst_eFPGA.Tile_X6Y13_S_term_single 1200 20 N
-Inst_eFPGA.Tile_X7Y0_N_term_single 1415 2755 N
-Inst_eFPGA.Tile_X7Y1_LUT4AB 1415 2530 N
-Inst_eFPGA.Tile_X7Y2_LUT4AB 1415 2305 N
-Inst_eFPGA.Tile_X7Y3_LUT4AB 1415 2080 N
-Inst_eFPGA.Tile_X7Y4_LUT4AB 1415 1855 N
-Inst_eFPGA.Tile_X7Y5_LUT4AB 1415 1630 N
-Inst_eFPGA.Tile_X7Y6_LUT4AB 1415 1405 N
-Inst_eFPGA.Tile_X7Y7_LUT4AB 1415 1180 N
-Inst_eFPGA.Tile_X7Y8_LUT4AB 1415 955 N
-Inst_eFPGA.Tile_X7Y9_LUT4AB 1415 730 N
-Inst_eFPGA.Tile_X7Y10_LUT4AB 1415 505 N
-Inst_eFPGA.Tile_X7Y11_LUT4AB 1415 280 N
-Inst_eFPGA.Tile_X7Y12_LUT4AB 1415 55 N
-Inst_eFPGA.Tile_X7Y13_S_term_single 1415 20 N
-Inst_eFPGA.Tile_X8Y0_N_term_DSP 1630 2755 N
-Inst_eFPGA.Tile_X8Y1_X8Y2_DSP_tile 1630 2305 N
-Inst_eFPGA.Tile_X8Y3_X8Y4_DSP_tile 1630 1855 N
-Inst_eFPGA.Tile_X8Y5_X8Y6_DSP_tile 1630 1405 N
-Inst_eFPGA.Tile_X8Y7_X8Y8_DSP_tile 1630 955 N
-Inst_eFPGA.Tile_X8Y9_X8Y10_DSP_tile 1630 505 N
-Inst_eFPGA.Tile_X8Y11_X8Y12_DSP_tile 1630 55 N
-Inst_eFPGA.Tile_X8Y13_S_term_DSP 1630 20 N
-Inst_eFPGA.Tile_X9Y0_N_term_single 1845 2755 N
-Inst_eFPGA.Tile_X9Y1_LUT4AB 1845 2530 N
-Inst_eFPGA.Tile_X9Y2_LUT4AB 1845 2305 N
-Inst_eFPGA.Tile_X9Y3_LUT4AB 1845 2080 N
-Inst_eFPGA.Tile_X9Y4_LUT4AB 1845 1855 N
-Inst_eFPGA.Tile_X9Y5_LUT4AB 1845 1630 N
-Inst_eFPGA.Tile_X9Y6_LUT4AB 1845 1405 N
-Inst_eFPGA.Tile_X9Y7_LUT4AB 1845 1180 N
-Inst_eFPGA.Tile_X9Y8_LUT4AB 1845 955 N
-Inst_eFPGA.Tile_X9Y9_LUT4AB 1845 730 N
-Inst_eFPGA.Tile_X9Y10_LUT4AB 1845 505 N
-Inst_eFPGA.Tile_X9Y11_LUT4AB 1845 280 N
-Inst_eFPGA.Tile_X9Y12_LUT4AB 1845 55 N
-Inst_eFPGA.Tile_X9Y13_S_term_single 1845 20 N
-Inst_eFPGA.Tile_X10Y0_N_term_single 2060 2755 N
-Inst_eFPGA.Tile_X10Y1_LUT4AB 2060 2530 N
-Inst_eFPGA.Tile_X10Y2_LUT4AB 2060 2305 N
-Inst_eFPGA.Tile_X10Y3_LUT4AB 2060 2080 N
-Inst_eFPGA.Tile_X10Y4_LUT4AB 2060 1855 N
-Inst_eFPGA.Tile_X10Y5_LUT4AB 2060 1630 N
-Inst_eFPGA.Tile_X10Y6_LUT4AB 2060 1405 N
-Inst_eFPGA.Tile_X10Y7_LUT4AB 2060 1180 N
-Inst_eFPGA.Tile_X10Y8_LUT4AB 2060 955 N
-Inst_eFPGA.Tile_X10Y9_LUT4AB 2060 730 N
-Inst_eFPGA.Tile_X10Y10_LUT4AB 2060 505 N
-Inst_eFPGA.Tile_X10Y11_LUT4AB 2060 280 N
-Inst_eFPGA.Tile_X10Y12_LUT4AB 2060 55 N
-Inst_eFPGA.Tile_X10Y13_S_term_single 2060 20 N
-Inst_eFPGA.Tile_X11Y0_N_term_single 2275 2755 N
-Inst_eFPGA.Tile_X11Y1_LUT4AB 2275 2530 N
-Inst_eFPGA.Tile_X11Y2_LUT4AB 2275 2305 N
-Inst_eFPGA.Tile_X11Y3_LUT4AB 2275 2080 N
-Inst_eFPGA.Tile_X11Y4_LUT4AB 2275 1855 N
-Inst_eFPGA.Tile_X11Y5_LUT4AB 2275 1630 N
-Inst_eFPGA.Tile_X11Y6_LUT4AB 2275 1405 N
-Inst_eFPGA.Tile_X11Y7_LUT4AB 2275 1180 N
-Inst_eFPGA.Tile_X11Y8_LUT4AB 2275 955 N
-Inst_eFPGA.Tile_X11Y9_LUT4AB 2275 730 N
-Inst_eFPGA.Tile_X11Y10_LUT4AB 2275 505 N
-Inst_eFPGA.Tile_X11Y11_LUT4AB 2275 280 N
-Inst_eFPGA.Tile_X11Y12_LUT4AB 2275 55 N
-Inst_eFPGA.Tile_X11Y13_S_term_single 2275 20 N
-Inst_eFPGA.Tile_X12Y0_N_term_single 2490 2755 N
-Inst_eFPGA.Tile_X12Y1_LUT4AB 2490 2530 N
-Inst_eFPGA.Tile_X12Y2_LUT4AB 2490 2305 N
-Inst_eFPGA.Tile_X12Y3_LUT4AB 2490 2080 N
-Inst_eFPGA.Tile_X12Y4_LUT4AB 2490 1855 N
-Inst_eFPGA.Tile_X12Y5_LUT4AB 2490 1630 N
-Inst_eFPGA.Tile_X12Y6_LUT4AB 2490 1405 N
-Inst_eFPGA.Tile_X12Y7_LUT4AB 2490 1180 N
-Inst_eFPGA.Tile_X12Y8_LUT4AB 2490 955 N
-Inst_eFPGA.Tile_X12Y9_LUT4AB 2490 730 N
-Inst_eFPGA.Tile_X12Y10_LUT4AB 2490 505 N
-Inst_eFPGA.Tile_X12Y11_LUT4AB 2490 280 N
-Inst_eFPGA.Tile_X12Y12_LUT4AB 2490 55 N
-Inst_eFPGA.Tile_X12Y13_S_term_single 2490 20 N
-Inst_eFPGA.Tile_X13Y0_N_term_RAM_IO 2705 2755 N
-Inst_eFPGA.Tile_X13Y1_RAM_IO 2705 2530 N
-Inst_eFPGA.Tile_X13Y2_RAM_IO 2705 2305 N
-Inst_eFPGA.Tile_X13Y3_RAM_IO 2705 2080 N
-Inst_eFPGA.Tile_X13Y4_RAM_IO 2705 1855 N
-Inst_eFPGA.Tile_X13Y5_RAM_IO 2705 1630 N
-Inst_eFPGA.Tile_X13Y6_RAM_IO 2705 1405 N
-Inst_eFPGA.Tile_X13Y7_RAM_IO 2705 1180 N
-Inst_eFPGA.Tile_X13Y8_RAM_IO 2705 955 N
-Inst_eFPGA.Tile_X13Y9_RAM_IO 2705 730 N
-Inst_eFPGA.Tile_X13Y10_RAM_IO 2705 505 N
-Inst_eFPGA.Tile_X13Y11_RAM_IO 2705 280 N
-Inst_eFPGA.Tile_X13Y12_RAM_IO 2705 55 N
-Inst_eFPGA.Tile_X13Y13_S_term_RAM_IO 2705 20 N
-Inst_BlockRAM_0.memory_cell 3000 55 N
-Inst_BlockRAM_1.memory_cell 3000 730 N
-Inst_BlockRAM_2.memory_cell 3000 1405 N
-Inst_BlockRAM_3.memory_cell 3000 2080 N
diff --git a/openlane/user_project_wrapper/macros/placements/__pycache__/fabric_params.cpython-36.pyc b/openlane/user_project_wrapper/macros/placements/__pycache__/fabric_params.cpython-36.pyc
deleted file mode 100644
index d6fed77..0000000
--- a/openlane/user_project_wrapper/macros/placements/__pycache__/fabric_params.cpython-36.pyc
+++ /dev/null
Binary files differ
diff --git a/openlane/user_project_wrapper/macros/placements/fabric_params.py b/openlane/user_project_wrapper/macros/placements/fabric_params.py
deleted file mode 100644
index cdd6441..0000000
--- a/openlane/user_project_wrapper/macros/placements/fabric_params.py
+++ /dev/null
@@ -1,24 +0,0 @@
-col = 8
-row = 12
-regfile_col = [3]
-DSP_col = [6]
-LUT4AB_size = [200.1, 200.26]
-DSP_size = [200.1, 400.52]
-RegFile_size = [200.1, 200.26]
-W_IO_size = [80.04, 200.26]
-RAM_IO_size = [109.94, 200.26]
-BRAM_size = [529.92, 420.24]
-N_term_single_size = [200.1, 30.26]
-N_term_DSP_size = [200.1, 30.26]
-N_term_single2_size = [200.1, 30.26]
-N_term_RAM_IO_size = [200.1, 30.26]
-S_term_single_size = [200.1, 30.26]
-S_term_DSP_size = [200.1, 30.26]
-S_term_single2_size = [200.1, 30.26]
-S_term_RAM_IO_size = [200.1, 30.26]
-Space = 20
-SpaceW = 20
-Space_BRAM = 20
-Offset_WL = 150
-Offset_WR = 50
-Offset_H = 250
diff --git a/openlane/user_project_wrapper/macros/placements/fabric_params.pyc b/openlane/user_project_wrapper/macros/placements/fabric_params.pyc
deleted file mode 100644
index 37a450f..0000000
--- a/openlane/user_project_wrapper/macros/placements/fabric_params.pyc
+++ /dev/null
Binary files differ
diff --git a/openlane/user_project_wrapper/macros/placements/gen_placement.py b/openlane/user_project_wrapper/macros/placements/gen_placement.py
deleted file mode 100644
index 9ad7daa..0000000
--- a/openlane/user_project_wrapper/macros/placements/gen_placement.py
+++ /dev/null
@@ -1,158 +0,0 @@
-import re
-from array import *
-import fileinput
-import sys, getopt
-import csv
-import fabric_params
-
-COL = fabric_params.col
-ROW = fabric_params.row
-REGFILE = fabric_params.regfile_col
-DSP = fabric_params.DSP_col
-
-LUT4AB_size = fabric_params.LUT4AB_size 
-DSP_size = fabric_params.DSP_size
-RegFile_size = fabric_params.RegFile_size
-W_IO_size = fabric_params.W_IO_size 
-RAM_IO_size = fabric_params.RAM_IO_size 
-BRAM_size = fabric_params.BRAM_size 
-N_term_single_size = fabric_params.N_term_single_size 
-N_term_single2_size = fabric_params.N_term_single2_size
-N_term_RAM_IO_size = fabric_params.N_term_RAM_IO_size 
-S_term_single_size = fabric_params.S_term_single_size 
-S_term_single2_size = fabric_params.S_term_single2_size
-S_term_RAM_IO_size = fabric_params.S_term_RAM_IO_size 
-Space = fabric_params.Space
-SpaceW = fabric_params.SpaceW
-Space_BRAM = fabric_params.Space_BRAM
-offset_WL = fabric_params.Offset_WL
-offset_WR = fabric_params.Offset_WR
-offset_H = fabric_params.Offset_H
-
-LUT4AB_W = LUT4AB_size[0]
-LUT4AB_H = LUT4AB_size[1]
-DSP_W = DSP_size[0]
-DSP_H = DSP_size[1]
-BRAM_W = BRAM_size[0]
-BRAM_H = BRAM_size[1]
-RegFile_W = RegFile_size[0]
-RegFile_H = RegFile_size[1]
-N_term_H = N_term_single_size[1]
-S_term_H = S_term_single_size[1]
-W_IO_W = W_IO_size[0]
-W_IO_H = W_IO_size[1]
-RAM_IO_W = RAM_IO_size[0]
-RAM_IO_H = RAM_IO_size[1]
-
-#offset = 10
-x_co = 0
-y_co = 0
-reg_count = 0
-bram_count = int(ROW/2 - 1)
-placement = ""
-Tile_H = W_IO_H
-if REGFILE[0] == 0:
-   No_RegFile_col = 0
-else:
-   No_RegFile_col = len(REGFILE)
-if DSP[0] == 0:
-   No_DSP_col = 0
-else:
-   No_DSP_col = len(DSP)
-No_LUT4AB_col = COL - No_RegFile_col - No_DSP_col
-
-core_H = ROW*Tile_H + (ROW-1)*Space
-core_W = No_LUT4AB_col*LUT4AB_W + No_DSP_col*DSP_W + No_RegFile_col*RegFile_W + (COL-1)*SpaceW 
-#fabric_H = 3400 
-fabric_H = N_term_H + core_H + S_term_H + 2*Space + 2*offset_H
-fabric_W = offset_WL + W_IO_W + core_W + RAM_IO_W + 2*Space + Space_BRAM + BRAM_W + offset_WR
-
-print ('column = ', COL)
-print ('row = ', ROW)
-print ('LUT4AB col = ', No_LUT4AB_col, 'DSP_col = ',No_DSP_col,'regfile col = ',No_RegFile_col)
-print ('fabric_H = ', core_H)
-print ('fabric_W = ', core_W)
-print ('AREA (XY) = {} x {}'.format(fabric_W, fabric_H))
-
-#try:
-#    with open("sdc_template.sdc", 'r') as file :
-#        placement = file.read()
-#except IOError:
-#    print("sdc_template.sdc is not accesstable")
-
-##############
-## Tile column
-## x = 0 : W_IO
-## 1 <= x =< COL : LUT4AB, RegFile
-## x = COL+1 : RAM_IO
-## x = COL+2 : BRAM
-##############
-
-for x in range(COL+3):
-    if x==0:
-         x_co = offset_WL
-    elif x==COL+2:
-         x_co += RAM_IO_W + Space_BRAM
-         #x_co = fabric_W + Space_BRAM
-    else:
-         x_co = offset_WL + W_IO_W + (x-reg_count-1)*LUT4AB_W + reg_count*RegFile_W + x*SpaceW
-         #print('x - reg_col -1 =',x-reg_count-1,'reg_count = ',reg_count)
-    print('x_co = '+str(x_co)+'at x = '+str(x))
-    if REGFILE.count(x) == 1:
-         reg_count += 1
-         #print('reg col =',x,'reg_count = ',reg_count)
-
-    for y in range(ROW+2):
-         Tile = 'inst_eFPGA_top.Inst_eFPGA.Tile_X'+str(x)+'Y'+str(y)
-         if y==0: 
-             y_co = fabric_H - N_term_H - offset_H
-         elif y==ROW+1:
-             y_co -= (S_term_H + Space)
-             #y_co = fabric_H - N_term_H - core_H - 2*Space - S_term_H - offset_H
-         elif y%2 == 0:
-             y_co -= (Tile_H + Space) 
-             #y_co = fabric_H - N_term_H - y*Tile_H - y*Space - offset_H
-         else:
-             y_co -= (Tile_H + Space) 
-
-         if x == 0 and y != 0 and y  <= ROW:
-             placement += str(Tile)+'_W_IO '+str(x_co)+' '+str(y_co)+' N\n'
-         if y == 0 and x != 0 and x <= COL:
-             if REGFILE.count(x) == 1:
-                 placement += str(Tile)+'_N_term_single2 '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) == 1:
-                 placement += str(Tile)+'_N_term_DSP '+str(x_co)+' '+str(y_co)+' N\n'
-             else:
-                 placement += str(Tile)+'_N_term_single '+str(x_co)+' '+str(y_co)+' N\n'
-         if x >= 1 and y >= 1 and x <= COL and y <= ROW: 
-             if REGFILE.count(x) == 1:
-                 placement += str(Tile)+'_RegFile '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) == 1 and y%2 == 0:
-                 Tile = 'inst_eFPGA_top.Inst_eFPGA.Tile_X'+str(x)+'Y'+str(y-1)+'_X'+str(x)+'Y'+str(y)
-                 placement += str(Tile)+'_DSP_tile '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) != 1:
-                 placement += str(Tile)+'_LUT4AB '+str(x_co)+' '+str(y_co)+' N\n'
-         if y == ROW+1 and x != 0 and x <= COL:
-             if REGFILE.count(x) == 1:
-                 placement += str(Tile)+'_S_term_single2 '+str(x_co)+' '+str(y_co)+' N\n'
-             elif DSP.count(x) == 1:
-                 placement += str(Tile)+'_S_term_DSP '+str(x_co)+' '+str(y_co)+' N\n'
-             else:
-                 placement += str(Tile)+'_S_term_single '+str(x_co)+' '+str(y_co)+' N\n'
-         if x == COL+1 and y == 0:
-             placement += str(Tile)+'_N_term_RAM_IO '+str(x_co)+' '+str(y_co)+' N\n'
-         if x == COL+1 and y >= 1 and y <= ROW: 
-             placement += str(Tile)+'_RAM_IO '+str(x_co)+' '+str(y_co)+' N\n'
-         if x == COL+1 and y == ROW+1: 
-             placement += str(Tile)+'_S_term_RAM_IO '+str(x_co)+' '+str(y_co)+' N\n'
-     
-         if x == COL+2 and y%2 == 0 and y <= ROW and y >= 1:
-             Tile = 'inst_eFPGA_top.Inst_BlockRAM_'+str(bram_count)+' '
-             #Tile = 'Inst_BlockRAM_'+str(bram_count)+'.memory_cell '
-             placement += str(Tile)+str(x_co)+' '+str(y_co)+' N\n'
-             bram_count -= 1
-
-if placement:
-   with open("./macro_placement.cfg", 'w') as file:
-        file.write(placement) 
-
diff --git a/openlane/user_project_wrapper/macros/placements/inst_list.txt b/openlane/user_project_wrapper/macros/placements/inst_list.txt
deleted file mode 100644
index 9481f97..0000000
--- a/openlane/user_project_wrapper/macros/placements/inst_list.txt
+++ /dev/null
@@ -1,287 +0,0 @@
-Tile_X1Y0_N_term_single
-Tile_X2Y0_N_term_single
-Tile_X3Y0_N_term_single
-Tile_X4Y0_N_term_single2
-Tile_X5Y0_N_term_single
-Tile_X6Y0_N_term_single
-Tile_X7Y0_N_term_single
-Tile_X8Y0_N_term_single2
-Tile_X9Y0_N_term_single
-Tile_X10Y0_N_term_single
-Tile_X11Y0_N_term_single
-Tile_X12Y0_N_term_single2
-Tile_X13Y0_N_term_single
-Tile_X14Y0_N_term_single
-Tile_X15Y0_N_term_single
-Tile_X16Y0_N_term_RAM_IO
-Tile_X0Y1_W_IO
-Tile_X1Y1_LUT4AB
-Tile_X2Y1_LUT4AB
-Tile_X3Y1_LUT4AB
-Tile_X4Y1_RegFile
-Tile_X5Y1_LUT4AB
-Tile_X6Y1_LUT4AB
-Tile_X7Y1_LUT4AB
-Tile_X8Y1_RegFile
-Tile_X9Y1_LUT4AB
-Tile_X10Y1_LUT4AB
-Tile_X11Y1_LUT4AB
-Tile_X12Y1_RegFile
-Tile_X13Y1_LUT4AB
-Tile_X14Y1_LUT4AB
-Tile_X15Y1_LUT4AB
-Tile_X16Y1_RAM_IO
-Tile_X0Y2_W_IO
-Tile_X1Y2_LUT4AB
-Tile_X2Y2_LUT4AB
-Tile_X3Y2_LUT4AB
-Tile_X4Y2_RegFile
-Tile_X5Y2_LUT4AB
-Tile_X6Y2_LUT4AB
-Tile_X7Y2_LUT4AB
-Tile_X8Y2_RegFile
-Tile_X9Y2_LUT4AB
-Tile_X10Y2_LUT4AB
-Tile_X11Y2_LUT4AB
-Tile_X12Y2_RegFile
-Tile_X13Y2_LUT4AB
-Tile_X14Y2_LUT4AB
-Tile_X15Y2_LUT4AB
-Tile_X16Y2_RAM_IO
-Tile_X0Y3_W_IO
-Tile_X1Y3_LUT4AB
-Tile_X2Y3_LUT4AB
-Tile_X3Y3_LUT4AB
-Tile_X4Y3_RegFile
-Tile_X5Y3_LUT4AB
-Tile_X6Y3_LUT4AB
-Tile_X7Y3_LUT4AB
-Tile_X8Y3_RegFile
-Tile_X9Y3_LUT4AB
-Tile_X10Y3_LUT4AB
-Tile_X11Y3_LUT4AB
-Tile_X12Y3_RegFile
-Tile_X13Y3_LUT4AB
-Tile_X14Y3_LUT4AB
-Tile_X15Y3_LUT4AB
-Tile_X16Y3_RAM_IO
-Tile_X0Y4_W_IO
-Tile_X1Y4_LUT4AB
-Tile_X2Y4_LUT4AB
-Tile_X3Y4_LUT4AB
-Tile_X4Y4_RegFile
-Tile_X5Y4_LUT4AB
-Tile_X6Y4_LUT4AB
-Tile_X7Y4_LUT4AB
-Tile_X8Y4_RegFile
-Tile_X9Y4_LUT4AB
-Tile_X10Y4_LUT4AB
-Tile_X11Y4_LUT4AB
-Tile_X12Y4_RegFile
-Tile_X13Y4_LUT4AB
-Tile_X14Y4_LUT4AB
-Tile_X15Y4_LUT4AB
-Tile_X16Y4_RAM_IO
-Tile_X0Y5_W_IO
-Tile_X1Y5_LUT4AB
-Tile_X2Y5_LUT4AB
-Tile_X3Y5_LUT4AB
-Tile_X4Y5_RegFile
-Tile_X5Y5_LUT4AB
-Tile_X6Y5_LUT4AB
-Tile_X7Y5_LUT4AB
-Tile_X8Y5_RegFile
-Tile_X9Y5_LUT4AB
-Tile_X10Y5_LUT4AB
-Tile_X11Y5_LUT4AB
-Tile_X12Y5_RegFile
-Tile_X13Y5_LUT4AB
-Tile_X14Y5_LUT4AB
-Tile_X15Y5_LUT4AB
-Tile_X16Y5_RAM_IO
-Tile_X0Y6_W_IO
-Tile_X1Y6_LUT4AB
-Tile_X2Y6_LUT4AB
-Tile_X3Y6_LUT4AB
-Tile_X4Y6_RegFile
-Tile_X5Y6_LUT4AB
-Tile_X6Y6_LUT4AB
-Tile_X7Y6_LUT4AB
-Tile_X8Y6_RegFile
-Tile_X9Y6_LUT4AB
-Tile_X10Y6_LUT4AB
-Tile_X11Y6_LUT4AB
-Tile_X12Y6_RegFile
-Tile_X13Y6_LUT4AB
-Tile_X14Y6_LUT4AB
-Tile_X15Y6_LUT4AB
-Tile_X16Y6_RAM_IO
-Tile_X0Y7_W_IO
-Tile_X1Y7_LUT4AB
-Tile_X2Y7_LUT4AB
-Tile_X3Y7_LUT4AB
-Tile_X4Y7_RegFile
-Tile_X5Y7_LUT4AB
-Tile_X6Y7_LUT4AB
-Tile_X7Y7_LUT4AB
-Tile_X8Y7_RegFile
-Tile_X9Y7_LUT4AB
-Tile_X10Y7_LUT4AB
-Tile_X11Y7_LUT4AB
-Tile_X12Y7_RegFile
-Tile_X13Y7_LUT4AB
-Tile_X14Y7_LUT4AB
-Tile_X15Y7_LUT4AB
-Tile_X16Y7_RAM_IO
-Tile_X0Y8_W_IO
-Tile_X1Y8_LUT4AB
-Tile_X2Y8_LUT4AB
-Tile_X3Y8_LUT4AB
-Tile_X4Y8_RegFile
-Tile_X5Y8_LUT4AB
-Tile_X6Y8_LUT4AB
-Tile_X7Y8_LUT4AB
-Tile_X8Y8_RegFile
-Tile_X9Y8_LUT4AB
-Tile_X10Y8_LUT4AB
-Tile_X11Y8_LUT4AB
-Tile_X12Y8_RegFile
-Tile_X13Y8_LUT4AB
-Tile_X14Y8_LUT4AB
-Tile_X15Y8_LUT4AB
-Tile_X16Y8_RAM_IO
-Tile_X0Y9_W_IO
-Tile_X1Y9_LUT4AB
-Tile_X2Y9_LUT4AB
-Tile_X3Y9_LUT4AB
-Tile_X4Y9_RegFile
-Tile_X5Y9_LUT4AB
-Tile_X6Y9_LUT4AB
-Tile_X7Y9_LUT4AB
-Tile_X8Y9_RegFile
-Tile_X9Y9_LUT4AB
-Tile_X10Y9_LUT4AB
-Tile_X11Y9_LUT4AB
-Tile_X12Y9_RegFile
-Tile_X13Y9_LUT4AB
-Tile_X14Y9_LUT4AB
-Tile_X15Y9_LUT4AB
-Tile_X16Y9_RAM_IO
-Tile_X0Y10_W_IO
-Tile_X1Y10_LUT4AB
-Tile_X2Y10_LUT4AB
-Tile_X3Y10_LUT4AB
-Tile_X4Y10_RegFile
-Tile_X5Y10_LUT4AB
-Tile_X6Y10_LUT4AB
-Tile_X7Y10_LUT4AB
-Tile_X8Y10_RegFile
-Tile_X9Y10_LUT4AB
-Tile_X10Y10_LUT4AB
-Tile_X11Y10_LUT4AB
-Tile_X12Y10_RegFile
-Tile_X13Y10_LUT4AB
-Tile_X14Y10_LUT4AB
-Tile_X15Y10_LUT4AB
-Tile_X16Y10_RAM_IO
-Tile_X0Y11_W_IO
-Tile_X1Y11_LUT4AB
-Tile_X2Y11_LUT4AB
-Tile_X3Y11_LUT4AB
-Tile_X4Y11_RegFile
-Tile_X5Y11_LUT4AB
-Tile_X6Y11_LUT4AB
-Tile_X7Y11_LUT4AB
-Tile_X8Y11_RegFile
-Tile_X9Y11_LUT4AB
-Tile_X10Y11_LUT4AB
-Tile_X11Y11_LUT4AB
-Tile_X12Y11_RegFile
-Tile_X13Y11_LUT4AB
-Tile_X14Y11_LUT4AB
-Tile_X15Y11_LUT4AB
-Tile_X16Y11_RAM_IO
-Tile_X0Y12_W_IO
-Tile_X1Y12_LUT4AB
-Tile_X2Y12_LUT4AB
-Tile_X3Y12_LUT4AB
-Tile_X4Y12_RegFile
-Tile_X5Y12_LUT4AB
-Tile_X6Y12_LUT4AB
-Tile_X7Y12_LUT4AB
-Tile_X8Y12_RegFile
-Tile_X9Y12_LUT4AB
-Tile_X10Y12_LUT4AB
-Tile_X11Y12_LUT4AB
-Tile_X12Y12_RegFile
-Tile_X13Y12_LUT4AB
-Tile_X14Y12_LUT4AB
-Tile_X15Y12_LUT4AB
-Tile_X16Y12_RAM_IO
-Tile_X0Y13_W_IO
-Tile_X1Y13_LUT4AB
-Tile_X2Y13_LUT4AB
-Tile_X3Y13_LUT4AB
-Tile_X4Y13_RegFile
-Tile_X5Y13_LUT4AB
-Tile_X6Y13_LUT4AB
-Tile_X7Y13_LUT4AB
-Tile_X8Y13_RegFile
-Tile_X9Y13_LUT4AB
-Tile_X10Y13_LUT4AB
-Tile_X11Y13_LUT4AB
-Tile_X12Y13_RegFile
-Tile_X13Y13_LUT4AB
-Tile_X14Y13_LUT4AB
-Tile_X15Y13_LUT4AB
-Tile_X16Y13_RAM_IO
-Tile_X0Y14_W_IO
-Tile_X1Y14_LUT4AB
-Tile_X2Y14_LUT4AB
-Tile_X3Y14_LUT4AB
-Tile_X4Y14_RegFile
-Tile_X5Y14_LUT4AB
-Tile_X6Y14_LUT4AB
-Tile_X7Y14_LUT4AB
-Tile_X8Y14_RegFile
-Tile_X9Y14_LUT4AB
-Tile_X10Y14_LUT4AB
-Tile_X11Y14_LUT4AB
-Tile_X12Y14_RegFile
-Tile_X13Y14_LUT4AB
-Tile_X14Y14_LUT4AB
-Tile_X15Y14_LUT4AB
-Tile_X16Y14_RAM_IO
-Tile_X0Y15_W_IO
-Tile_X1Y15_LUT4AB
-Tile_X2Y15_LUT4AB
-Tile_X3Y15_LUT4AB
-Tile_X4Y15_RegFile
-Tile_X5Y15_LUT4AB
-Tile_X6Y15_LUT4AB
-Tile_X7Y15_LUT4AB
-Tile_X8Y15_RegFile
-Tile_X9Y15_LUT4AB
-Tile_X10Y15_LUT4AB
-Tile_X11Y15_LUT4AB
-Tile_X12Y15_RegFile
-Tile_X13Y15_LUT4AB
-Tile_X14Y15_LUT4AB
-Tile_X15Y15_LUT4AB
-Tile_X16Y15_RAM_IO
-Tile_X1Y16_S_term_single
-Tile_X2Y16_S_term_single
-Tile_X3Y16_S_term_single
-Tile_X4Y16_S_term_single2
-Tile_X5Y16_S_term_single
-Tile_X6Y16_S_term_single
-Tile_X7Y16_S_term_single
-Tile_X8Y16_S_term_single2
-Tile_X9Y16_S_term_single
-Tile_X10Y16_S_term_single
-Tile_X11Y16_S_term_single
-Tile_X12Y16_S_term_single2
-Tile_X13Y16_S_term_single
-Tile_X14Y16_S_term_single
-Tile_X15Y16_S_term_single
-Tile_X16Y16_S_term_RAM_IO
diff --git a/openlane/user_project_wrapper/macros/placements/macro_placement.cfg b/openlane/user_project_wrapper/macros/placements/macro_placement.cfg
index 5e1d16e..c1edc68 100644
--- a/openlane/user_project_wrapper/macros/placements/macro_placement.cfg
+++ b/openlane/user_project_wrapper/macros/placements/macro_placement.cfg
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 inst_eFPGA_top.Inst_eFPGA.Tile_X0Y1_W_IO 150 2723.12 N
 inst_eFPGA_top.Inst_eFPGA.Tile_X0Y2_W_IO 150 2502.8599999999997 N
 inst_eFPGA_top.Inst_eFPGA.Tile_X0Y3_W_IO 150 2282.5999999999995 N
diff --git a/openlane/user_project_wrapper/macros/placements/macro_placement.cfg.fabric b/openlane/user_project_wrapper/macros/placements/macro_placement.cfg.fabric
deleted file mode 100644
index 25b2e1e..0000000
--- a/openlane/user_project_wrapper/macros/placements/macro_placement.cfg.fabric
+++ /dev/null
@@ -1,138 +0,0 @@
-Inst_eFPGA.Tile_X0Y1_W_IO 100 2743.12 N
-Inst_eFPGA.Tile_X0Y2_W_IO 100 2512.8599999999997 N
-Inst_eFPGA.Tile_X0Y3_W_IO 100 2282.5999999999995 N
-Inst_eFPGA.Tile_X0Y4_W_IO 100 2052.3399999999992 N
-Inst_eFPGA.Tile_X0Y5_W_IO 100 1822.0799999999992 N
-Inst_eFPGA.Tile_X0Y6_W_IO 100 1591.8199999999993 N
-Inst_eFPGA.Tile_X0Y7_W_IO 100 1361.5599999999993 N
-Inst_eFPGA.Tile_X0Y8_W_IO 100 1131.2999999999993 N
-Inst_eFPGA.Tile_X0Y9_W_IO 100 901.0399999999993 N
-Inst_eFPGA.Tile_X0Y10_W_IO 100 670.7799999999993 N
-Inst_eFPGA.Tile_X0Y11_W_IO 100 440.5199999999993 N
-Inst_eFPGA.Tile_X0Y12_W_IO 100 210.2599999999993 N
-Inst_eFPGA.Tile_X1Y0_N_term_single 210.04000000000002 2973.38 N
-Inst_eFPGA.Tile_X1Y1_LUT4AB 210.04000000000002 2743.12 N
-Inst_eFPGA.Tile_X1Y2_LUT4AB 210.04000000000002 2512.8599999999997 N
-Inst_eFPGA.Tile_X1Y3_LUT4AB 210.04000000000002 2282.5999999999995 N
-Inst_eFPGA.Tile_X1Y4_LUT4AB 210.04000000000002 2052.3399999999992 N
-Inst_eFPGA.Tile_X1Y5_LUT4AB 210.04000000000002 1822.0799999999992 N
-Inst_eFPGA.Tile_X1Y6_LUT4AB 210.04000000000002 1591.8199999999993 N
-Inst_eFPGA.Tile_X1Y7_LUT4AB 210.04000000000002 1361.5599999999993 N
-Inst_eFPGA.Tile_X1Y8_LUT4AB 210.04000000000002 1131.2999999999993 N
-Inst_eFPGA.Tile_X1Y9_LUT4AB 210.04000000000002 901.0399999999993 N
-Inst_eFPGA.Tile_X1Y10_LUT4AB 210.04000000000002 670.7799999999993 N
-Inst_eFPGA.Tile_X1Y11_LUT4AB 210.04000000000002 440.5199999999993 N
-Inst_eFPGA.Tile_X1Y12_LUT4AB 210.04000000000002 210.2599999999993 N
-Inst_eFPGA.Tile_X1Y13_S_term_single 210.04000000000002 149.99999999999932 N
-Inst_eFPGA.Tile_X2Y0_N_term_single 440.14 2973.38 N
-Inst_eFPGA.Tile_X2Y1_LUT4AB 440.14 2743.12 N
-Inst_eFPGA.Tile_X2Y2_LUT4AB 440.14 2512.8599999999997 N
-Inst_eFPGA.Tile_X2Y3_LUT4AB 440.14 2282.5999999999995 N
-Inst_eFPGA.Tile_X2Y4_LUT4AB 440.14 2052.3399999999992 N
-Inst_eFPGA.Tile_X2Y5_LUT4AB 440.14 1822.0799999999992 N
-Inst_eFPGA.Tile_X2Y6_LUT4AB 440.14 1591.8199999999993 N
-Inst_eFPGA.Tile_X2Y7_LUT4AB 440.14 1361.5599999999993 N
-Inst_eFPGA.Tile_X2Y8_LUT4AB 440.14 1131.2999999999993 N
-Inst_eFPGA.Tile_X2Y9_LUT4AB 440.14 901.0399999999993 N
-Inst_eFPGA.Tile_X2Y10_LUT4AB 440.14 670.7799999999993 N
-Inst_eFPGA.Tile_X2Y11_LUT4AB 440.14 440.5199999999993 N
-Inst_eFPGA.Tile_X2Y12_LUT4AB 440.14 210.2599999999993 N
-Inst_eFPGA.Tile_X2Y13_S_term_single 440.14 149.99999999999932 N
-Inst_eFPGA.Tile_X3Y0_N_term_single2 670.24 2973.38 N
-Inst_eFPGA.Tile_X3Y1_RegFile 670.24 2743.12 N
-Inst_eFPGA.Tile_X3Y2_RegFile 670.24 2512.8599999999997 N
-Inst_eFPGA.Tile_X3Y3_RegFile 670.24 2282.5999999999995 N
-Inst_eFPGA.Tile_X3Y4_RegFile 670.24 2052.3399999999992 N
-Inst_eFPGA.Tile_X3Y5_RegFile 670.24 1822.0799999999992 N
-Inst_eFPGA.Tile_X3Y6_RegFile 670.24 1591.8199999999993 N
-Inst_eFPGA.Tile_X3Y7_RegFile 670.24 1361.5599999999993 N
-Inst_eFPGA.Tile_X3Y8_RegFile 670.24 1131.2999999999993 N
-Inst_eFPGA.Tile_X3Y9_RegFile 670.24 901.0399999999993 N
-Inst_eFPGA.Tile_X3Y10_RegFile 670.24 670.7799999999993 N
-Inst_eFPGA.Tile_X3Y11_RegFile 670.24 440.5199999999993 N
-Inst_eFPGA.Tile_X3Y12_RegFile 670.24 210.2599999999993 N
-Inst_eFPGA.Tile_X3Y13_S_term_single2 670.24 149.99999999999932 N
-Inst_eFPGA.Tile_X4Y0_N_term_single 900.34 2973.38 N
-Inst_eFPGA.Tile_X4Y1_LUT4AB 900.34 2743.12 N
-Inst_eFPGA.Tile_X4Y2_LUT4AB 900.34 2512.8599999999997 N
-Inst_eFPGA.Tile_X4Y3_LUT4AB 900.34 2282.5999999999995 N
-Inst_eFPGA.Tile_X4Y4_LUT4AB 900.34 2052.3399999999992 N
-Inst_eFPGA.Tile_X4Y5_LUT4AB 900.34 1822.0799999999992 N
-Inst_eFPGA.Tile_X4Y6_LUT4AB 900.34 1591.8199999999993 N
-Inst_eFPGA.Tile_X4Y7_LUT4AB 900.34 1361.5599999999993 N
-Inst_eFPGA.Tile_X4Y8_LUT4AB 900.34 1131.2999999999993 N
-Inst_eFPGA.Tile_X4Y9_LUT4AB 900.34 901.0399999999993 N
-Inst_eFPGA.Tile_X4Y10_LUT4AB 900.34 670.7799999999993 N
-Inst_eFPGA.Tile_X4Y11_LUT4AB 900.34 440.5199999999993 N
-Inst_eFPGA.Tile_X4Y12_LUT4AB 900.34 210.2599999999993 N
-Inst_eFPGA.Tile_X4Y13_S_term_single 900.34 149.99999999999932 N
-Inst_eFPGA.Tile_X5Y0_N_term_single 1130.44 2973.38 N
-Inst_eFPGA.Tile_X5Y1_LUT4AB 1130.44 2743.12 N
-Inst_eFPGA.Tile_X5Y2_LUT4AB 1130.44 2512.8599999999997 N
-Inst_eFPGA.Tile_X5Y3_LUT4AB 1130.44 2282.5999999999995 N
-Inst_eFPGA.Tile_X5Y4_LUT4AB 1130.44 2052.3399999999992 N
-Inst_eFPGA.Tile_X5Y5_LUT4AB 1130.44 1822.0799999999992 N
-Inst_eFPGA.Tile_X5Y6_LUT4AB 1130.44 1591.8199999999993 N
-Inst_eFPGA.Tile_X5Y7_LUT4AB 1130.44 1361.5599999999993 N
-Inst_eFPGA.Tile_X5Y8_LUT4AB 1130.44 1131.2999999999993 N
-Inst_eFPGA.Tile_X5Y9_LUT4AB 1130.44 901.0399999999993 N
-Inst_eFPGA.Tile_X5Y10_LUT4AB 1130.44 670.7799999999993 N
-Inst_eFPGA.Tile_X5Y11_LUT4AB 1130.44 440.5199999999993 N
-Inst_eFPGA.Tile_X5Y12_LUT4AB 1130.44 210.2599999999993 N
-Inst_eFPGA.Tile_X5Y13_S_term_single 1130.44 149.99999999999932 N
-Inst_eFPGA.Tile_X6Y0_N_term_DSP 1360.54 2973.38 N
-Inst_eFPGA.Tile_X6Y1_X6Y2_DSP_tile 1360.54 2512.8599999999997 N
-Inst_eFPGA.Tile_X6Y3_X6Y4_DSP_tile 1360.54 2052.3399999999992 N
-Inst_eFPGA.Tile_X6Y5_X6Y6_DSP_tile 1360.54 1591.8199999999993 N
-Inst_eFPGA.Tile_X6Y7_X6Y8_DSP_tile 1360.54 1131.2999999999993 N
-Inst_eFPGA.Tile_X6Y9_X6Y10_DSP_tile 1360.54 670.7799999999993 N
-Inst_eFPGA.Tile_X6Y11_X6Y12_DSP_tile 1360.54 210.2599999999993 N
-Inst_eFPGA.Tile_X6Y13_S_term_DSP 1360.54 149.99999999999932 N
-Inst_eFPGA.Tile_X7Y0_N_term_single 1590.6399999999999 2973.38 N
-Inst_eFPGA.Tile_X7Y1_LUT4AB 1590.6399999999999 2743.12 N
-Inst_eFPGA.Tile_X7Y2_LUT4AB 1590.6399999999999 2512.8599999999997 N
-Inst_eFPGA.Tile_X7Y3_LUT4AB 1590.6399999999999 2282.5999999999995 N
-Inst_eFPGA.Tile_X7Y4_LUT4AB 1590.6399999999999 2052.3399999999992 N
-Inst_eFPGA.Tile_X7Y5_LUT4AB 1590.6399999999999 1822.0799999999992 N
-Inst_eFPGA.Tile_X7Y6_LUT4AB 1590.6399999999999 1591.8199999999993 N
-Inst_eFPGA.Tile_X7Y7_LUT4AB 1590.6399999999999 1361.5599999999993 N
-Inst_eFPGA.Tile_X7Y8_LUT4AB 1590.6399999999999 1131.2999999999993 N
-Inst_eFPGA.Tile_X7Y9_LUT4AB 1590.6399999999999 901.0399999999993 N
-Inst_eFPGA.Tile_X7Y10_LUT4AB 1590.6399999999999 670.7799999999993 N
-Inst_eFPGA.Tile_X7Y11_LUT4AB 1590.6399999999999 440.5199999999993 N
-Inst_eFPGA.Tile_X7Y12_LUT4AB 1590.6399999999999 210.2599999999993 N
-Inst_eFPGA.Tile_X7Y13_S_term_single 1590.6399999999999 149.99999999999932 N
-Inst_eFPGA.Tile_X8Y0_N_term_single 1820.7399999999998 2973.38 N
-Inst_eFPGA.Tile_X8Y1_LUT4AB 1820.7399999999998 2743.12 N
-Inst_eFPGA.Tile_X8Y2_LUT4AB 1820.7399999999998 2512.8599999999997 N
-Inst_eFPGA.Tile_X8Y3_LUT4AB 1820.7399999999998 2282.5999999999995 N
-Inst_eFPGA.Tile_X8Y4_LUT4AB 1820.7399999999998 2052.3399999999992 N
-Inst_eFPGA.Tile_X8Y5_LUT4AB 1820.7399999999998 1822.0799999999992 N
-Inst_eFPGA.Tile_X8Y6_LUT4AB 1820.7399999999998 1591.8199999999993 N
-Inst_eFPGA.Tile_X8Y7_LUT4AB 1820.7399999999998 1361.5599999999993 N
-Inst_eFPGA.Tile_X8Y8_LUT4AB 1820.7399999999998 1131.2999999999993 N
-Inst_eFPGA.Tile_X8Y9_LUT4AB 1820.7399999999998 901.0399999999993 N
-Inst_eFPGA.Tile_X8Y10_LUT4AB 1820.7399999999998 670.7799999999993 N
-Inst_eFPGA.Tile_X8Y11_LUT4AB 1820.7399999999998 440.5199999999993 N
-Inst_eFPGA.Tile_X8Y12_LUT4AB 1820.7399999999998 210.2599999999993 N
-Inst_eFPGA.Tile_X8Y13_S_term_single 1820.7399999999998 149.99999999999932 N
-Inst_eFPGA.Tile_X9Y0_N_term_RAM_IO 2050.84 2973.38 N
-Inst_eFPGA.Tile_X9Y1_RAM_IO 2050.84 2743.12 N
-Inst_eFPGA.Tile_X9Y2_RAM_IO 2050.84 2512.8599999999997 N
-Inst_eFPGA.Tile_X9Y3_RAM_IO 2050.84 2282.5999999999995 N
-Inst_eFPGA.Tile_X9Y4_RAM_IO 2050.84 2052.3399999999992 N
-Inst_eFPGA.Tile_X9Y5_RAM_IO 2050.84 1822.0799999999992 N
-Inst_eFPGA.Tile_X9Y6_RAM_IO 2050.84 1591.8199999999993 N
-Inst_eFPGA.Tile_X9Y7_RAM_IO 2050.84 1361.5599999999993 N
-Inst_eFPGA.Tile_X9Y8_RAM_IO 2050.84 1131.2999999999993 N
-Inst_eFPGA.Tile_X9Y9_RAM_IO 2050.84 901.0399999999993 N
-Inst_eFPGA.Tile_X9Y10_RAM_IO 2050.84 670.7799999999993 N
-Inst_eFPGA.Tile_X9Y11_RAM_IO 2050.84 440.5199999999993 N
-Inst_eFPGA.Tile_X9Y12_RAM_IO 2050.84 210.2599999999993 N
-Inst_eFPGA.Tile_X9Y13_S_term_RAM_IO 2050.84 149.99999999999932 N
-Inst_BlockRAM_5 2190.78 2512.8599999999997 N
-Inst_BlockRAM_4 2190.78 2052.3399999999992 N
-Inst_BlockRAM_3 2190.78 1591.8199999999993 N
-Inst_BlockRAM_2 2190.78 1131.2999999999993 N
-Inst_BlockRAM_1 2190.78 670.7799999999993 N
-Inst_BlockRAM_0 2190.78 210.2599999999993 N
diff --git a/openlane/user_project_wrapper/macros/placements/macro_placement.cfg.old b/openlane/user_project_wrapper/macros/placements/macro_placement.cfg.old
deleted file mode 100644
index dab5f89..0000000
--- a/openlane/user_project_wrapper/macros/placements/macro_placement.cfg.old
+++ /dev/null
@@ -1,138 +0,0 @@
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y1_W_IO 150 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y2_W_IO 150 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y3_W_IO 150 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y4_W_IO 150 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y5_W_IO 150 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y6_W_IO 150 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y7_W_IO 150 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y8_W_IO 150 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y9_W_IO 150 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y10_W_IO 150 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y11_W_IO 150 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X0Y12_W_IO 150 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y0_N_term_single 260.04 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y1_LUT4AB 260.04 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y2_LUT4AB 260.04 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y3_LUT4AB 260.04 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y4_LUT4AB 260.04 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y5_LUT4AB 260.04 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y6_LUT4AB 260.04 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y7_LUT4AB 260.04 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y8_LUT4AB 260.04 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y9_LUT4AB 260.04 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y10_LUT4AB 260.04 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_LUT4AB 260.04 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y12_LUT4AB 260.04 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X1Y13_S_term_single 260.04 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y0_N_term_single 490.14 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y1_LUT4AB 490.14 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y2_LUT4AB 490.14 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y3_LUT4AB 490.14 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y4_LUT4AB 490.14 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y5_LUT4AB 490.14 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y6_LUT4AB 490.14 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y7_LUT4AB 490.14 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y8_LUT4AB 490.14 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y9_LUT4AB 490.14 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y10_LUT4AB 490.14 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_LUT4AB 490.14 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y12_LUT4AB 490.14 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X2Y13_S_term_single 490.14 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y0_N_term_single2 720.24 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y1_RegFile 720.24 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y2_RegFile 720.24 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y3_RegFile 720.24 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y4_RegFile 720.24 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y5_RegFile 720.24 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y6_RegFile 720.24 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y7_RegFile 720.24 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y8_RegFile 720.24 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y9_RegFile 720.24 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_RegFile 720.24 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_RegFile 720.24 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y12_RegFile 720.24 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X3Y13_S_term_single2 720.24 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y0_N_term_single 950.34 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y1_LUT4AB 950.34 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y2_LUT4AB 950.34 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y3_LUT4AB 950.34 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y4_LUT4AB 950.34 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y5_LUT4AB 950.34 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y6_LUT4AB 950.34 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y7_LUT4AB 950.34 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y8_LUT4AB 950.34 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y9_LUT4AB 950.34 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y10_LUT4AB 950.34 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_LUT4AB 950.34 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y12_LUT4AB 950.34 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X4Y13_S_term_single 950.34 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y0_N_term_single 1180.4399999999998 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y1_LUT4AB 1180.4399999999998 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y2_LUT4AB 1180.4399999999998 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y3_LUT4AB 1180.4399999999998 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y4_LUT4AB 1180.4399999999998 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y5_LUT4AB 1180.4399999999998 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y6_LUT4AB 1180.4399999999998 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y7_LUT4AB 1180.4399999999998 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y8_LUT4AB 1180.4399999999998 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y9_LUT4AB 1180.4399999999998 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y10_LUT4AB 1180.4399999999998 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_LUT4AB 1180.4399999999998 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y12_LUT4AB 1180.4399999999998 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X5Y13_S_term_single 1180.4399999999998 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y0_N_term_DSP 1410.54 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y1_X6Y2_DSP_tile 1410.54 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y3_X6Y4_DSP_tile 1410.54 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y5_X6Y6_DSP_tile 1410.54 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y7_X6Y8_DSP_tile 1410.54 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y9_X6Y10_DSP_tile 1410.54 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_X6Y12_DSP_tile 1410.54 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X6Y13_S_term_DSP 1410.54 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y0_N_term_single 1640.6399999999999 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y1_LUT4AB 1640.6399999999999 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y2_LUT4AB 1640.6399999999999 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y3_LUT4AB 1640.6399999999999 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y4_LUT4AB 1640.6399999999999 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y5_LUT4AB 1640.6399999999999 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y6_LUT4AB 1640.6399999999999 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y7_LUT4AB 1640.6399999999999 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y8_LUT4AB 1640.6399999999999 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y9_LUT4AB 1640.6399999999999 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y10_LUT4AB 1640.6399999999999 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y11_LUT4AB 1640.6399999999999 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y12_LUT4AB 1640.6399999999999 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X7Y13_S_term_single 1640.6399999999999 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y0_N_term_single 1870.7399999999998 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y1_LUT4AB 1870.7399999999998 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y2_LUT4AB 1870.7399999999998 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y3_LUT4AB 1870.7399999999998 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y4_LUT4AB 1870.7399999999998 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y5_LUT4AB 1870.7399999999998 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y6_LUT4AB 1870.7399999999998 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y7_LUT4AB 1870.7399999999998 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y8_LUT4AB 1870.7399999999998 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y9_LUT4AB 1870.7399999999998 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y10_LUT4AB 1870.7399999999998 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_LUT4AB 1870.7399999999998 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y12_LUT4AB 1870.7399999999998 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X8Y13_S_term_single 1870.7399999999998 249.99999999999932 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y0_N_term_RAM_IO 2100.84 3073.38 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y1_RAM_IO 2100.84 2843.12 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y2_RAM_IO 2100.84 2612.8599999999997 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y3_RAM_IO 2100.84 2382.5999999999995 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y4_RAM_IO 2100.84 2152.3399999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y5_RAM_IO 2100.84 1922.0799999999992 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y6_RAM_IO 2100.84 1691.8199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y7_RAM_IO 2100.84 1461.5599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y8_RAM_IO 2100.84 1231.2999999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y9_RAM_IO 2100.84 1001.0399999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_RAM_IO 2100.84 770.7799999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_RAM_IO 2100.84 540.5199999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y12_RAM_IO 2100.84 310.2599999999993 N
-inst_eFPGA_top.Inst_eFPGA.Tile_X9Y13_S_term_RAM_IO 2100.84 249.99999999999932 N
-inst_eFPGA_top.Inst_BlockRAM_5 2240.78 2612.8599999999997 N
-inst_eFPGA_top.Inst_BlockRAM_4 2240.78 2152.3399999999992 N
-inst_eFPGA_top.Inst_BlockRAM_3 2240.78 1691.8199999999993 N
-inst_eFPGA_top.Inst_BlockRAM_2 2240.78 1231.2999999999993 N
-inst_eFPGA_top.Inst_BlockRAM_1 2240.78 770.7799999999993 N
-inst_eFPGA_top.Inst_BlockRAM_0 2240.78 310.2599999999993 N
diff --git a/openlane/user_project_wrapper/macros/update_lefgds.csh b/openlane/user_project_wrapper/macros/update_lefgds.csh
deleted file mode 100755
index 2b5260b..0000000
--- a/openlane/user_project_wrapper/macros/update_lefgds.csh
+++ /dev/null
@@ -1,35 +0,0 @@
-#!/bin/csh
-#cp ~/SKY130/eFPGA_v2/Innovus/BRAM_v3/OUTPUTs/BRAM.lef lef/
-cp ~/SKY130/eFPGA_v2/Innovus/BRAM_v31/OUTPUTs/BRAM.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/LUT4AB/runs/std_mux4/results/magic/LUT4AB.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/DSP/runs/std_mux4/results/magic/DSP.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_DSP/runs/std_mux4/results/magic/N_term_DSP.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_RAM_IO/runs/std_mux4/results/magic/N_term_RAM_IO.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_single/runs/std_mux4/results/magic/N_term_single.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_single2/runs/std_mux4/results/magic/N_term_single2.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/RAM_IO/runs/std_mux4/results/magic/RAM_IO.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/RegFile/runs/std_mux4/results/magic/RegFile.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_DSP/runs/std_mux4/results/magic/S_term_DSP.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_RAM_IO/runs/std_mux4/results/magic/S_term_RAM_IO.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_single/runs/std_mux4/results/magic/S_term_single.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_single2/runs/std_mux4/results/magic/S_term_single2.lef lef/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/W_IO/runs/std_mux4/results/magic/W_IO.lef lef/
-cp ~/SKY130/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.lef ./lef
-
-#cp ~/SKY130/eFPGA_v2/Innovus/BRAM_v3/OUTPUTs/BRAM.gds gds/
-cp ~/SKY130/eFPGA_v2/Innovus/BRAM_v31/OUTPUTs/BRAM.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/LUT4AB/runs/std_mux4/results/magic/LUT4AB.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/DSP/runs/std_mux4/results/magic/DSP.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_DSP/runs/std_mux4/results/magic/N_term_DSP.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_RAM_IO/runs/std_mux4/results/magic/N_term_RAM_IO.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_single/runs/std_mux4/results/magic/N_term_single.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/N_term_single2/runs/std_mux4/results/magic/N_term_single2.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/RAM_IO/runs/std_mux4/results/magic/RAM_IO.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/RegFile/runs/std_mux4/results/magic/RegFile.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_DSP/runs/std_mux4/results/magic/S_term_DSP.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_RAM_IO/runs/std_mux4/results/magic/S_term_RAM_IO.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_single/runs/std_mux4/results/magic/S_term_single.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/S_term_single2/runs/std_mux4/results/magic/S_term_single2.gds gds/
-cp ~/SKY130/gg-mpw3-2021/OpenLane/designs/W_IO/runs/std_mux4/results/magic/W_IO.gds gds/
-cp ~/SKY130/sky130_sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8/sky130_sram_2kbyte_1rw1r_32x512_8.gds ./gds
-
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 0ec9438..1f744e9 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module user_project_wrapper (user_clock2,
     vccd1,
     vccd2,
@@ -180016,6 +180033,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y2_FAB2RAM_D3_O2 ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y2_FAB2RAM_D3_O3 }));
  W_IO \inst_eFPGA_top.Inst_eFPGA.Tile_X0Y10_W_IO  (.A_I_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y10_A_I_top ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .A_T_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y10_A_T_top ),
     .A_O_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y10_A_O_top ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y11_UserCLKo ),
@@ -180232,6 +180250,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y10_WW4BEG[0] }));
  W_IO \inst_eFPGA_top.Inst_eFPGA.Tile_X0Y11_W_IO  (.A_I_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y11_A_I_top ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .A_T_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y11_A_T_top ),
     .A_O_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y11_A_O_top ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y12_UserCLKo ),
@@ -180448,6 +180467,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_WW4BEG[0] }));
  W_IO \inst_eFPGA_top.Inst_eFPGA.Tile_X0Y12_W_IO  (.A_I_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y12_A_I_top ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .A_T_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y12_A_T_top ),
     .A_O_top(\inst_eFPGA_top.Inst_eFPGA.Tile_X0Y12_A_O_top ),
     .UserCLK(\clknet_leaf_10_inst_eFPGA_top.CLK ),
@@ -182765,6 +182785,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y0_SS4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y10_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y10_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y10_UserCLKo ),
@@ -183273,6 +183294,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y10_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y12_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y12_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y11_UserCLKo ),
@@ -183781,6 +183803,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X1Y12_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y12_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y13_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y13_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X1Y12_UserCLKo ),
@@ -189166,6 +189189,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y0_SS4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y10_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y10_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y10_UserCLKo ),
@@ -189674,6 +189698,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y12_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y12_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y11_UserCLKo ),
@@ -190182,6 +190207,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X2Y12_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y12_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y13_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y13_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X2Y12_UserCLKo ),
@@ -195566,6 +195592,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y0_SS4BEG[0] }));
  RegFile \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_RegFile  (.UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_UserCLKo ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_UserCLKo ),
     .E1BEG({\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_E1BEG[3] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y10_E1BEG[2] ,
@@ -196072,6 +196099,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y10_WW4BEG[0] }));
  RegFile \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_RegFile  (.UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y12_UserCLKo ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_UserCLKo ),
     .E1BEG({\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_E1BEG[3] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y11_E1BEG[2] ,
@@ -196578,6 +196606,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_WW4BEG[0] }));
  RegFile \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y12_RegFile  (.UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y13_UserCLKo ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y12_UserCLKo ),
     .E1BEG({\inst_eFPGA_top.Inst_eFPGA.Tile_X3Y12_E1BEG[3] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X3Y12_E1BEG[2] ,
@@ -201942,6 +201971,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y0_SS4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y10_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y10_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y10_UserCLKo ),
@@ -202450,6 +202480,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y10_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y12_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y12_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y11_UserCLKo ),
@@ -202958,6 +202989,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X4Y12_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y12_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y13_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y13_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X4Y12_UserCLKo ),
@@ -208343,6 +208375,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y0_SS4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y10_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y10_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y10_UserCLKo ),
@@ -208851,6 +208884,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y10_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y12_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y12_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y11_UserCLKo ),
@@ -209359,6 +209393,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X5Y12_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y12_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y13_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y13_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X5Y12_UserCLKo ),
@@ -214743,6 +214778,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y0_SS4BEG[0] }));
  DSP \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_X6Y12_DSP_tile  (.UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X6Y13_UserCLKo ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_UserCLKo ),
     .FrameStrobe({\inst_eFPGA_top.Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[19] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y13_FrameStrobe_O[18] ,
@@ -219614,6 +219650,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y0_SS4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y10_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y10_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y11_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y11_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y10_UserCLKo ),
@@ -220122,6 +220159,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y10_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y11_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y11_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y12_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y12_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y11_UserCLKo ),
@@ -220630,6 +220668,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y12_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y12_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y13_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y13_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X7Y12_UserCLKo ),
@@ -226015,6 +226054,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y0_SS4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y0_SS4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y10_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y10_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y10_UserCLKo ),
@@ -226523,6 +226563,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y12_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y12_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y11_UserCLKo ),
@@ -227031,6 +227072,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_WW4BEG[0] }));
  LUT4AB \inst_eFPGA_top.Inst_eFPGA.Tile_X8Y12_LUT4AB  (.Co(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y12_Co ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .Ci(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y13_Co ),
     .UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y13_UserCLKo ),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X8Y12_UserCLKo ),
@@ -232383,6 +232425,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y0_S4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y0_S4BEG[0] }));
  RAM_IO \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_RAM_IO  (.RAM2FAB_D0_I0(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_RAM2FAB_D0_I0 ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .RAM2FAB_D0_I1(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_RAM2FAB_D0_I1 ),
     .RAM2FAB_D0_I2(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_RAM2FAB_D0_I2 ),
     .RAM2FAB_D0_I3(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_RAM2FAB_D0_I3 ),
@@ -232777,6 +232820,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y10_WW4BEG[0] }));
  RAM_IO \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_RAM_IO  (.RAM2FAB_D0_I0(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_RAM2FAB_D0_I0 ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .RAM2FAB_D0_I1(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_RAM2FAB_D0_I1 ),
     .RAM2FAB_D0_I2(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_RAM2FAB_D0_I2 ),
     .RAM2FAB_D0_I3(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_RAM2FAB_D0_I3 ),
@@ -233171,6 +233215,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y11_WW4BEG[0] }));
  RAM_IO \inst_eFPGA_top.Inst_eFPGA.Tile_X9Y12_RAM_IO  (.RAM2FAB_D0_I0(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y12_RAM2FAB_D0_I0 ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .RAM2FAB_D0_I1(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y12_RAM2FAB_D0_I1 ),
     .RAM2FAB_D0_I2(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y12_RAM2FAB_D0_I2 ),
     .RAM2FAB_D0_I3(\inst_eFPGA_top.Inst_eFPGA.Tile_X9Y12_RAM2FAB_D0_I3 ),
diff --git a/verilog/rtl/BB/BlockRAM_1KB.v b/verilog/rtl/BB/BlockRAM_1KB.v
index 0e227e3..4b1d2ee 100644
--- a/verilog/rtl/BB/BlockRAM_1KB.v
+++ b/verilog/rtl/BB/BlockRAM_1KB.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module BlockRAM_1KB (clk, rd_addr, rd_data, wr_addr, wr_data, C0, C1, C2, C3, C4, C5);
 
 	parameter READ_ADDRESS_MSB_FROM_DATALSB = 24; //default 24 means bits wr_data[25:24] will become bits [9:8] of read address
@@ -151,4 +168,4 @@
   input   csb1; // active low chip select
   input [ADDR_WIDTH-1:0]  addr1;
   output [DATA_WIDTH-1:0] dout1;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/BB/DSP_bot_tile.v b/verilog/rtl/BB/DSP_bot_tile.v
index 6c91cc0..739c0c2 100644
--- a/verilog/rtl/BB/DSP_bot_tile.v
+++ b/verilog/rtl/BB/DSP_bot_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module DSP_bot (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, bot2top, N1END, N2MID, N2END, N4END, NN4END, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, S1END, S2MID, S2END, S4END, SS4END, top2bot, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/DSP_tile.v b/verilog/rtl/BB/DSP_tile.v
index 34478d6..66496de 100644
--- a/verilog/rtl/BB/DSP_tile.v
+++ b/verilog/rtl/BB/DSP_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module DSP (top_N1BEG, top_N2BEG, top_N2BEGb, top_N4BEG, top_NN4BEG, top_S1END, top_S2MID, top_S2END, top_S4END, top_SS4END, top_E1BEG, top_E2BEG, top_E2BEGb, top_EE4BEG, top_E6BEG, top_E1END, top_E2MID, top_E2END, top_EE4END, top_E6END, top_W1BEG, top_W2BEG, top_W2BEGb, top_WW4BEG, top_W6BEG, top_W1END, top_W2MID, top_W2END, top_WW4END, top_W6END, bot_E1BEG, bot_E2BEG, bot_E2BEGb, bot_EE4BEG, bot_E6BEG, bot_E1END, bot_E2MID, bot_E2END, bot_EE4END, bot_E6END, bot_W1BEG, bot_W2BEG, bot_W2BEGb, bot_WW4BEG, bot_W6BEG, bot_W1END, bot_W2MID, bot_W2END, bot_WW4END, bot_W6END, bot_S1BEG, bot_S2BEG, bot_S2BEGb, bot_S4BEG, bot_SS4BEG, bot_N1END, bot_N2MID, bot_N2END, bot_N4END, bot_NN4END, UserCLK, UserCLKo, top_FrameData, top_FrameData_O, bot_FrameData, bot_FrameData_O, FrameStrobe, FrameStrobe_O);
 
 	parameter MaxFramesPerCol = 20;
@@ -241,4 +258,4 @@
 	.FrameStrobe_O(bot2top_FrameStrobe)
 	);
 	
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/BB/DSP_top_tile.v b/verilog/rtl/BB/DSP_top_tile.v
index e3def5b..2654c73 100644
--- a/verilog/rtl/BB/DSP_top_tile.v
+++ b/verilog/rtl/BB/DSP_top_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module DSP_top (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, N1END, N2MID, N2END, N4END, NN4END, bot2top, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, top2bot, S1END, S2MID, S2END, S4END, SS4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/LUT4AB_tile.v b/verilog/rtl/BB/LUT4AB_tile.v
index f52a40a..df481cf 100644
--- a/verilog/rtl/BB/LUT4AB_tile.v
+++ b/verilog/rtl/BB/LUT4AB_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module LUT4AB (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, Co, N1END, N2MID, N2END, N4END, NN4END, Ci, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, S1END, S2MID, S2END, S4END, SS4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/N_term_DSP_tile.v b/verilog/rtl/BB/N_term_DSP_tile.v
index b4a4bef..558ae7a 100644
--- a/verilog/rtl/BB/N_term_DSP_tile.v
+++ b/verilog/rtl/BB/N_term_DSP_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module N_term_DSP (N1END, N2MID, N2END, N4END, NN4END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/N_term_RAM_IO_tile.v b/verilog/rtl/BB/N_term_RAM_IO_tile.v
index 3b2d2ce..9cee014 100644
--- a/verilog/rtl/BB/N_term_RAM_IO_tile.v
+++ b/verilog/rtl/BB/N_term_RAM_IO_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module N_term_RAM_IO (N1END, N2MID, N2END, N4END, S1BEG, S2BEG, S2BEGb, S4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/N_term_single2_tile.v b/verilog/rtl/BB/N_term_single2_tile.v
index fe0333c..a6a8af7 100644
--- a/verilog/rtl/BB/N_term_single2_tile.v
+++ b/verilog/rtl/BB/N_term_single2_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module N_term_single2 (N1END, N2MID, N2END, N4END, NN4END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/N_term_single_tile.v b/verilog/rtl/BB/N_term_single_tile.v
index 343027e..3902c5a 100644
--- a/verilog/rtl/BB/N_term_single_tile.v
+++ b/verilog/rtl/BB/N_term_single_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module N_term_single (N1END, N2MID, N2END, N4END, NN4END, Ci, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/RAM_IO_tile.v b/verilog/rtl/BB/RAM_IO_tile.v
index a46ef26..90d6af1 100644
--- a/verilog/rtl/BB/RAM_IO_tile.v
+++ b/verilog/rtl/BB/RAM_IO_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module RAM_IO (N1BEG, N2BEG, N2BEGb, N4BEG, N1END, N2MID, N2END, N4END, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, S1END, S2MID, S2END, S4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, RAM2FAB_D0_I0, RAM2FAB_D0_I1, RAM2FAB_D0_I2, RAM2FAB_D0_I3, UserCLK, RAM2FAB_D1_I0, RAM2FAB_D1_I1, RAM2FAB_D1_I2, RAM2FAB_D1_I3, RAM2FAB_D2_I0, RAM2FAB_D2_I1, RAM2FAB_D2_I2, RAM2FAB_D2_I3, RAM2FAB_D3_I0, RAM2FAB_D3_I1, RAM2FAB_D3_I2, RAM2FAB_D3_I3, FAB2RAM_D0_O0, FAB2RAM_D0_O1, FAB2RAM_D0_O2, FAB2RAM_D0_O3, FAB2RAM_D1_O0, FAB2RAM_D1_O1, FAB2RAM_D1_O2, FAB2RAM_D1_O3, FAB2RAM_D2_O0, FAB2RAM_D2_O1, FAB2RAM_D2_O2, FAB2RAM_D2_O3, FAB2RAM_D3_O0, FAB2RAM_D3_O1, FAB2RAM_D3_O2, FAB2RAM_D3_O3, FAB2RAM_A0_O0, FAB2RAM_A0_O1, FAB2RAM_A0_O2, FAB2RAM_A0_O3, FAB2RAM_A1_O0, FAB2RAM_A1_O1, FAB2RAM_A1_O2, FAB2RAM_A1_O3, FAB2RAM_C_O0, FAB2RAM_C_O1, FAB2RAM_C_O2, FAB2RAM_C_O3, Config_accessC_bit0, Config_accessC_bit1, Config_accessC_bit2, Config_accessC_bit3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/RegFile_tile.v b/verilog/rtl/BB/RegFile_tile.v
index 23f7ebf..fd96fcb 100644
--- a/verilog/rtl/BB/RegFile_tile.v
+++ b/verilog/rtl/BB/RegFile_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module RegFile (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, N1END, N2MID, N2END, N4END, NN4END, E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, E1END, E2MID, E2END, EE4END, E6END, S1BEG, S2BEG, S2BEGb, S4BEG, SS4BEG, S1END, S2MID, S2END, S4END, SS4END, W1BEG, W2BEG, W2BEGb, WW4BEG, W6BEG, W1END, W2MID, W2END, WW4END, W6END, UserCLK, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/S_term_DSP_tile.v b/verilog/rtl/BB/S_term_DSP_tile.v
index c9c7aef..a6e5a5b 100644
--- a/verilog/rtl/BB/S_term_DSP_tile.v
+++ b/verilog/rtl/BB/S_term_DSP_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module S_term_DSP (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, S1END, S2MID, S2END, S4END, SS4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/S_term_RAM_IO_tile.v b/verilog/rtl/BB/S_term_RAM_IO_tile.v
index d1cda15..0ed57ce 100644
--- a/verilog/rtl/BB/S_term_RAM_IO_tile.v
+++ b/verilog/rtl/BB/S_term_RAM_IO_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module S_term_RAM_IO (N1BEG, N2BEG, N2BEGb, N4BEG, S1END, S2MID, S2END, S4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/S_term_single2_tile.v b/verilog/rtl/BB/S_term_single2_tile.v
index ba88725..a61ee8f 100644
--- a/verilog/rtl/BB/S_term_single2_tile.v
+++ b/verilog/rtl/BB/S_term_single2_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module S_term_single2 (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, S1END, S2MID, S2END, S4END, SS4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/S_term_single_tile.v b/verilog/rtl/BB/S_term_single_tile.v
index 67e7e6f..564a0f2 100644
--- a/verilog/rtl/BB/S_term_single_tile.v
+++ b/verilog/rtl/BB/S_term_single_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module S_term_single (N1BEG, N2BEG, N2BEGb, N4BEG, NN4BEG, Co, S1END, S2MID, S2END, S4END, SS4END, UserCLK, UserCLKo, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/W_IO_tile.v b/verilog/rtl/BB/W_IO_tile.v
index 94f3771..9c8e243 100644
--- a/verilog/rtl/BB/W_IO_tile.v
+++ b/verilog/rtl/BB/W_IO_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module W_IO (E1BEG, E2BEG, E2BEGb, EE4BEG, E6BEG, W1END, W2MID, W2END, WW4END, W6END, A_I_top, A_T_top, A_O_top, UserCLK, B_I_top, B_T_top, B_O_top, A_config_C_bit0, A_config_C_bit1, A_config_C_bit2, A_config_C_bit3, B_config_C_bit0, B_config_C_bit1, B_config_C_bit2, B_config_C_bit3, UserCLKo, FrameData, FrameData_O, FrameStrobe, FrameStrobe_O);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameBitsPerRow = 32;
diff --git a/verilog/rtl/BB/fabric_DSP_tile.v b/verilog/rtl/BB/fabric_DSP_tile.v
index 1452a8a..c0b9af7 100644
--- a/verilog/rtl/BB/fabric_DSP_tile.v
+++ b/verilog/rtl/BB/fabric_DSP_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 	//External IO ports exported directly from the corresponding tiles
 module eFPGA (Tile_X0Y1_A_I_top, Tile_X0Y1_A_T_top, Tile_X0Y1_A_O_top, UserCLK, Tile_X0Y1_B_I_top, Tile_X0Y1_B_T_top, Tile_X0Y1_B_O_top, Tile_X0Y1_A_config_C_bit0, Tile_X0Y1_A_config_C_bit1, Tile_X0Y1_A_config_C_bit2, Tile_X0Y1_A_config_C_bit3, Tile_X0Y1_B_config_C_bit0, Tile_X0Y1_B_config_C_bit1, Tile_X0Y1_B_config_C_bit2, Tile_X0Y1_B_config_C_bit3, Tile_X9Y1_RAM2FAB_D0_I0, Tile_X9Y1_RAM2FAB_D0_I1, Tile_X9Y1_RAM2FAB_D0_I2, Tile_X9Y1_RAM2FAB_D0_I3, Tile_X9Y1_RAM2FAB_D1_I0, Tile_X9Y1_RAM2FAB_D1_I1, Tile_X9Y1_RAM2FAB_D1_I2, Tile_X9Y1_RAM2FAB_D1_I3, Tile_X9Y1_RAM2FAB_D2_I0, Tile_X9Y1_RAM2FAB_D2_I1, Tile_X9Y1_RAM2FAB_D2_I2, Tile_X9Y1_RAM2FAB_D2_I3, Tile_X9Y1_RAM2FAB_D3_I0, Tile_X9Y1_RAM2FAB_D3_I1, Tile_X9Y1_RAM2FAB_D3_I2, Tile_X9Y1_RAM2FAB_D3_I3, Tile_X9Y1_FAB2RAM_D0_O0, Tile_X9Y1_FAB2RAM_D0_O1, Tile_X9Y1_FAB2RAM_D0_O2, Tile_X9Y1_FAB2RAM_D0_O3, Tile_X9Y1_FAB2RAM_D1_O0, Tile_X9Y1_FAB2RAM_D1_O1, Tile_X9Y1_FAB2RAM_D1_O2, Tile_X9Y1_FAB2RAM_D1_O3, Tile_X9Y1_FAB2RAM_D2_O0, Tile_X9Y1_FAB2RAM_D2_O1, Tile_X9Y1_FAB2RAM_D2_O2, Tile_X9Y1_FAB2RAM_D2_O3, Tile_X9Y1_FAB2RAM_D3_O0, Tile_X9Y1_FAB2RAM_D3_O1, Tile_X9Y1_FAB2RAM_D3_O2, Tile_X9Y1_FAB2RAM_D3_O3, Tile_X9Y1_FAB2RAM_A0_O0, Tile_X9Y1_FAB2RAM_A0_O1, Tile_X9Y1_FAB2RAM_A0_O2, Tile_X9Y1_FAB2RAM_A0_O3, Tile_X9Y1_FAB2RAM_A1_O0, Tile_X9Y1_FAB2RAM_A1_O1, Tile_X9Y1_FAB2RAM_A1_O2, Tile_X9Y1_FAB2RAM_A1_O3, Tile_X9Y1_FAB2RAM_C_O0, Tile_X9Y1_FAB2RAM_C_O1, Tile_X9Y1_FAB2RAM_C_O2, Tile_X9Y1_FAB2RAM_C_O3, Tile_X9Y1_Config_accessC_bit0, Tile_X9Y1_Config_accessC_bit1, Tile_X9Y1_Config_accessC_bit2, Tile_X9Y1_Config_accessC_bit3, Tile_X0Y2_A_I_top, Tile_X0Y2_A_T_top, Tile_X0Y2_A_O_top, Tile_X0Y2_B_I_top, Tile_X0Y2_B_T_top, Tile_X0Y2_B_O_top, Tile_X0Y2_A_config_C_bit0, Tile_X0Y2_A_config_C_bit1, Tile_X0Y2_A_config_C_bit2, Tile_X0Y2_A_config_C_bit3, Tile_X0Y2_B_config_C_bit0, Tile_X0Y2_B_config_C_bit1, Tile_X0Y2_B_config_C_bit2, Tile_X0Y2_B_config_C_bit3, Tile_X9Y2_RAM2FAB_D0_I0, Tile_X9Y2_RAM2FAB_D0_I1, Tile_X9Y2_RAM2FAB_D0_I2, Tile_X9Y2_RAM2FAB_D0_I3, Tile_X9Y2_RAM2FAB_D1_I0, Tile_X9Y2_RAM2FAB_D1_I1, Tile_X9Y2_RAM2FAB_D1_I2, Tile_X9Y2_RAM2FAB_D1_I3, Tile_X9Y2_RAM2FAB_D2_I0, Tile_X9Y2_RAM2FAB_D2_I1, Tile_X9Y2_RAM2FAB_D2_I2, Tile_X9Y2_RAM2FAB_D2_I3, Tile_X9Y2_RAM2FAB_D3_I0, Tile_X9Y2_RAM2FAB_D3_I1, Tile_X9Y2_RAM2FAB_D3_I2, Tile_X9Y2_RAM2FAB_D3_I3, Tile_X9Y2_FAB2RAM_D0_O0, Tile_X9Y2_FAB2RAM_D0_O1, Tile_X9Y2_FAB2RAM_D0_O2, Tile_X9Y2_FAB2RAM_D0_O3, Tile_X9Y2_FAB2RAM_D1_O0, Tile_X9Y2_FAB2RAM_D1_O1, Tile_X9Y2_FAB2RAM_D1_O2, Tile_X9Y2_FAB2RAM_D1_O3, Tile_X9Y2_FAB2RAM_D2_O0, Tile_X9Y2_FAB2RAM_D2_O1, Tile_X9Y2_FAB2RAM_D2_O2, Tile_X9Y2_FAB2RAM_D2_O3, Tile_X9Y2_FAB2RAM_D3_O0, Tile_X9Y2_FAB2RAM_D3_O1, Tile_X9Y2_FAB2RAM_D3_O2, Tile_X9Y2_FAB2RAM_D3_O3, Tile_X9Y2_FAB2RAM_A0_O0, Tile_X9Y2_FAB2RAM_A0_O1, Tile_X9Y2_FAB2RAM_A0_O2, Tile_X9Y2_FAB2RAM_A0_O3, Tile_X9Y2_FAB2RAM_A1_O0, Tile_X9Y2_FAB2RAM_A1_O1, Tile_X9Y2_FAB2RAM_A1_O2, Tile_X9Y2_FAB2RAM_A1_O3, Tile_X9Y2_FAB2RAM_C_O0, Tile_X9Y2_FAB2RAM_C_O1, Tile_X9Y2_FAB2RAM_C_O2, Tile_X9Y2_FAB2RAM_C_O3, Tile_X9Y2_Config_accessC_bit0, Tile_X9Y2_Config_accessC_bit1, Tile_X9Y2_Config_accessC_bit2, Tile_X9Y2_Config_accessC_bit3, Tile_X0Y3_A_I_top, Tile_X0Y3_A_T_top, Tile_X0Y3_A_O_top, Tile_X0Y3_B_I_top, Tile_X0Y3_B_T_top, Tile_X0Y3_B_O_top, Tile_X0Y3_A_config_C_bit0, Tile_X0Y3_A_config_C_bit1, Tile_X0Y3_A_config_C_bit2, Tile_X0Y3_A_config_C_bit3, Tile_X0Y3_B_config_C_bit0, Tile_X0Y3_B_config_C_bit1, Tile_X0Y3_B_config_C_bit2, Tile_X0Y3_B_config_C_bit3, Tile_X9Y3_RAM2FAB_D0_I0, Tile_X9Y3_RAM2FAB_D0_I1, Tile_X9Y3_RAM2FAB_D0_I2, Tile_X9Y3_RAM2FAB_D0_I3, Tile_X9Y3_RAM2FAB_D1_I0, Tile_X9Y3_RAM2FAB_D1_I1, Tile_X9Y3_RAM2FAB_D1_I2, Tile_X9Y3_RAM2FAB_D1_I3, Tile_X9Y3_RAM2FAB_D2_I0, Tile_X9Y3_RAM2FAB_D2_I1, Tile_X9Y3_RAM2FAB_D2_I2, Tile_X9Y3_RAM2FAB_D2_I3, Tile_X9Y3_RAM2FAB_D3_I0, Tile_X9Y3_RAM2FAB_D3_I1, Tile_X9Y3_RAM2FAB_D3_I2, Tile_X9Y3_RAM2FAB_D3_I3, Tile_X9Y3_FAB2RAM_D0_O0, Tile_X9Y3_FAB2RAM_D0_O1, Tile_X9Y3_FAB2RAM_D0_O2, Tile_X9Y3_FAB2RAM_D0_O3, Tile_X9Y3_FAB2RAM_D1_O0, Tile_X9Y3_FAB2RAM_D1_O1, Tile_X9Y3_FAB2RAM_D1_O2, Tile_X9Y3_FAB2RAM_D1_O3, Tile_X9Y3_FAB2RAM_D2_O0, Tile_X9Y3_FAB2RAM_D2_O1, Tile_X9Y3_FAB2RAM_D2_O2, Tile_X9Y3_FAB2RAM_D2_O3, Tile_X9Y3_FAB2RAM_D3_O0, Tile_X9Y3_FAB2RAM_D3_O1, Tile_X9Y3_FAB2RAM_D3_O2, Tile_X9Y3_FAB2RAM_D3_O3, Tile_X9Y3_FAB2RAM_A0_O0, Tile_X9Y3_FAB2RAM_A0_O1, Tile_X9Y3_FAB2RAM_A0_O2, Tile_X9Y3_FAB2RAM_A0_O3, Tile_X9Y3_FAB2RAM_A1_O0, Tile_X9Y3_FAB2RAM_A1_O1, Tile_X9Y3_FAB2RAM_A1_O2, Tile_X9Y3_FAB2RAM_A1_O3, Tile_X9Y3_FAB2RAM_C_O0, Tile_X9Y3_FAB2RAM_C_O1, Tile_X9Y3_FAB2RAM_C_O2, Tile_X9Y3_FAB2RAM_C_O3, Tile_X9Y3_Config_accessC_bit0, Tile_X9Y3_Config_accessC_bit1, Tile_X9Y3_Config_accessC_bit2, Tile_X9Y3_Config_accessC_bit3, Tile_X0Y4_A_I_top, Tile_X0Y4_A_T_top, Tile_X0Y4_A_O_top, Tile_X0Y4_B_I_top, Tile_X0Y4_B_T_top, Tile_X0Y4_B_O_top, Tile_X0Y4_A_config_C_bit0, Tile_X0Y4_A_config_C_bit1, Tile_X0Y4_A_config_C_bit2, Tile_X0Y4_A_config_C_bit3, Tile_X0Y4_B_config_C_bit0, Tile_X0Y4_B_config_C_bit1, Tile_X0Y4_B_config_C_bit2, Tile_X0Y4_B_config_C_bit3, Tile_X9Y4_RAM2FAB_D0_I0, Tile_X9Y4_RAM2FAB_D0_I1, Tile_X9Y4_RAM2FAB_D0_I2, Tile_X9Y4_RAM2FAB_D0_I3, Tile_X9Y4_RAM2FAB_D1_I0, Tile_X9Y4_RAM2FAB_D1_I1, Tile_X9Y4_RAM2FAB_D1_I2, Tile_X9Y4_RAM2FAB_D1_I3, Tile_X9Y4_RAM2FAB_D2_I0, Tile_X9Y4_RAM2FAB_D2_I1, Tile_X9Y4_RAM2FAB_D2_I2, Tile_X9Y4_RAM2FAB_D2_I3, Tile_X9Y4_RAM2FAB_D3_I0, Tile_X9Y4_RAM2FAB_D3_I1, Tile_X9Y4_RAM2FAB_D3_I2, Tile_X9Y4_RAM2FAB_D3_I3, Tile_X9Y4_FAB2RAM_D0_O0, Tile_X9Y4_FAB2RAM_D0_O1, Tile_X9Y4_FAB2RAM_D0_O2, Tile_X9Y4_FAB2RAM_D0_O3, Tile_X9Y4_FAB2RAM_D1_O0, Tile_X9Y4_FAB2RAM_D1_O1, Tile_X9Y4_FAB2RAM_D1_O2, Tile_X9Y4_FAB2RAM_D1_O3, Tile_X9Y4_FAB2RAM_D2_O0, Tile_X9Y4_FAB2RAM_D2_O1, Tile_X9Y4_FAB2RAM_D2_O2, Tile_X9Y4_FAB2RAM_D2_O3, Tile_X9Y4_FAB2RAM_D3_O0, Tile_X9Y4_FAB2RAM_D3_O1, Tile_X9Y4_FAB2RAM_D3_O2, Tile_X9Y4_FAB2RAM_D3_O3, Tile_X9Y4_FAB2RAM_A0_O0, Tile_X9Y4_FAB2RAM_A0_O1, Tile_X9Y4_FAB2RAM_A0_O2, Tile_X9Y4_FAB2RAM_A0_O3, Tile_X9Y4_FAB2RAM_A1_O0, Tile_X9Y4_FAB2RAM_A1_O1, Tile_X9Y4_FAB2RAM_A1_O2, Tile_X9Y4_FAB2RAM_A1_O3, Tile_X9Y4_FAB2RAM_C_O0, Tile_X9Y4_FAB2RAM_C_O1, Tile_X9Y4_FAB2RAM_C_O2, Tile_X9Y4_FAB2RAM_C_O3, Tile_X9Y4_Config_accessC_bit0, Tile_X9Y4_Config_accessC_bit1, Tile_X9Y4_Config_accessC_bit2, Tile_X9Y4_Config_accessC_bit3, Tile_X0Y5_A_I_top, Tile_X0Y5_A_T_top, Tile_X0Y5_A_O_top, Tile_X0Y5_B_I_top, Tile_X0Y5_B_T_top, Tile_X0Y5_B_O_top, Tile_X0Y5_A_config_C_bit0, Tile_X0Y5_A_config_C_bit1, Tile_X0Y5_A_config_C_bit2, Tile_X0Y5_A_config_C_bit3, Tile_X0Y5_B_config_C_bit0, Tile_X0Y5_B_config_C_bit1, Tile_X0Y5_B_config_C_bit2, Tile_X0Y5_B_config_C_bit3, Tile_X9Y5_RAM2FAB_D0_I0, Tile_X9Y5_RAM2FAB_D0_I1, Tile_X9Y5_RAM2FAB_D0_I2, Tile_X9Y5_RAM2FAB_D0_I3, Tile_X9Y5_RAM2FAB_D1_I0, Tile_X9Y5_RAM2FAB_D1_I1, Tile_X9Y5_RAM2FAB_D1_I2, Tile_X9Y5_RAM2FAB_D1_I3, Tile_X9Y5_RAM2FAB_D2_I0, Tile_X9Y5_RAM2FAB_D2_I1, Tile_X9Y5_RAM2FAB_D2_I2, Tile_X9Y5_RAM2FAB_D2_I3, Tile_X9Y5_RAM2FAB_D3_I0, Tile_X9Y5_RAM2FAB_D3_I1, Tile_X9Y5_RAM2FAB_D3_I2, Tile_X9Y5_RAM2FAB_D3_I3, Tile_X9Y5_FAB2RAM_D0_O0, Tile_X9Y5_FAB2RAM_D0_O1, Tile_X9Y5_FAB2RAM_D0_O2, Tile_X9Y5_FAB2RAM_D0_O3, Tile_X9Y5_FAB2RAM_D1_O0, Tile_X9Y5_FAB2RAM_D1_O1, Tile_X9Y5_FAB2RAM_D1_O2, Tile_X9Y5_FAB2RAM_D1_O3, Tile_X9Y5_FAB2RAM_D2_O0, Tile_X9Y5_FAB2RAM_D2_O1, Tile_X9Y5_FAB2RAM_D2_O2, Tile_X9Y5_FAB2RAM_D2_O3, Tile_X9Y5_FAB2RAM_D3_O0, Tile_X9Y5_FAB2RAM_D3_O1, Tile_X9Y5_FAB2RAM_D3_O2, Tile_X9Y5_FAB2RAM_D3_O3, Tile_X9Y5_FAB2RAM_A0_O0, Tile_X9Y5_FAB2RAM_A0_O1, Tile_X9Y5_FAB2RAM_A0_O2, Tile_X9Y5_FAB2RAM_A0_O3, Tile_X9Y5_FAB2RAM_A1_O0, Tile_X9Y5_FAB2RAM_A1_O1, Tile_X9Y5_FAB2RAM_A1_O2, Tile_X9Y5_FAB2RAM_A1_O3, Tile_X9Y5_FAB2RAM_C_O0, Tile_X9Y5_FAB2RAM_C_O1, Tile_X9Y5_FAB2RAM_C_O2, Tile_X9Y5_FAB2RAM_C_O3, Tile_X9Y5_Config_accessC_bit0, Tile_X9Y5_Config_accessC_bit1, Tile_X9Y5_Config_accessC_bit2, Tile_X9Y5_Config_accessC_bit3, Tile_X0Y6_A_I_top, Tile_X0Y6_A_T_top, Tile_X0Y6_A_O_top, Tile_X0Y6_B_I_top, Tile_X0Y6_B_T_top, Tile_X0Y6_B_O_top, Tile_X0Y6_A_config_C_bit0, Tile_X0Y6_A_config_C_bit1, Tile_X0Y6_A_config_C_bit2, Tile_X0Y6_A_config_C_bit3, Tile_X0Y6_B_config_C_bit0, Tile_X0Y6_B_config_C_bit1, Tile_X0Y6_B_config_C_bit2, Tile_X0Y6_B_config_C_bit3, Tile_X9Y6_RAM2FAB_D0_I0, Tile_X9Y6_RAM2FAB_D0_I1, Tile_X9Y6_RAM2FAB_D0_I2, Tile_X9Y6_RAM2FAB_D0_I3, Tile_X9Y6_RAM2FAB_D1_I0, Tile_X9Y6_RAM2FAB_D1_I1, Tile_X9Y6_RAM2FAB_D1_I2, Tile_X9Y6_RAM2FAB_D1_I3, Tile_X9Y6_RAM2FAB_D2_I0, Tile_X9Y6_RAM2FAB_D2_I1, Tile_X9Y6_RAM2FAB_D2_I2, Tile_X9Y6_RAM2FAB_D2_I3, Tile_X9Y6_RAM2FAB_D3_I0, Tile_X9Y6_RAM2FAB_D3_I1, Tile_X9Y6_RAM2FAB_D3_I2, Tile_X9Y6_RAM2FAB_D3_I3, Tile_X9Y6_FAB2RAM_D0_O0, Tile_X9Y6_FAB2RAM_D0_O1, Tile_X9Y6_FAB2RAM_D0_O2, Tile_X9Y6_FAB2RAM_D0_O3, Tile_X9Y6_FAB2RAM_D1_O0, Tile_X9Y6_FAB2RAM_D1_O1, Tile_X9Y6_FAB2RAM_D1_O2, Tile_X9Y6_FAB2RAM_D1_O3, Tile_X9Y6_FAB2RAM_D2_O0, Tile_X9Y6_FAB2RAM_D2_O1, Tile_X9Y6_FAB2RAM_D2_O2, Tile_X9Y6_FAB2RAM_D2_O3, Tile_X9Y6_FAB2RAM_D3_O0, Tile_X9Y6_FAB2RAM_D3_O1, Tile_X9Y6_FAB2RAM_D3_O2, Tile_X9Y6_FAB2RAM_D3_O3, Tile_X9Y6_FAB2RAM_A0_O0, Tile_X9Y6_FAB2RAM_A0_O1, Tile_X9Y6_FAB2RAM_A0_O2, Tile_X9Y6_FAB2RAM_A0_O3, Tile_X9Y6_FAB2RAM_A1_O0, Tile_X9Y6_FAB2RAM_A1_O1, Tile_X9Y6_FAB2RAM_A1_O2, Tile_X9Y6_FAB2RAM_A1_O3, Tile_X9Y6_FAB2RAM_C_O0, Tile_X9Y6_FAB2RAM_C_O1, Tile_X9Y6_FAB2RAM_C_O2, Tile_X9Y6_FAB2RAM_C_O3, Tile_X9Y6_Config_accessC_bit0, Tile_X9Y6_Config_accessC_bit1, Tile_X9Y6_Config_accessC_bit2, Tile_X9Y6_Config_accessC_bit3, Tile_X0Y7_A_I_top, Tile_X0Y7_A_T_top, Tile_X0Y7_A_O_top, Tile_X0Y7_B_I_top, Tile_X0Y7_B_T_top, Tile_X0Y7_B_O_top, Tile_X0Y7_A_config_C_bit0, Tile_X0Y7_A_config_C_bit1, Tile_X0Y7_A_config_C_bit2, Tile_X0Y7_A_config_C_bit3, Tile_X0Y7_B_config_C_bit0, Tile_X0Y7_B_config_C_bit1, Tile_X0Y7_B_config_C_bit2, Tile_X0Y7_B_config_C_bit3, Tile_X9Y7_RAM2FAB_D0_I0, Tile_X9Y7_RAM2FAB_D0_I1, Tile_X9Y7_RAM2FAB_D0_I2, Tile_X9Y7_RAM2FAB_D0_I3, Tile_X9Y7_RAM2FAB_D1_I0, Tile_X9Y7_RAM2FAB_D1_I1, Tile_X9Y7_RAM2FAB_D1_I2, Tile_X9Y7_RAM2FAB_D1_I3, Tile_X9Y7_RAM2FAB_D2_I0, Tile_X9Y7_RAM2FAB_D2_I1, Tile_X9Y7_RAM2FAB_D2_I2, Tile_X9Y7_RAM2FAB_D2_I3, Tile_X9Y7_RAM2FAB_D3_I0, Tile_X9Y7_RAM2FAB_D3_I1, Tile_X9Y7_RAM2FAB_D3_I2, Tile_X9Y7_RAM2FAB_D3_I3, Tile_X9Y7_FAB2RAM_D0_O0, Tile_X9Y7_FAB2RAM_D0_O1, Tile_X9Y7_FAB2RAM_D0_O2, Tile_X9Y7_FAB2RAM_D0_O3, Tile_X9Y7_FAB2RAM_D1_O0, Tile_X9Y7_FAB2RAM_D1_O1, Tile_X9Y7_FAB2RAM_D1_O2, Tile_X9Y7_FAB2RAM_D1_O3, Tile_X9Y7_FAB2RAM_D2_O0, Tile_X9Y7_FAB2RAM_D2_O1, Tile_X9Y7_FAB2RAM_D2_O2, Tile_X9Y7_FAB2RAM_D2_O3, Tile_X9Y7_FAB2RAM_D3_O0, Tile_X9Y7_FAB2RAM_D3_O1, Tile_X9Y7_FAB2RAM_D3_O2, Tile_X9Y7_FAB2RAM_D3_O3, Tile_X9Y7_FAB2RAM_A0_O0, Tile_X9Y7_FAB2RAM_A0_O1, Tile_X9Y7_FAB2RAM_A0_O2, Tile_X9Y7_FAB2RAM_A0_O3, Tile_X9Y7_FAB2RAM_A1_O0, Tile_X9Y7_FAB2RAM_A1_O1, Tile_X9Y7_FAB2RAM_A1_O2, Tile_X9Y7_FAB2RAM_A1_O3, Tile_X9Y7_FAB2RAM_C_O0, Tile_X9Y7_FAB2RAM_C_O1, Tile_X9Y7_FAB2RAM_C_O2, Tile_X9Y7_FAB2RAM_C_O3, Tile_X9Y7_Config_accessC_bit0, Tile_X9Y7_Config_accessC_bit1, Tile_X9Y7_Config_accessC_bit2, Tile_X9Y7_Config_accessC_bit3, Tile_X0Y8_A_I_top, Tile_X0Y8_A_T_top, Tile_X0Y8_A_O_top, Tile_X0Y8_B_I_top, Tile_X0Y8_B_T_top, Tile_X0Y8_B_O_top, Tile_X0Y8_A_config_C_bit0, Tile_X0Y8_A_config_C_bit1, Tile_X0Y8_A_config_C_bit2, Tile_X0Y8_A_config_C_bit3, Tile_X0Y8_B_config_C_bit0, Tile_X0Y8_B_config_C_bit1, Tile_X0Y8_B_config_C_bit2, Tile_X0Y8_B_config_C_bit3, Tile_X9Y8_RAM2FAB_D0_I0, Tile_X9Y8_RAM2FAB_D0_I1, Tile_X9Y8_RAM2FAB_D0_I2, Tile_X9Y8_RAM2FAB_D0_I3, Tile_X9Y8_RAM2FAB_D1_I0, Tile_X9Y8_RAM2FAB_D1_I1, Tile_X9Y8_RAM2FAB_D1_I2, Tile_X9Y8_RAM2FAB_D1_I3, Tile_X9Y8_RAM2FAB_D2_I0, Tile_X9Y8_RAM2FAB_D2_I1, Tile_X9Y8_RAM2FAB_D2_I2, Tile_X9Y8_RAM2FAB_D2_I3, Tile_X9Y8_RAM2FAB_D3_I0, Tile_X9Y8_RAM2FAB_D3_I1, Tile_X9Y8_RAM2FAB_D3_I2, Tile_X9Y8_RAM2FAB_D3_I3, Tile_X9Y8_FAB2RAM_D0_O0, Tile_X9Y8_FAB2RAM_D0_O1, Tile_X9Y8_FAB2RAM_D0_O2, Tile_X9Y8_FAB2RAM_D0_O3, Tile_X9Y8_FAB2RAM_D1_O0, Tile_X9Y8_FAB2RAM_D1_O1, Tile_X9Y8_FAB2RAM_D1_O2, Tile_X9Y8_FAB2RAM_D1_O3, Tile_X9Y8_FAB2RAM_D2_O0, Tile_X9Y8_FAB2RAM_D2_O1, Tile_X9Y8_FAB2RAM_D2_O2, Tile_X9Y8_FAB2RAM_D2_O3, Tile_X9Y8_FAB2RAM_D3_O0, Tile_X9Y8_FAB2RAM_D3_O1, Tile_X9Y8_FAB2RAM_D3_O2, Tile_X9Y8_FAB2RAM_D3_O3, Tile_X9Y8_FAB2RAM_A0_O0, Tile_X9Y8_FAB2RAM_A0_O1, Tile_X9Y8_FAB2RAM_A0_O2, Tile_X9Y8_FAB2RAM_A0_O3, Tile_X9Y8_FAB2RAM_A1_O0, Tile_X9Y8_FAB2RAM_A1_O1, Tile_X9Y8_FAB2RAM_A1_O2, Tile_X9Y8_FAB2RAM_A1_O3, Tile_X9Y8_FAB2RAM_C_O0, Tile_X9Y8_FAB2RAM_C_O1, Tile_X9Y8_FAB2RAM_C_O2, Tile_X9Y8_FAB2RAM_C_O3, Tile_X9Y8_Config_accessC_bit0, Tile_X9Y8_Config_accessC_bit1, Tile_X9Y8_Config_accessC_bit2, Tile_X9Y8_Config_accessC_bit3, Tile_X0Y9_A_I_top, Tile_X0Y9_A_T_top, Tile_X0Y9_A_O_top, Tile_X0Y9_B_I_top, Tile_X0Y9_B_T_top, Tile_X0Y9_B_O_top, Tile_X0Y9_A_config_C_bit0, Tile_X0Y9_A_config_C_bit1, Tile_X0Y9_A_config_C_bit2, Tile_X0Y9_A_config_C_bit3, Tile_X0Y9_B_config_C_bit0, Tile_X0Y9_B_config_C_bit1, Tile_X0Y9_B_config_C_bit2, Tile_X0Y9_B_config_C_bit3, Tile_X9Y9_RAM2FAB_D0_I0, Tile_X9Y9_RAM2FAB_D0_I1, Tile_X9Y9_RAM2FAB_D0_I2, Tile_X9Y9_RAM2FAB_D0_I3, Tile_X9Y9_RAM2FAB_D1_I0, Tile_X9Y9_RAM2FAB_D1_I1, Tile_X9Y9_RAM2FAB_D1_I2, Tile_X9Y9_RAM2FAB_D1_I3, Tile_X9Y9_RAM2FAB_D2_I0, Tile_X9Y9_RAM2FAB_D2_I1, Tile_X9Y9_RAM2FAB_D2_I2, Tile_X9Y9_RAM2FAB_D2_I3, Tile_X9Y9_RAM2FAB_D3_I0, Tile_X9Y9_RAM2FAB_D3_I1, Tile_X9Y9_RAM2FAB_D3_I2, Tile_X9Y9_RAM2FAB_D3_I3, Tile_X9Y9_FAB2RAM_D0_O0, Tile_X9Y9_FAB2RAM_D0_O1, Tile_X9Y9_FAB2RAM_D0_O2, Tile_X9Y9_FAB2RAM_D0_O3, Tile_X9Y9_FAB2RAM_D1_O0, Tile_X9Y9_FAB2RAM_D1_O1, Tile_X9Y9_FAB2RAM_D1_O2, Tile_X9Y9_FAB2RAM_D1_O3, Tile_X9Y9_FAB2RAM_D2_O0, Tile_X9Y9_FAB2RAM_D2_O1, Tile_X9Y9_FAB2RAM_D2_O2, Tile_X9Y9_FAB2RAM_D2_O3, Tile_X9Y9_FAB2RAM_D3_O0, Tile_X9Y9_FAB2RAM_D3_O1, Tile_X9Y9_FAB2RAM_D3_O2, Tile_X9Y9_FAB2RAM_D3_O3, Tile_X9Y9_FAB2RAM_A0_O0, Tile_X9Y9_FAB2RAM_A0_O1, Tile_X9Y9_FAB2RAM_A0_O2, Tile_X9Y9_FAB2RAM_A0_O3, Tile_X9Y9_FAB2RAM_A1_O0, Tile_X9Y9_FAB2RAM_A1_O1, Tile_X9Y9_FAB2RAM_A1_O2, Tile_X9Y9_FAB2RAM_A1_O3, Tile_X9Y9_FAB2RAM_C_O0, Tile_X9Y9_FAB2RAM_C_O1, Tile_X9Y9_FAB2RAM_C_O2, Tile_X9Y9_FAB2RAM_C_O3, Tile_X9Y9_Config_accessC_bit0, Tile_X9Y9_Config_accessC_bit1, Tile_X9Y9_Config_accessC_bit2, Tile_X9Y9_Config_accessC_bit3, Tile_X0Y10_A_I_top, Tile_X0Y10_A_T_top, Tile_X0Y10_A_O_top, Tile_X0Y10_B_I_top, Tile_X0Y10_B_T_top, Tile_X0Y10_B_O_top, Tile_X0Y10_A_config_C_bit0, Tile_X0Y10_A_config_C_bit1, Tile_X0Y10_A_config_C_bit2, Tile_X0Y10_A_config_C_bit3, Tile_X0Y10_B_config_C_bit0, Tile_X0Y10_B_config_C_bit1, Tile_X0Y10_B_config_C_bit2, Tile_X0Y10_B_config_C_bit3, Tile_X9Y10_RAM2FAB_D0_I0, Tile_X9Y10_RAM2FAB_D0_I1, Tile_X9Y10_RAM2FAB_D0_I2, Tile_X9Y10_RAM2FAB_D0_I3, Tile_X9Y10_RAM2FAB_D1_I0, Tile_X9Y10_RAM2FAB_D1_I1, Tile_X9Y10_RAM2FAB_D1_I2, Tile_X9Y10_RAM2FAB_D1_I3, Tile_X9Y10_RAM2FAB_D2_I0, Tile_X9Y10_RAM2FAB_D2_I1, Tile_X9Y10_RAM2FAB_D2_I2, Tile_X9Y10_RAM2FAB_D2_I3, Tile_X9Y10_RAM2FAB_D3_I0, Tile_X9Y10_RAM2FAB_D3_I1, Tile_X9Y10_RAM2FAB_D3_I2, Tile_X9Y10_RAM2FAB_D3_I3, Tile_X9Y10_FAB2RAM_D0_O0, Tile_X9Y10_FAB2RAM_D0_O1, Tile_X9Y10_FAB2RAM_D0_O2, Tile_X9Y10_FAB2RAM_D0_O3, Tile_X9Y10_FAB2RAM_D1_O0, Tile_X9Y10_FAB2RAM_D1_O1, Tile_X9Y10_FAB2RAM_D1_O2, Tile_X9Y10_FAB2RAM_D1_O3, Tile_X9Y10_FAB2RAM_D2_O0, Tile_X9Y10_FAB2RAM_D2_O1, Tile_X9Y10_FAB2RAM_D2_O2, Tile_X9Y10_FAB2RAM_D2_O3, Tile_X9Y10_FAB2RAM_D3_O0, Tile_X9Y10_FAB2RAM_D3_O1, Tile_X9Y10_FAB2RAM_D3_O2, Tile_X9Y10_FAB2RAM_D3_O3, Tile_X9Y10_FAB2RAM_A0_O0, Tile_X9Y10_FAB2RAM_A0_O1, Tile_X9Y10_FAB2RAM_A0_O2, Tile_X9Y10_FAB2RAM_A0_O3, Tile_X9Y10_FAB2RAM_A1_O0, Tile_X9Y10_FAB2RAM_A1_O1, Tile_X9Y10_FAB2RAM_A1_O2, Tile_X9Y10_FAB2RAM_A1_O3, Tile_X9Y10_FAB2RAM_C_O0, Tile_X9Y10_FAB2RAM_C_O1, Tile_X9Y10_FAB2RAM_C_O2, Tile_X9Y10_FAB2RAM_C_O3, Tile_X9Y10_Config_accessC_bit0, Tile_X9Y10_Config_accessC_bit1, Tile_X9Y10_Config_accessC_bit2, Tile_X9Y10_Config_accessC_bit3, Tile_X0Y11_A_I_top, Tile_X0Y11_A_T_top, Tile_X0Y11_A_O_top, Tile_X0Y11_B_I_top, Tile_X0Y11_B_T_top, Tile_X0Y11_B_O_top, Tile_X0Y11_A_config_C_bit0, Tile_X0Y11_A_config_C_bit1, Tile_X0Y11_A_config_C_bit2, Tile_X0Y11_A_config_C_bit3, Tile_X0Y11_B_config_C_bit0, Tile_X0Y11_B_config_C_bit1, Tile_X0Y11_B_config_C_bit2, Tile_X0Y11_B_config_C_bit3, Tile_X9Y11_RAM2FAB_D0_I0, Tile_X9Y11_RAM2FAB_D0_I1, Tile_X9Y11_RAM2FAB_D0_I2, Tile_X9Y11_RAM2FAB_D0_I3, Tile_X9Y11_RAM2FAB_D1_I0, Tile_X9Y11_RAM2FAB_D1_I1, Tile_X9Y11_RAM2FAB_D1_I2, Tile_X9Y11_RAM2FAB_D1_I3, Tile_X9Y11_RAM2FAB_D2_I0, Tile_X9Y11_RAM2FAB_D2_I1, Tile_X9Y11_RAM2FAB_D2_I2, Tile_X9Y11_RAM2FAB_D2_I3, Tile_X9Y11_RAM2FAB_D3_I0, Tile_X9Y11_RAM2FAB_D3_I1, Tile_X9Y11_RAM2FAB_D3_I2, Tile_X9Y11_RAM2FAB_D3_I3, Tile_X9Y11_FAB2RAM_D0_O0, Tile_X9Y11_FAB2RAM_D0_O1, Tile_X9Y11_FAB2RAM_D0_O2, Tile_X9Y11_FAB2RAM_D0_O3, Tile_X9Y11_FAB2RAM_D1_O0, Tile_X9Y11_FAB2RAM_D1_O1, Tile_X9Y11_FAB2RAM_D1_O2, Tile_X9Y11_FAB2RAM_D1_O3, Tile_X9Y11_FAB2RAM_D2_O0, Tile_X9Y11_FAB2RAM_D2_O1, Tile_X9Y11_FAB2RAM_D2_O2, Tile_X9Y11_FAB2RAM_D2_O3, Tile_X9Y11_FAB2RAM_D3_O0, Tile_X9Y11_FAB2RAM_D3_O1, Tile_X9Y11_FAB2RAM_D3_O2, Tile_X9Y11_FAB2RAM_D3_O3, Tile_X9Y11_FAB2RAM_A0_O0, Tile_X9Y11_FAB2RAM_A0_O1, Tile_X9Y11_FAB2RAM_A0_O2, Tile_X9Y11_FAB2RAM_A0_O3, Tile_X9Y11_FAB2RAM_A1_O0, Tile_X9Y11_FAB2RAM_A1_O1, Tile_X9Y11_FAB2RAM_A1_O2, Tile_X9Y11_FAB2RAM_A1_O3, Tile_X9Y11_FAB2RAM_C_O0, Tile_X9Y11_FAB2RAM_C_O1, Tile_X9Y11_FAB2RAM_C_O2, Tile_X9Y11_FAB2RAM_C_O3, Tile_X9Y11_Config_accessC_bit0, Tile_X9Y11_Config_accessC_bit1, Tile_X9Y11_Config_accessC_bit2, Tile_X9Y11_Config_accessC_bit3, Tile_X0Y12_A_I_top, Tile_X0Y12_A_T_top, Tile_X0Y12_A_O_top, Tile_X0Y12_B_I_top, Tile_X0Y12_B_T_top, Tile_X0Y12_B_O_top, Tile_X0Y12_A_config_C_bit0, Tile_X0Y12_A_config_C_bit1, Tile_X0Y12_A_config_C_bit2, Tile_X0Y12_A_config_C_bit3, Tile_X0Y12_B_config_C_bit0, Tile_X0Y12_B_config_C_bit1, Tile_X0Y12_B_config_C_bit2, Tile_X0Y12_B_config_C_bit3, Tile_X9Y12_RAM2FAB_D0_I0, Tile_X9Y12_RAM2FAB_D0_I1, Tile_X9Y12_RAM2FAB_D0_I2, Tile_X9Y12_RAM2FAB_D0_I3, Tile_X9Y12_RAM2FAB_D1_I0, Tile_X9Y12_RAM2FAB_D1_I1, Tile_X9Y12_RAM2FAB_D1_I2, Tile_X9Y12_RAM2FAB_D1_I3, Tile_X9Y12_RAM2FAB_D2_I0, Tile_X9Y12_RAM2FAB_D2_I1, Tile_X9Y12_RAM2FAB_D2_I2, Tile_X9Y12_RAM2FAB_D2_I3, Tile_X9Y12_RAM2FAB_D3_I0, Tile_X9Y12_RAM2FAB_D3_I1, Tile_X9Y12_RAM2FAB_D3_I2, Tile_X9Y12_RAM2FAB_D3_I3, Tile_X9Y12_FAB2RAM_D0_O0, Tile_X9Y12_FAB2RAM_D0_O1, Tile_X9Y12_FAB2RAM_D0_O2, Tile_X9Y12_FAB2RAM_D0_O3, Tile_X9Y12_FAB2RAM_D1_O0, Tile_X9Y12_FAB2RAM_D1_O1, Tile_X9Y12_FAB2RAM_D1_O2, Tile_X9Y12_FAB2RAM_D1_O3, Tile_X9Y12_FAB2RAM_D2_O0, Tile_X9Y12_FAB2RAM_D2_O1, Tile_X9Y12_FAB2RAM_D2_O2, Tile_X9Y12_FAB2RAM_D2_O3, Tile_X9Y12_FAB2RAM_D3_O0, Tile_X9Y12_FAB2RAM_D3_O1, Tile_X9Y12_FAB2RAM_D3_O2, Tile_X9Y12_FAB2RAM_D3_O3, Tile_X9Y12_FAB2RAM_A0_O0, Tile_X9Y12_FAB2RAM_A0_O1, Tile_X9Y12_FAB2RAM_A0_O2, Tile_X9Y12_FAB2RAM_A0_O3, Tile_X9Y12_FAB2RAM_A1_O0, Tile_X9Y12_FAB2RAM_A1_O1, Tile_X9Y12_FAB2RAM_A1_O2, Tile_X9Y12_FAB2RAM_A1_O3, Tile_X9Y12_FAB2RAM_C_O0, Tile_X9Y12_FAB2RAM_C_O1, Tile_X9Y12_FAB2RAM_C_O2, Tile_X9Y12_FAB2RAM_C_O3, Tile_X9Y12_Config_accessC_bit0, Tile_X9Y12_Config_accessC_bit1, Tile_X9Y12_Config_accessC_bit2, Tile_X9Y12_Config_accessC_bit3, FrameData, FrameStrobe);
 	parameter MaxFramesPerCol = 20;
diff --git a/verilog/rtl/Config.v b/verilog/rtl/Config.v
index 4d88493..eb9ec59 100644
--- a/verilog/rtl/Config.v
+++ b/verilog/rtl/Config.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module Config (CLK, Rx, ComActive, ReceiveLED, s_clk, s_data, SelfWriteData, SelfWriteStrobe, ConfigWriteData, ConfigWriteStrobe, FrameAddressRegister, LongFrameStrobe, RowSelect);
 	//parameter NumberOfRows = 16;
 	parameter RowSelectWidth = 5;
diff --git a/verilog/rtl/ConfigFSM.v b/verilog/rtl/ConfigFSM.v
index 35c40c6..ce48662 100644
--- a/verilog/rtl/ConfigFSM.v
+++ b/verilog/rtl/ConfigFSM.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module ConfigFSM (CLK, WriteData, WriteStrobe, Reset, FrameAddressRegister, LongFrameStrobe, RowSelect);
 	parameter NumberOfRows = 12;
 	parameter RowSelectWidth = 5;
diff --git a/verilog/rtl/Config_access.v b/verilog/rtl/Config_access.v
index 42b8e92..60bd154 100644
--- a/verilog/rtl/Config_access.v
+++ b/verilog/rtl/Config_access.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module Config_access (C_bit0, C_bit1, C_bit2, C_bit3, ConfigBits);
 	parameter NoConfigBits = 4;// has to be adjusted manually (we don't use an arithmetic parser for the value)
 	// Pin0
diff --git a/verilog/rtl/Frame_Data_Reg_Pack.v b/verilog/rtl/Frame_Data_Reg_Pack.v
index ae987bb..66eaf6b 100644
--- a/verilog/rtl/Frame_Data_Reg_Pack.v
+++ b/verilog/rtl/Frame_Data_Reg_Pack.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module Frame_Data_Reg_0 (FrameData_I, FrameData_O, RowSelect, CLK);
 	parameter FrameBitsPerRow = 32;
 	parameter RowSelectWidth = 5;
@@ -177,4 +194,3 @@
 			FrameData_O <= FrameData_I;
 	end//CLK
 endmodule
-
diff --git a/verilog/rtl/Frame_Select_Pack.v b/verilog/rtl/Frame_Select_Pack.v
index de9fc7c..59d6f0f 100644
--- a/verilog/rtl/Frame_Select_Pack.v
+++ b/verilog/rtl/Frame_Select_Pack.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module Frame_Select_0 (FrameStrobe_I, FrameStrobe_O, FrameSelect, FrameStrobe);
 	parameter MaxFramesPerCol = 20;
 	parameter FrameSelectWidth = 5;
@@ -177,4 +194,3 @@
 			FrameStrobe_O = 'd0;
 	end
 endmodule
-
diff --git a/verilog/rtl/bitbang.v b/verilog/rtl/bitbang.v
index d700b23..ee41099 100644
--- a/verilog/rtl/bitbang.v
+++ b/verilog/rtl/bitbang.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module bitbang (s_clk, s_data, strobe, data, active, clk);
 	localparam on_pattern = 16'hFAB1; 
 	localparam off_pattern = 16'hFAB0; 
@@ -76,4 +93,4 @@
 //    end if;
 //end process;
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/config_UART.v b/verilog/rtl/config_UART.v
index 43dded1..5c8135a 100644
--- a/verilog/rtl/config_UART.v
+++ b/verilog/rtl/config_UART.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 module config_UART #(
 	parameter Mode = 0, // [0:auto|1:hex|2:bin] auto selects between ASCII-Hex and binary mode and takes a bit more logic, 
 						// bin is for faster binary mode, but might not work on all machines/boards
@@ -413,4 +430,4 @@
 		end
 	end//CLK
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/verilog/rtl/eFPGA_v3_top_sky130.v b/verilog/rtl/eFPGA_v3_top_sky130.v
index 04d673f..35e739e 100644
--- a/verilog/rtl/eFPGA_v3_top_sky130.v
+++ b/verilog/rtl/eFPGA_v3_top_sky130.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 
 module eFPGA_top (
 	// Wishbone Slave ports (WB MI A)
diff --git a/verilog/rtl/fabric_DSP_tile.v b/verilog/rtl/fabric_DSP_tile.v
index 325d480..a892e47 100644
--- a/verilog/rtl/fabric_DSP_tile.v
+++ b/verilog/rtl/fabric_DSP_tile.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 	//External IO ports exported directly from the corresponding tiles
 module eFPGA (Tile_X0Y1_A_I_top, Tile_X0Y1_A_T_top, Tile_X0Y1_A_O_top, UserCLK, Tile_X0Y1_B_I_top, Tile_X0Y1_B_T_top, Tile_X0Y1_B_O_top, Tile_X0Y1_A_config_C_bit0, Tile_X0Y1_A_config_C_bit1, Tile_X0Y1_A_config_C_bit2, Tile_X0Y1_A_config_C_bit3, Tile_X0Y1_B_config_C_bit0, Tile_X0Y1_B_config_C_bit1, Tile_X0Y1_B_config_C_bit2, Tile_X0Y1_B_config_C_bit3, Tile_X9Y1_RAM2FAB_D0_I0, Tile_X9Y1_RAM2FAB_D0_I1, Tile_X9Y1_RAM2FAB_D0_I2, Tile_X9Y1_RAM2FAB_D0_I3, Tile_X9Y1_RAM2FAB_D1_I0, Tile_X9Y1_RAM2FAB_D1_I1, Tile_X9Y1_RAM2FAB_D1_I2, Tile_X9Y1_RAM2FAB_D1_I3, Tile_X9Y1_RAM2FAB_D2_I0, Tile_X9Y1_RAM2FAB_D2_I1, Tile_X9Y1_RAM2FAB_D2_I2, Tile_X9Y1_RAM2FAB_D2_I3, Tile_X9Y1_RAM2FAB_D3_I0, Tile_X9Y1_RAM2FAB_D3_I1, Tile_X9Y1_RAM2FAB_D3_I2, Tile_X9Y1_RAM2FAB_D3_I3, Tile_X9Y1_FAB2RAM_D0_O0, Tile_X9Y1_FAB2RAM_D0_O1, Tile_X9Y1_FAB2RAM_D0_O2, Tile_X9Y1_FAB2RAM_D0_O3, Tile_X9Y1_FAB2RAM_D1_O0, Tile_X9Y1_FAB2RAM_D1_O1, Tile_X9Y1_FAB2RAM_D1_O2, Tile_X9Y1_FAB2RAM_D1_O3, Tile_X9Y1_FAB2RAM_D2_O0, Tile_X9Y1_FAB2RAM_D2_O1, Tile_X9Y1_FAB2RAM_D2_O2, Tile_X9Y1_FAB2RAM_D2_O3, Tile_X9Y1_FAB2RAM_D3_O0, Tile_X9Y1_FAB2RAM_D3_O1, Tile_X9Y1_FAB2RAM_D3_O2, Tile_X9Y1_FAB2RAM_D3_O3, Tile_X9Y1_FAB2RAM_A0_O0, Tile_X9Y1_FAB2RAM_A0_O1, Tile_X9Y1_FAB2RAM_A0_O2, Tile_X9Y1_FAB2RAM_A0_O3, Tile_X9Y1_FAB2RAM_A1_O0, Tile_X9Y1_FAB2RAM_A1_O1, Tile_X9Y1_FAB2RAM_A1_O2, Tile_X9Y1_FAB2RAM_A1_O3, Tile_X9Y1_FAB2RAM_C_O0, Tile_X9Y1_FAB2RAM_C_O1, Tile_X9Y1_FAB2RAM_C_O2, Tile_X9Y1_FAB2RAM_C_O3, Tile_X9Y1_Config_accessC_bit0, Tile_X9Y1_Config_accessC_bit1, Tile_X9Y1_Config_accessC_bit2, Tile_X9Y1_Config_accessC_bit3, Tile_X0Y2_A_I_top, Tile_X0Y2_A_T_top, Tile_X0Y2_A_O_top, Tile_X0Y2_B_I_top, Tile_X0Y2_B_T_top, Tile_X0Y2_B_O_top, Tile_X0Y2_A_config_C_bit0, Tile_X0Y2_A_config_C_bit1, Tile_X0Y2_A_config_C_bit2, Tile_X0Y2_A_config_C_bit3, Tile_X0Y2_B_config_C_bit0, Tile_X0Y2_B_config_C_bit1, Tile_X0Y2_B_config_C_bit2, Tile_X0Y2_B_config_C_bit3, Tile_X9Y2_RAM2FAB_D0_I0, Tile_X9Y2_RAM2FAB_D0_I1, Tile_X9Y2_RAM2FAB_D0_I2, Tile_X9Y2_RAM2FAB_D0_I3, Tile_X9Y2_RAM2FAB_D1_I0, Tile_X9Y2_RAM2FAB_D1_I1, Tile_X9Y2_RAM2FAB_D1_I2, Tile_X9Y2_RAM2FAB_D1_I3, Tile_X9Y2_RAM2FAB_D2_I0, Tile_X9Y2_RAM2FAB_D2_I1, Tile_X9Y2_RAM2FAB_D2_I2, Tile_X9Y2_RAM2FAB_D2_I3, Tile_X9Y2_RAM2FAB_D3_I0, Tile_X9Y2_RAM2FAB_D3_I1, Tile_X9Y2_RAM2FAB_D3_I2, Tile_X9Y2_RAM2FAB_D3_I3, Tile_X9Y2_FAB2RAM_D0_O0, Tile_X9Y2_FAB2RAM_D0_O1, Tile_X9Y2_FAB2RAM_D0_O2, Tile_X9Y2_FAB2RAM_D0_O3, Tile_X9Y2_FAB2RAM_D1_O0, Tile_X9Y2_FAB2RAM_D1_O1, Tile_X9Y2_FAB2RAM_D1_O2, Tile_X9Y2_FAB2RAM_D1_O3, Tile_X9Y2_FAB2RAM_D2_O0, Tile_X9Y2_FAB2RAM_D2_O1, Tile_X9Y2_FAB2RAM_D2_O2, Tile_X9Y2_FAB2RAM_D2_O3, Tile_X9Y2_FAB2RAM_D3_O0, Tile_X9Y2_FAB2RAM_D3_O1, Tile_X9Y2_FAB2RAM_D3_O2, Tile_X9Y2_FAB2RAM_D3_O3, Tile_X9Y2_FAB2RAM_A0_O0, Tile_X9Y2_FAB2RAM_A0_O1, Tile_X9Y2_FAB2RAM_A0_O2, Tile_X9Y2_FAB2RAM_A0_O3, Tile_X9Y2_FAB2RAM_A1_O0, Tile_X9Y2_FAB2RAM_A1_O1, Tile_X9Y2_FAB2RAM_A1_O2, Tile_X9Y2_FAB2RAM_A1_O3, Tile_X9Y2_FAB2RAM_C_O0, Tile_X9Y2_FAB2RAM_C_O1, Tile_X9Y2_FAB2RAM_C_O2, Tile_X9Y2_FAB2RAM_C_O3, Tile_X9Y2_Config_accessC_bit0, Tile_X9Y2_Config_accessC_bit1, Tile_X9Y2_Config_accessC_bit2, Tile_X9Y2_Config_accessC_bit3, Tile_X0Y3_A_I_top, Tile_X0Y3_A_T_top, Tile_X0Y3_A_O_top, Tile_X0Y3_B_I_top, Tile_X0Y3_B_T_top, Tile_X0Y3_B_O_top, Tile_X0Y3_A_config_C_bit0, Tile_X0Y3_A_config_C_bit1, Tile_X0Y3_A_config_C_bit2, Tile_X0Y3_A_config_C_bit3, Tile_X0Y3_B_config_C_bit0, Tile_X0Y3_B_config_C_bit1, Tile_X0Y3_B_config_C_bit2, Tile_X0Y3_B_config_C_bit3, Tile_X9Y3_RAM2FAB_D0_I0, Tile_X9Y3_RAM2FAB_D0_I1, Tile_X9Y3_RAM2FAB_D0_I2, Tile_X9Y3_RAM2FAB_D0_I3, Tile_X9Y3_RAM2FAB_D1_I0, Tile_X9Y3_RAM2FAB_D1_I1, Tile_X9Y3_RAM2FAB_D1_I2, Tile_X9Y3_RAM2FAB_D1_I3, Tile_X9Y3_RAM2FAB_D2_I0, Tile_X9Y3_RAM2FAB_D2_I1, Tile_X9Y3_RAM2FAB_D2_I2, Tile_X9Y3_RAM2FAB_D2_I3, Tile_X9Y3_RAM2FAB_D3_I0, Tile_X9Y3_RAM2FAB_D3_I1, Tile_X9Y3_RAM2FAB_D3_I2, Tile_X9Y3_RAM2FAB_D3_I3, Tile_X9Y3_FAB2RAM_D0_O0, Tile_X9Y3_FAB2RAM_D0_O1, Tile_X9Y3_FAB2RAM_D0_O2, Tile_X9Y3_FAB2RAM_D0_O3, Tile_X9Y3_FAB2RAM_D1_O0, Tile_X9Y3_FAB2RAM_D1_O1, Tile_X9Y3_FAB2RAM_D1_O2, Tile_X9Y3_FAB2RAM_D1_O3, Tile_X9Y3_FAB2RAM_D2_O0, Tile_X9Y3_FAB2RAM_D2_O1, Tile_X9Y3_FAB2RAM_D2_O2, Tile_X9Y3_FAB2RAM_D2_O3, Tile_X9Y3_FAB2RAM_D3_O0, Tile_X9Y3_FAB2RAM_D3_O1, Tile_X9Y3_FAB2RAM_D3_O2, Tile_X9Y3_FAB2RAM_D3_O3, Tile_X9Y3_FAB2RAM_A0_O0, Tile_X9Y3_FAB2RAM_A0_O1, Tile_X9Y3_FAB2RAM_A0_O2, Tile_X9Y3_FAB2RAM_A0_O3, Tile_X9Y3_FAB2RAM_A1_O0, Tile_X9Y3_FAB2RAM_A1_O1, Tile_X9Y3_FAB2RAM_A1_O2, Tile_X9Y3_FAB2RAM_A1_O3, Tile_X9Y3_FAB2RAM_C_O0, Tile_X9Y3_FAB2RAM_C_O1, Tile_X9Y3_FAB2RAM_C_O2, Tile_X9Y3_FAB2RAM_C_O3, Tile_X9Y3_Config_accessC_bit0, Tile_X9Y3_Config_accessC_bit1, Tile_X9Y3_Config_accessC_bit2, Tile_X9Y3_Config_accessC_bit3, Tile_X0Y4_A_I_top, Tile_X0Y4_A_T_top, Tile_X0Y4_A_O_top, Tile_X0Y4_B_I_top, Tile_X0Y4_B_T_top, Tile_X0Y4_B_O_top, Tile_X0Y4_A_config_C_bit0, Tile_X0Y4_A_config_C_bit1, Tile_X0Y4_A_config_C_bit2, Tile_X0Y4_A_config_C_bit3, Tile_X0Y4_B_config_C_bit0, Tile_X0Y4_B_config_C_bit1, Tile_X0Y4_B_config_C_bit2, Tile_X0Y4_B_config_C_bit3, Tile_X9Y4_RAM2FAB_D0_I0, Tile_X9Y4_RAM2FAB_D0_I1, Tile_X9Y4_RAM2FAB_D0_I2, Tile_X9Y4_RAM2FAB_D0_I3, Tile_X9Y4_RAM2FAB_D1_I0, Tile_X9Y4_RAM2FAB_D1_I1, Tile_X9Y4_RAM2FAB_D1_I2, Tile_X9Y4_RAM2FAB_D1_I3, Tile_X9Y4_RAM2FAB_D2_I0, Tile_X9Y4_RAM2FAB_D2_I1, Tile_X9Y4_RAM2FAB_D2_I2, Tile_X9Y4_RAM2FAB_D2_I3, Tile_X9Y4_RAM2FAB_D3_I0, Tile_X9Y4_RAM2FAB_D3_I1, Tile_X9Y4_RAM2FAB_D3_I2, Tile_X9Y4_RAM2FAB_D3_I3, Tile_X9Y4_FAB2RAM_D0_O0, Tile_X9Y4_FAB2RAM_D0_O1, Tile_X9Y4_FAB2RAM_D0_O2, Tile_X9Y4_FAB2RAM_D0_O3, Tile_X9Y4_FAB2RAM_D1_O0, Tile_X9Y4_FAB2RAM_D1_O1, Tile_X9Y4_FAB2RAM_D1_O2, Tile_X9Y4_FAB2RAM_D1_O3, Tile_X9Y4_FAB2RAM_D2_O0, Tile_X9Y4_FAB2RAM_D2_O1, Tile_X9Y4_FAB2RAM_D2_O2, Tile_X9Y4_FAB2RAM_D2_O3, Tile_X9Y4_FAB2RAM_D3_O0, Tile_X9Y4_FAB2RAM_D3_O1, Tile_X9Y4_FAB2RAM_D3_O2, Tile_X9Y4_FAB2RAM_D3_O3, Tile_X9Y4_FAB2RAM_A0_O0, Tile_X9Y4_FAB2RAM_A0_O1, Tile_X9Y4_FAB2RAM_A0_O2, Tile_X9Y4_FAB2RAM_A0_O3, Tile_X9Y4_FAB2RAM_A1_O0, Tile_X9Y4_FAB2RAM_A1_O1, Tile_X9Y4_FAB2RAM_A1_O2, Tile_X9Y4_FAB2RAM_A1_O3, Tile_X9Y4_FAB2RAM_C_O0, Tile_X9Y4_FAB2RAM_C_O1, Tile_X9Y4_FAB2RAM_C_O2, Tile_X9Y4_FAB2RAM_C_O3, Tile_X9Y4_Config_accessC_bit0, Tile_X9Y4_Config_accessC_bit1, Tile_X9Y4_Config_accessC_bit2, Tile_X9Y4_Config_accessC_bit3, Tile_X0Y5_A_I_top, Tile_X0Y5_A_T_top, Tile_X0Y5_A_O_top, Tile_X0Y5_B_I_top, Tile_X0Y5_B_T_top, Tile_X0Y5_B_O_top, Tile_X0Y5_A_config_C_bit0, Tile_X0Y5_A_config_C_bit1, Tile_X0Y5_A_config_C_bit2, Tile_X0Y5_A_config_C_bit3, Tile_X0Y5_B_config_C_bit0, Tile_X0Y5_B_config_C_bit1, Tile_X0Y5_B_config_C_bit2, Tile_X0Y5_B_config_C_bit3, Tile_X9Y5_RAM2FAB_D0_I0, Tile_X9Y5_RAM2FAB_D0_I1, Tile_X9Y5_RAM2FAB_D0_I2, Tile_X9Y5_RAM2FAB_D0_I3, Tile_X9Y5_RAM2FAB_D1_I0, Tile_X9Y5_RAM2FAB_D1_I1, Tile_X9Y5_RAM2FAB_D1_I2, Tile_X9Y5_RAM2FAB_D1_I3, Tile_X9Y5_RAM2FAB_D2_I0, Tile_X9Y5_RAM2FAB_D2_I1, Tile_X9Y5_RAM2FAB_D2_I2, Tile_X9Y5_RAM2FAB_D2_I3, Tile_X9Y5_RAM2FAB_D3_I0, Tile_X9Y5_RAM2FAB_D3_I1, Tile_X9Y5_RAM2FAB_D3_I2, Tile_X9Y5_RAM2FAB_D3_I3, Tile_X9Y5_FAB2RAM_D0_O0, Tile_X9Y5_FAB2RAM_D0_O1, Tile_X9Y5_FAB2RAM_D0_O2, Tile_X9Y5_FAB2RAM_D0_O3, Tile_X9Y5_FAB2RAM_D1_O0, Tile_X9Y5_FAB2RAM_D1_O1, Tile_X9Y5_FAB2RAM_D1_O2, Tile_X9Y5_FAB2RAM_D1_O3, Tile_X9Y5_FAB2RAM_D2_O0, Tile_X9Y5_FAB2RAM_D2_O1, Tile_X9Y5_FAB2RAM_D2_O2, Tile_X9Y5_FAB2RAM_D2_O3, Tile_X9Y5_FAB2RAM_D3_O0, Tile_X9Y5_FAB2RAM_D3_O1, Tile_X9Y5_FAB2RAM_D3_O2, Tile_X9Y5_FAB2RAM_D3_O3, Tile_X9Y5_FAB2RAM_A0_O0, Tile_X9Y5_FAB2RAM_A0_O1, Tile_X9Y5_FAB2RAM_A0_O2, Tile_X9Y5_FAB2RAM_A0_O3, Tile_X9Y5_FAB2RAM_A1_O0, Tile_X9Y5_FAB2RAM_A1_O1, Tile_X9Y5_FAB2RAM_A1_O2, Tile_X9Y5_FAB2RAM_A1_O3, Tile_X9Y5_FAB2RAM_C_O0, Tile_X9Y5_FAB2RAM_C_O1, Tile_X9Y5_FAB2RAM_C_O2, Tile_X9Y5_FAB2RAM_C_O3, Tile_X9Y5_Config_accessC_bit0, Tile_X9Y5_Config_accessC_bit1, Tile_X9Y5_Config_accessC_bit2, Tile_X9Y5_Config_accessC_bit3, Tile_X0Y6_A_I_top, Tile_X0Y6_A_T_top, Tile_X0Y6_A_O_top, Tile_X0Y6_B_I_top, Tile_X0Y6_B_T_top, Tile_X0Y6_B_O_top, Tile_X0Y6_A_config_C_bit0, Tile_X0Y6_A_config_C_bit1, Tile_X0Y6_A_config_C_bit2, Tile_X0Y6_A_config_C_bit3, Tile_X0Y6_B_config_C_bit0, Tile_X0Y6_B_config_C_bit1, Tile_X0Y6_B_config_C_bit2, Tile_X0Y6_B_config_C_bit3, Tile_X9Y6_RAM2FAB_D0_I0, Tile_X9Y6_RAM2FAB_D0_I1, Tile_X9Y6_RAM2FAB_D0_I2, Tile_X9Y6_RAM2FAB_D0_I3, Tile_X9Y6_RAM2FAB_D1_I0, Tile_X9Y6_RAM2FAB_D1_I1, Tile_X9Y6_RAM2FAB_D1_I2, Tile_X9Y6_RAM2FAB_D1_I3, Tile_X9Y6_RAM2FAB_D2_I0, Tile_X9Y6_RAM2FAB_D2_I1, Tile_X9Y6_RAM2FAB_D2_I2, Tile_X9Y6_RAM2FAB_D2_I3, Tile_X9Y6_RAM2FAB_D3_I0, Tile_X9Y6_RAM2FAB_D3_I1, Tile_X9Y6_RAM2FAB_D3_I2, Tile_X9Y6_RAM2FAB_D3_I3, Tile_X9Y6_FAB2RAM_D0_O0, Tile_X9Y6_FAB2RAM_D0_O1, Tile_X9Y6_FAB2RAM_D0_O2, Tile_X9Y6_FAB2RAM_D0_O3, Tile_X9Y6_FAB2RAM_D1_O0, Tile_X9Y6_FAB2RAM_D1_O1, Tile_X9Y6_FAB2RAM_D1_O2, Tile_X9Y6_FAB2RAM_D1_O3, Tile_X9Y6_FAB2RAM_D2_O0, Tile_X9Y6_FAB2RAM_D2_O1, Tile_X9Y6_FAB2RAM_D2_O2, Tile_X9Y6_FAB2RAM_D2_O3, Tile_X9Y6_FAB2RAM_D3_O0, Tile_X9Y6_FAB2RAM_D3_O1, Tile_X9Y6_FAB2RAM_D3_O2, Tile_X9Y6_FAB2RAM_D3_O3, Tile_X9Y6_FAB2RAM_A0_O0, Tile_X9Y6_FAB2RAM_A0_O1, Tile_X9Y6_FAB2RAM_A0_O2, Tile_X9Y6_FAB2RAM_A0_O3, Tile_X9Y6_FAB2RAM_A1_O0, Tile_X9Y6_FAB2RAM_A1_O1, Tile_X9Y6_FAB2RAM_A1_O2, Tile_X9Y6_FAB2RAM_A1_O3, Tile_X9Y6_FAB2RAM_C_O0, Tile_X9Y6_FAB2RAM_C_O1, Tile_X9Y6_FAB2RAM_C_O2, Tile_X9Y6_FAB2RAM_C_O3, Tile_X9Y6_Config_accessC_bit0, Tile_X9Y6_Config_accessC_bit1, Tile_X9Y6_Config_accessC_bit2, Tile_X9Y6_Config_accessC_bit3, Tile_X0Y7_A_I_top, Tile_X0Y7_A_T_top, Tile_X0Y7_A_O_top, Tile_X0Y7_B_I_top, Tile_X0Y7_B_T_top, Tile_X0Y7_B_O_top, Tile_X0Y7_A_config_C_bit0, Tile_X0Y7_A_config_C_bit1, Tile_X0Y7_A_config_C_bit2, Tile_X0Y7_A_config_C_bit3, Tile_X0Y7_B_config_C_bit0, Tile_X0Y7_B_config_C_bit1, Tile_X0Y7_B_config_C_bit2, Tile_X0Y7_B_config_C_bit3, Tile_X9Y7_RAM2FAB_D0_I0, Tile_X9Y7_RAM2FAB_D0_I1, Tile_X9Y7_RAM2FAB_D0_I2, Tile_X9Y7_RAM2FAB_D0_I3, Tile_X9Y7_RAM2FAB_D1_I0, Tile_X9Y7_RAM2FAB_D1_I1, Tile_X9Y7_RAM2FAB_D1_I2, Tile_X9Y7_RAM2FAB_D1_I3, Tile_X9Y7_RAM2FAB_D2_I0, Tile_X9Y7_RAM2FAB_D2_I1, Tile_X9Y7_RAM2FAB_D2_I2, Tile_X9Y7_RAM2FAB_D2_I3, Tile_X9Y7_RAM2FAB_D3_I0, Tile_X9Y7_RAM2FAB_D3_I1, Tile_X9Y7_RAM2FAB_D3_I2, Tile_X9Y7_RAM2FAB_D3_I3, Tile_X9Y7_FAB2RAM_D0_O0, Tile_X9Y7_FAB2RAM_D0_O1, Tile_X9Y7_FAB2RAM_D0_O2, Tile_X9Y7_FAB2RAM_D0_O3, Tile_X9Y7_FAB2RAM_D1_O0, Tile_X9Y7_FAB2RAM_D1_O1, Tile_X9Y7_FAB2RAM_D1_O2, Tile_X9Y7_FAB2RAM_D1_O3, Tile_X9Y7_FAB2RAM_D2_O0, Tile_X9Y7_FAB2RAM_D2_O1, Tile_X9Y7_FAB2RAM_D2_O2, Tile_X9Y7_FAB2RAM_D2_O3, Tile_X9Y7_FAB2RAM_D3_O0, Tile_X9Y7_FAB2RAM_D3_O1, Tile_X9Y7_FAB2RAM_D3_O2, Tile_X9Y7_FAB2RAM_D3_O3, Tile_X9Y7_FAB2RAM_A0_O0, Tile_X9Y7_FAB2RAM_A0_O1, Tile_X9Y7_FAB2RAM_A0_O2, Tile_X9Y7_FAB2RAM_A0_O3, Tile_X9Y7_FAB2RAM_A1_O0, Tile_X9Y7_FAB2RAM_A1_O1, Tile_X9Y7_FAB2RAM_A1_O2, Tile_X9Y7_FAB2RAM_A1_O3, Tile_X9Y7_FAB2RAM_C_O0, Tile_X9Y7_FAB2RAM_C_O1, Tile_X9Y7_FAB2RAM_C_O2, Tile_X9Y7_FAB2RAM_C_O3, Tile_X9Y7_Config_accessC_bit0, Tile_X9Y7_Config_accessC_bit1, Tile_X9Y7_Config_accessC_bit2, Tile_X9Y7_Config_accessC_bit3, Tile_X0Y8_A_I_top, Tile_X0Y8_A_T_top, Tile_X0Y8_A_O_top, Tile_X0Y8_B_I_top, Tile_X0Y8_B_T_top, Tile_X0Y8_B_O_top, Tile_X0Y8_A_config_C_bit0, Tile_X0Y8_A_config_C_bit1, Tile_X0Y8_A_config_C_bit2, Tile_X0Y8_A_config_C_bit3, Tile_X0Y8_B_config_C_bit0, Tile_X0Y8_B_config_C_bit1, Tile_X0Y8_B_config_C_bit2, Tile_X0Y8_B_config_C_bit3, Tile_X9Y8_RAM2FAB_D0_I0, Tile_X9Y8_RAM2FAB_D0_I1, Tile_X9Y8_RAM2FAB_D0_I2, Tile_X9Y8_RAM2FAB_D0_I3, Tile_X9Y8_RAM2FAB_D1_I0, Tile_X9Y8_RAM2FAB_D1_I1, Tile_X9Y8_RAM2FAB_D1_I2, Tile_X9Y8_RAM2FAB_D1_I3, Tile_X9Y8_RAM2FAB_D2_I0, Tile_X9Y8_RAM2FAB_D2_I1, Tile_X9Y8_RAM2FAB_D2_I2, Tile_X9Y8_RAM2FAB_D2_I3, Tile_X9Y8_RAM2FAB_D3_I0, Tile_X9Y8_RAM2FAB_D3_I1, Tile_X9Y8_RAM2FAB_D3_I2, Tile_X9Y8_RAM2FAB_D3_I3, Tile_X9Y8_FAB2RAM_D0_O0, Tile_X9Y8_FAB2RAM_D0_O1, Tile_X9Y8_FAB2RAM_D0_O2, Tile_X9Y8_FAB2RAM_D0_O3, Tile_X9Y8_FAB2RAM_D1_O0, Tile_X9Y8_FAB2RAM_D1_O1, Tile_X9Y8_FAB2RAM_D1_O2, Tile_X9Y8_FAB2RAM_D1_O3, Tile_X9Y8_FAB2RAM_D2_O0, Tile_X9Y8_FAB2RAM_D2_O1, Tile_X9Y8_FAB2RAM_D2_O2, Tile_X9Y8_FAB2RAM_D2_O3, Tile_X9Y8_FAB2RAM_D3_O0, Tile_X9Y8_FAB2RAM_D3_O1, Tile_X9Y8_FAB2RAM_D3_O2, Tile_X9Y8_FAB2RAM_D3_O3, Tile_X9Y8_FAB2RAM_A0_O0, Tile_X9Y8_FAB2RAM_A0_O1, Tile_X9Y8_FAB2RAM_A0_O2, Tile_X9Y8_FAB2RAM_A0_O3, Tile_X9Y8_FAB2RAM_A1_O0, Tile_X9Y8_FAB2RAM_A1_O1, Tile_X9Y8_FAB2RAM_A1_O2, Tile_X9Y8_FAB2RAM_A1_O3, Tile_X9Y8_FAB2RAM_C_O0, Tile_X9Y8_FAB2RAM_C_O1, Tile_X9Y8_FAB2RAM_C_O2, Tile_X9Y8_FAB2RAM_C_O3, Tile_X9Y8_Config_accessC_bit0, Tile_X9Y8_Config_accessC_bit1, Tile_X9Y8_Config_accessC_bit2, Tile_X9Y8_Config_accessC_bit3, Tile_X0Y9_A_I_top, Tile_X0Y9_A_T_top, Tile_X0Y9_A_O_top, Tile_X0Y9_B_I_top, Tile_X0Y9_B_T_top, Tile_X0Y9_B_O_top, Tile_X0Y9_A_config_C_bit0, Tile_X0Y9_A_config_C_bit1, Tile_X0Y9_A_config_C_bit2, Tile_X0Y9_A_config_C_bit3, Tile_X0Y9_B_config_C_bit0, Tile_X0Y9_B_config_C_bit1, Tile_X0Y9_B_config_C_bit2, Tile_X0Y9_B_config_C_bit3, Tile_X9Y9_RAM2FAB_D0_I0, Tile_X9Y9_RAM2FAB_D0_I1, Tile_X9Y9_RAM2FAB_D0_I2, Tile_X9Y9_RAM2FAB_D0_I3, Tile_X9Y9_RAM2FAB_D1_I0, Tile_X9Y9_RAM2FAB_D1_I1, Tile_X9Y9_RAM2FAB_D1_I2, Tile_X9Y9_RAM2FAB_D1_I3, Tile_X9Y9_RAM2FAB_D2_I0, Tile_X9Y9_RAM2FAB_D2_I1, Tile_X9Y9_RAM2FAB_D2_I2, Tile_X9Y9_RAM2FAB_D2_I3, Tile_X9Y9_RAM2FAB_D3_I0, Tile_X9Y9_RAM2FAB_D3_I1, Tile_X9Y9_RAM2FAB_D3_I2, Tile_X9Y9_RAM2FAB_D3_I3, Tile_X9Y9_FAB2RAM_D0_O0, Tile_X9Y9_FAB2RAM_D0_O1, Tile_X9Y9_FAB2RAM_D0_O2, Tile_X9Y9_FAB2RAM_D0_O3, Tile_X9Y9_FAB2RAM_D1_O0, Tile_X9Y9_FAB2RAM_D1_O1, Tile_X9Y9_FAB2RAM_D1_O2, Tile_X9Y9_FAB2RAM_D1_O3, Tile_X9Y9_FAB2RAM_D2_O0, Tile_X9Y9_FAB2RAM_D2_O1, Tile_X9Y9_FAB2RAM_D2_O2, Tile_X9Y9_FAB2RAM_D2_O3, Tile_X9Y9_FAB2RAM_D3_O0, Tile_X9Y9_FAB2RAM_D3_O1, Tile_X9Y9_FAB2RAM_D3_O2, Tile_X9Y9_FAB2RAM_D3_O3, Tile_X9Y9_FAB2RAM_A0_O0, Tile_X9Y9_FAB2RAM_A0_O1, Tile_X9Y9_FAB2RAM_A0_O2, Tile_X9Y9_FAB2RAM_A0_O3, Tile_X9Y9_FAB2RAM_A1_O0, Tile_X9Y9_FAB2RAM_A1_O1, Tile_X9Y9_FAB2RAM_A1_O2, Tile_X9Y9_FAB2RAM_A1_O3, Tile_X9Y9_FAB2RAM_C_O0, Tile_X9Y9_FAB2RAM_C_O1, Tile_X9Y9_FAB2RAM_C_O2, Tile_X9Y9_FAB2RAM_C_O3, Tile_X9Y9_Config_accessC_bit0, Tile_X9Y9_Config_accessC_bit1, Tile_X9Y9_Config_accessC_bit2, Tile_X9Y9_Config_accessC_bit3, Tile_X0Y10_A_I_top, Tile_X0Y10_A_T_top, Tile_X0Y10_A_O_top, Tile_X0Y10_B_I_top, Tile_X0Y10_B_T_top, Tile_X0Y10_B_O_top, Tile_X0Y10_A_config_C_bit0, Tile_X0Y10_A_config_C_bit1, Tile_X0Y10_A_config_C_bit2, Tile_X0Y10_A_config_C_bit3, Tile_X0Y10_B_config_C_bit0, Tile_X0Y10_B_config_C_bit1, Tile_X0Y10_B_config_C_bit2, Tile_X0Y10_B_config_C_bit3, Tile_X9Y10_RAM2FAB_D0_I0, Tile_X9Y10_RAM2FAB_D0_I1, Tile_X9Y10_RAM2FAB_D0_I2, Tile_X9Y10_RAM2FAB_D0_I3, Tile_X9Y10_RAM2FAB_D1_I0, Tile_X9Y10_RAM2FAB_D1_I1, Tile_X9Y10_RAM2FAB_D1_I2, Tile_X9Y10_RAM2FAB_D1_I3, Tile_X9Y10_RAM2FAB_D2_I0, Tile_X9Y10_RAM2FAB_D2_I1, Tile_X9Y10_RAM2FAB_D2_I2, Tile_X9Y10_RAM2FAB_D2_I3, Tile_X9Y10_RAM2FAB_D3_I0, Tile_X9Y10_RAM2FAB_D3_I1, Tile_X9Y10_RAM2FAB_D3_I2, Tile_X9Y10_RAM2FAB_D3_I3, Tile_X9Y10_FAB2RAM_D0_O0, Tile_X9Y10_FAB2RAM_D0_O1, Tile_X9Y10_FAB2RAM_D0_O2, Tile_X9Y10_FAB2RAM_D0_O3, Tile_X9Y10_FAB2RAM_D1_O0, Tile_X9Y10_FAB2RAM_D1_O1, Tile_X9Y10_FAB2RAM_D1_O2, Tile_X9Y10_FAB2RAM_D1_O3, Tile_X9Y10_FAB2RAM_D2_O0, Tile_X9Y10_FAB2RAM_D2_O1, Tile_X9Y10_FAB2RAM_D2_O2, Tile_X9Y10_FAB2RAM_D2_O3, Tile_X9Y10_FAB2RAM_D3_O0, Tile_X9Y10_FAB2RAM_D3_O1, Tile_X9Y10_FAB2RAM_D3_O2, Tile_X9Y10_FAB2RAM_D3_O3, Tile_X9Y10_FAB2RAM_A0_O0, Tile_X9Y10_FAB2RAM_A0_O1, Tile_X9Y10_FAB2RAM_A0_O2, Tile_X9Y10_FAB2RAM_A0_O3, Tile_X9Y10_FAB2RAM_A1_O0, Tile_X9Y10_FAB2RAM_A1_O1, Tile_X9Y10_FAB2RAM_A1_O2, Tile_X9Y10_FAB2RAM_A1_O3, Tile_X9Y10_FAB2RAM_C_O0, Tile_X9Y10_FAB2RAM_C_O1, Tile_X9Y10_FAB2RAM_C_O2, Tile_X9Y10_FAB2RAM_C_O3, Tile_X9Y10_Config_accessC_bit0, Tile_X9Y10_Config_accessC_bit1, Tile_X9Y10_Config_accessC_bit2, Tile_X9Y10_Config_accessC_bit3, Tile_X0Y11_A_I_top, Tile_X0Y11_A_T_top, Tile_X0Y11_A_O_top, Tile_X0Y11_B_I_top, Tile_X0Y11_B_T_top, Tile_X0Y11_B_O_top, Tile_X0Y11_A_config_C_bit0, Tile_X0Y11_A_config_C_bit1, Tile_X0Y11_A_config_C_bit2, Tile_X0Y11_A_config_C_bit3, Tile_X0Y11_B_config_C_bit0, Tile_X0Y11_B_config_C_bit1, Tile_X0Y11_B_config_C_bit2, Tile_X0Y11_B_config_C_bit3, Tile_X9Y11_RAM2FAB_D0_I0, Tile_X9Y11_RAM2FAB_D0_I1, Tile_X9Y11_RAM2FAB_D0_I2, Tile_X9Y11_RAM2FAB_D0_I3, Tile_X9Y11_RAM2FAB_D1_I0, Tile_X9Y11_RAM2FAB_D1_I1, Tile_X9Y11_RAM2FAB_D1_I2, Tile_X9Y11_RAM2FAB_D1_I3, Tile_X9Y11_RAM2FAB_D2_I0, Tile_X9Y11_RAM2FAB_D2_I1, Tile_X9Y11_RAM2FAB_D2_I2, Tile_X9Y11_RAM2FAB_D2_I3, Tile_X9Y11_RAM2FAB_D3_I0, Tile_X9Y11_RAM2FAB_D3_I1, Tile_X9Y11_RAM2FAB_D3_I2, Tile_X9Y11_RAM2FAB_D3_I3, Tile_X9Y11_FAB2RAM_D0_O0, Tile_X9Y11_FAB2RAM_D0_O1, Tile_X9Y11_FAB2RAM_D0_O2, Tile_X9Y11_FAB2RAM_D0_O3, Tile_X9Y11_FAB2RAM_D1_O0, Tile_X9Y11_FAB2RAM_D1_O1, Tile_X9Y11_FAB2RAM_D1_O2, Tile_X9Y11_FAB2RAM_D1_O3, Tile_X9Y11_FAB2RAM_D2_O0, Tile_X9Y11_FAB2RAM_D2_O1, Tile_X9Y11_FAB2RAM_D2_O2, Tile_X9Y11_FAB2RAM_D2_O3, Tile_X9Y11_FAB2RAM_D3_O0, Tile_X9Y11_FAB2RAM_D3_O1, Tile_X9Y11_FAB2RAM_D3_O2, Tile_X9Y11_FAB2RAM_D3_O3, Tile_X9Y11_FAB2RAM_A0_O0, Tile_X9Y11_FAB2RAM_A0_O1, Tile_X9Y11_FAB2RAM_A0_O2, Tile_X9Y11_FAB2RAM_A0_O3, Tile_X9Y11_FAB2RAM_A1_O0, Tile_X9Y11_FAB2RAM_A1_O1, Tile_X9Y11_FAB2RAM_A1_O2, Tile_X9Y11_FAB2RAM_A1_O3, Tile_X9Y11_FAB2RAM_C_O0, Tile_X9Y11_FAB2RAM_C_O1, Tile_X9Y11_FAB2RAM_C_O2, Tile_X9Y11_FAB2RAM_C_O3, Tile_X9Y11_Config_accessC_bit0, Tile_X9Y11_Config_accessC_bit1, Tile_X9Y11_Config_accessC_bit2, Tile_X9Y11_Config_accessC_bit3, Tile_X0Y12_A_I_top, Tile_X0Y12_A_T_top, Tile_X0Y12_A_O_top, Tile_X0Y12_B_I_top, Tile_X0Y12_B_T_top, Tile_X0Y12_B_O_top, Tile_X0Y12_A_config_C_bit0, Tile_X0Y12_A_config_C_bit1, Tile_X0Y12_A_config_C_bit2, Tile_X0Y12_A_config_C_bit3, Tile_X0Y12_B_config_C_bit0, Tile_X0Y12_B_config_C_bit1, Tile_X0Y12_B_config_C_bit2, Tile_X0Y12_B_config_C_bit3, Tile_X9Y12_RAM2FAB_D0_I0, Tile_X9Y12_RAM2FAB_D0_I1, Tile_X9Y12_RAM2FAB_D0_I2, Tile_X9Y12_RAM2FAB_D0_I3, Tile_X9Y12_RAM2FAB_D1_I0, Tile_X9Y12_RAM2FAB_D1_I1, Tile_X9Y12_RAM2FAB_D1_I2, Tile_X9Y12_RAM2FAB_D1_I3, Tile_X9Y12_RAM2FAB_D2_I0, Tile_X9Y12_RAM2FAB_D2_I1, Tile_X9Y12_RAM2FAB_D2_I2, Tile_X9Y12_RAM2FAB_D2_I3, Tile_X9Y12_RAM2FAB_D3_I0, Tile_X9Y12_RAM2FAB_D3_I1, Tile_X9Y12_RAM2FAB_D3_I2, Tile_X9Y12_RAM2FAB_D3_I3, Tile_X9Y12_FAB2RAM_D0_O0, Tile_X9Y12_FAB2RAM_D0_O1, Tile_X9Y12_FAB2RAM_D0_O2, Tile_X9Y12_FAB2RAM_D0_O3, Tile_X9Y12_FAB2RAM_D1_O0, Tile_X9Y12_FAB2RAM_D1_O1, Tile_X9Y12_FAB2RAM_D1_O2, Tile_X9Y12_FAB2RAM_D1_O3, Tile_X9Y12_FAB2RAM_D2_O0, Tile_X9Y12_FAB2RAM_D2_O1, Tile_X9Y12_FAB2RAM_D2_O2, Tile_X9Y12_FAB2RAM_D2_O3, Tile_X9Y12_FAB2RAM_D3_O0, Tile_X9Y12_FAB2RAM_D3_O1, Tile_X9Y12_FAB2RAM_D3_O2, Tile_X9Y12_FAB2RAM_D3_O3, Tile_X9Y12_FAB2RAM_A0_O0, Tile_X9Y12_FAB2RAM_A0_O1, Tile_X9Y12_FAB2RAM_A0_O2, Tile_X9Y12_FAB2RAM_A0_O3, Tile_X9Y12_FAB2RAM_A1_O0, Tile_X9Y12_FAB2RAM_A1_O1, Tile_X9Y12_FAB2RAM_A1_O2, Tile_X9Y12_FAB2RAM_A1_O3, Tile_X9Y12_FAB2RAM_C_O0, Tile_X9Y12_FAB2RAM_C_O1, Tile_X9Y12_FAB2RAM_C_O2, Tile_X9Y12_FAB2RAM_C_O3, Tile_X9Y12_Config_accessC_bit0, Tile_X9Y12_Config_accessC_bit1, Tile_X9Y12_Config_accessC_bit2, Tile_X9Y12_Config_accessC_bit3, FrameData, FrameStrobe);
 	parameter MaxFramesPerCol = 20;
diff --git a/verilog/rtl/models_pack.v b/verilog/rtl/models_pack.v
index d5e3361..b59b074 100644
--- a/verilog/rtl/models_pack.v
+++ b/verilog/rtl/models_pack.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 // Models for the embedded FPGA fabric
 // LHD1 Latch area 11.76
 //`timescale 1ns/1ns
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 5711bc0..93bd762 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -1,3 +1,20 @@
+// SPDX-FileCopyrightText: 
+// 2022 Nguyen Dao
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+// SPDX-License-Identifier: Apache-2.0
+
 // SPDX-FileCopyrightText: 2020 Efabless Corporation
 //
 // Licensed under the Apache License, Version 2.0 (the "License");