diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 1f744e9..60111aa 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -218740,6 +218740,7 @@
     \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y7_WW4BEG[1] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X7Y7_WW4BEG[0] }));
  DSP \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y9_X6Y10_DSP_tile  (.UserCLK(\inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_UserCLKo ),
+	 .vccd1(vccd1), .vssd1(vssd1),
     .UserCLKo(\inst_eFPGA_top.Inst_eFPGA.Tile_X6Y9_UserCLKo ),
     .FrameStrobe({\inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[19] ,
     \inst_eFPGA_top.Inst_eFPGA.Tile_X6Y11_FrameStrobe_O[18] ,