)]}'
{
  "commit": "ea5ff7d937a3422c805b506215ae5242935638b2",
  "tree": "76d81ffcbd54654fb9857c795d14849d62e8d675",
  "parents": [
    "4afe80a9c6351d7ac4dd01538be61801a0e14d26"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Dec 18 10:44:16 2021 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sat Dec 18 10:44:16 2021 -0500"
  },
  "message": "Updated the layout to properly use the metal resistors in front of\npins that are connected to the same net.  Updated the GDS with this\nchange, and also to properly generate hierarchical layers, which\napparently had not been done previously.  Verilog and schematic\nhave not yet been updated with the metal resistor change, and so\nwill fail LVS until they are.\n",
  "tree_diff": [
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      "new_mode": 33188,
      "new_path": "gds/user_analog_project_wrapper.gds"
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}