diff --git a/LICENSE b/LICENSE
index 53d1f3d..57bc88a 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,675 +1,202 @@
-                    GNU GENERAL PUBLIC LICENSE
-                       Version 3, 29 June 2007
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
 
- Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
- Everyone is permitted to copy and distribute verbatim copies
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+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
 
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-the library.  If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.  But first, please read
-<https://www.gnu.org/licenses/why-not-lgpl.html>.
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
 
diff --git a/Makefile b/Makefile
index ad0a063..5012f59 100644
--- a/Makefile
+++ b/Makefile
@@ -117,7 +117,7 @@
 
 $(dv-targets-gl-sdf): SIM=GL_SDF
 $(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
-	$(docker_run_verify-sdk)
+	$(docker_run_verify-sdf)
 
 clean-targets=$(blocks:%=clean-%)
 .PHONY: $(clean-targets)
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def
index c5ce811..7012d99 100644
--- a/def/user_project_wrapper.def
+++ b/def/user_project_wrapper.def
@@ -1309,7 +1309,7 @@
     - via4_1600x3100 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 350 400 350  + ROWCOL 2 1  ;
 END VIAS
 COMPONENTS 1 ;
-    - mprj braille_driver_controller + FIXED ( 960000 900000 ) N ;
+    - mprj actuator_driver_controller + FIXED ( 960000 900000 ) N ;
 END COMPONENTS
 PINS 645 ;
     - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL
diff --git a/gds/user_project_wrapper.gds b/gds/user_project_wrapper.gds
index 5c1363f..50beaae 100644
--- a/gds/user_project_wrapper.gds
+++ b/gds/user_project_wrapper.gds
Binary files differ
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 3546d83..75a5988 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647363522
+timestamp 1647464975
 << metal1 >>
 rect 71774 702992 71780 703044
 rect 71832 703032 71838 703044
@@ -61734,7 +61734,7 @@
 rect 592298 -7622 592382 -7386
 rect 592618 -7622 592650 -7386
 rect -8726 -7654 592650 -7622
-use braille_driver_controller  mprj
+use actuator_driver_controller  mprj
 timestamp 0
 transform 1 0 192000 0 1 180000
 box 0 0 200000 180000
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 02614b7..c6e7b8d 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1647363532
+timestamp 1647464985
 << obsli1 >>
 rect 193104 182159 390812 357361
 << obsm1 >>
@@ -3762,8 +3762,8 @@
 string FIXED_BBOX 0 0 584000 704000
 string LEFclass BLOCK
 string LEFview TRUE
-string GDS_END 18061850
+string GDS_END 17996808
 string GDS_FILE /home/jasteve4/Documents/ActuatorController/openlane/user_project_wrapper/runs/user_project_wrapper/results/finishing/user_project_wrapper.magic.gds
-string GDS_START 16527522
+string GDS_START 16462480
 << end >>
 
diff --git a/openlane/braille_driver_controller/config.tcl b/openlane/actuator_driver_controller/config.tcl
similarity index 95%
rename from openlane/braille_driver_controller/config.tcl
rename to openlane/actuator_driver_controller/config.tcl
index 50845f4..110a42a 100755
--- a/openlane/braille_driver_controller/config.tcl
+++ b/openlane/actuator_driver_controller/config.tcl
@@ -18,11 +18,11 @@
 
 set script_dir [file dirname [file normalize [info script]]]
 
-set ::env(DESIGN_NAME) braille_driver_controller
+set ::env(DESIGN_NAME) actuator_driver_controller
 
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/braille_driver_controller.v
+	$script_dir/../../verilog/rtl/actuator_driver_controller.v
 	$script_dir/../../verilog/rtl/top.v
 	$script_dir/../../verilog/rtl/cells_controller.v
 	$script_dir/../../verilog/rtl/memory_controller.v
diff --git a/openlane/braille_driver_controller/pin_order.cfg b/openlane/actuator_driver_controller/pin_order.cfg
similarity index 100%
rename from openlane/braille_driver_controller/pin_order.cfg
rename to openlane/actuator_driver_controller/pin_order.cfg
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 6bfb9fd..53fa920 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -55,13 +55,13 @@
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/braille_driver_controller.v"
+	$script_dir/../../verilog/rtl/actuator_driver_controller.v"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/braille_driver_controller.lef"
+	$script_dir/../../lef/actuator_driver_controller.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/braille_driver_controller.gds"
+	$script_dir/../../gds/actuator_driver_controller.gds"
 
 # set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 60ddff5..8a10a17 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/jasteve4/Documents/ActuatorController/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h5m31s0ms,0h1m42s0ms,-2.0,-1,-1,-1,476.25,1,0,0,0,0,0,0,0,0,0,-1,-1,724084,1499,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,1.37,3.28,0.01,0.0,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,80.0,12.5,12.5,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/home/jasteve4/Documents/ActuatorController/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h5m35s0ms,0h1m45s0ms,-2.0,-1,-1,-1,476.16,1,0,0,0,0,0,0,0,0,0,-1,-1,724084,1499,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,1.37,3.28,0.01,0.0,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,80.0,12.5,12.5,AREA 0,5,50,1,180,180,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/spi/lvs/user_project_wrapper.spice b/spi/lvs/user_project_wrapper.spice
index bed0ecc..0bb628f 100644
--- a/spi/lvs/user_project_wrapper.spice
+++ b/spi/lvs/user_project_wrapper.spice
@@ -1,7 +1,7 @@
 * NGSPICE file created from user_project_wrapper.ext - technology: sky130A
 
-* Black-box entry subcircuit for braille_driver_controller abstract view
-.subckt braille_driver_controller io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
+* Black-box entry subcircuit for actuator_driver_controller abstract view
+.subckt actuator_driver_controller io_in[0] io_in[10] io_in[11] io_in[12] io_in[13]
 + io_in[14] io_in[15] io_in[16] io_in[17] io_in[18] io_in[19] io_in[1] io_in[20] io_in[21]
 + io_in[22] io_in[23] io_in[24] io_in[25] io_in[26] io_in[27] io_in[28] io_in[29]
 + io_in[2] io_in[30] io_in[31] io_in[32] io_in[33] io_in[34] io_in[35] io_in[36] io_in[37]
@@ -261,6 +261,6 @@
 + la_oenb[79] la_oenb[7] la_oenb[80] la_oenb[81] la_oenb[82] la_oenb[83] la_oenb[84]
 + la_oenb[85] la_oenb[86] la_oenb[87] la_oenb[88] la_oenb[89] la_oenb[8] la_oenb[90]
 + la_oenb[91] la_oenb[92] la_oenb[93] la_oenb[94] la_oenb[95] la_oenb[96] la_oenb[97]
-+ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 vccd1 vssd1 braille_driver_controller
++ la_oenb[98] la_oenb[99] la_oenb[9] user_clock2 vccd1 vssd1 actuator_driver_controller
 .ends
 
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v
index 6cde5b7..37984ed 100644
--- a/verilog/gl/user_project_wrapper.v
+++ b/verilog/gl/user_project_wrapper.v
@@ -54,7 +54,7 @@
  input [3:0] wbs_sel_i;
 
 
- braille_driver_controller mprj (.user_clock2(user_clock2),
+ actuator_driver_controller mprj (.user_clock2(user_clock2),
     .vccd1(vccd1),
     .vssd1(vssd1),
     .io_in({io_in[37],
diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project
index f75e8f3..fd58347 100644
--- a/verilog/includes/includes.gl+sdf.caravel_user_project
+++ b/verilog/includes/includes.gl+sdf.caravel_user_project
@@ -1,3 +1,3 @@
 // Caravel user project includes		
 $USER_PROJECT_VERILOG/gl/user_project_wrapper.v	     
-$USER_PROJECT_VERILOG/gl/braille_driver_controller.v
+$USER_PROJECT_VERILOG/gl/actuator_driver_controller.v
diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
index 9c7efb3..7a04a87 100644
--- a/verilog/includes/includes.gl.caravel_user_project
+++ b/verilog/includes/includes.gl.caravel_user_project
@@ -1,11 +1,3 @@
 # Caravel user project includes	     
 -v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/gl/braille_driver_controller.v    
-#-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
-#-v $(USER_PROJECT_VERILOG)/rtl/braille_driver_controller.v  
-#-v $(USER_PROJECT_VERILOG)/rtl/cells_controller.v  
-#-v $(USER_PROJECT_VERILOG)/rtl/memory_controller.v  
-#-v $(USER_PROJECT_VERILOG)/gl/spi_mod.v  
-#-v $(USER_PROJECT_VERILOG)/rtl/sync_reg.v  
-#-v $(USER_PROJECT_VERILOG)/gl/system_controller.v  
-#-v $(USER_PROJECT_VERILOG)/rtl/top.v
+-v $(USER_PROJECT_VERILOG)/gl/actuator_driver_controller.v    
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index f1bb3cf..ea46a7f 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,6 +1,6 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v	     
--v $(USER_PROJECT_VERILOG)/rtl/braille_driver_controller.v  
+-v $(USER_PROJECT_VERILOG)/rtl/actuator_driver_controller.v  
 -v $(USER_PROJECT_VERILOG)/rtl/cells_controller.v  
 -v $(USER_PROJECT_VERILOG)/rtl/memory_controller.v  
 -v $(USER_PROJECT_VERILOG)/rtl/spi_mod.v  
diff --git a/verilog/rtl/braille_driver_controller.v b/verilog/rtl/actuator_driver_controller.v
similarity index 90%
rename from verilog/rtl/braille_driver_controller.v
rename to verilog/rtl/actuator_driver_controller.v
index 0352ea3..eec0aeb 100644
--- a/verilog/rtl/braille_driver_controller.v
+++ b/verilog/rtl/actuator_driver_controller.v
@@ -17,20 +17,8 @@
 /*
  *-------------------------------------------------------------
  *
- * user_proj_example
+ * actuator_driver_contorller
  *
- * This is an example of a (trivially simple) user project,
- * showing how the user project can connect to the logic
- * analyzer, the wishbone bus, and the I/O pads.
- *
- * This project generates an integer count, which is output
- * on the user area GPIO pads (digital output only).  The
- * wishbone connection allows the project to be controlled
- * (start and stop) from the management SoC program.
- *
- * See the testbenches in directory "mprj_counter" for the
- * example programs that drive this user project.  The three
- * testbenches are "io_ports", "la_test1", and "la_test2".
  *
  *-------------------------------------------------------------
  */
@@ -39,7 +27,7 @@
 `endif
 
 
-module braille_driver_controller
+module actuator_driver_controller
 (
 `ifdef USE_POWER_PINS
     inout vccd1,	// User area 1 1.8V supply
diff --git a/verilog/rtl/cells_controller.v b/verilog/rtl/cells_controller.v
index f1c57ef..baa36aa 100644
--- a/verilog/rtl/cells_controller.v
+++ b/verilog/rtl/cells_controller.v
@@ -1,3 +1,27 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * cell_contorller
+ *
+ *
+ *-------------------------------------------------------------
+ */
 module cells_controller
 (
 `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/memory_controller.v b/verilog/rtl/memory_controller.v
index 66cf639..91d495a 100644
--- a/verilog/rtl/memory_controller.v
+++ b/verilog/rtl/memory_controller.v
@@ -1,3 +1,28 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * memory_contorller
+ *
+ *
+ *-------------------------------------------------------------
+ */
+
 module memory_controller
 (
 `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/spi_mod.v b/verilog/rtl/spi_mod.v
index 78cd3a4..06f7e83 100644
--- a/verilog/rtl/spi_mod.v
+++ b/verilog/rtl/spi_mod.v
@@ -1,3 +1,27 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * spi_mod
+ *
+ *
+ *-------------------------------------------------------------
+ */
 module spi_mod
 (
 `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/sync_reg.v b/verilog/rtl/sync_reg.v
index 061c4ed..9385ba0 100644
--- a/verilog/rtl/sync_reg.v
+++ b/verilog/rtl/sync_reg.v
@@ -1,3 +1,27 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * spi_mod
+ *
+ *
+ *-------------------------------------------------------------
+ */
 module sync_n(
 `ifdef USE_POWER_PINS
     inout vccd1,	// User area 1 1.8V supply
@@ -25,28 +49,3 @@
 
 
 endmodule
-/*
-module sync(
-  input wire signal,
-  output wire signal,
-  input wire clock
-);
-  reg [3:0] signal_state;
-
-  always@(posedge clock)
-  begin
-    if(signal)
-    begin
-      signal_state <= {signal_state[2:0],signal_n};
-    end
-    else
-    begin
-      signal_state <= 3'b000;
-    end
-  end
-
-  assign signal_sn = signal_state == 3'b111 ? 1'b1:1'b0;
-
-
-endmodule
-*/
diff --git a/verilog/rtl/system_controller.v b/verilog/rtl/system_controller.v
index cdec421..a440f8e 100644
--- a/verilog/rtl/system_controller.v
+++ b/verilog/rtl/system_controller.v
@@ -1,3 +1,27 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * system_controller
+ *
+ *
+ *-------------------------------------------------------------
+ */
 module system_controller
 (
 `ifdef USE_POWER_PINS
diff --git a/verilog/rtl/top.v b/verilog/rtl/top.v
index 500edfe..8611be8 100644
--- a/verilog/rtl/top.v
+++ b/verilog/rtl/top.v
@@ -1,3 +1,27 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * top
+ *
+ *
+ *-------------------------------------------------------------
+ */
 module top (
 `ifdef USE_POWER_PINS
     inout vccd1,	// User area 1 1.8V supply
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 9a77cf8..eca5367 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,6 +21,7 @@
     // Assume default net type to be wire because GL netlists don't have the wire definitions
     `default_nettype wire
     `include "gl/user_project_wrapper.v"
+    `include "gl/actuator_driver_cotroller.v"
 `else
     `include "user_project_wrapper.v"
     `include "cells_controller.v" 
@@ -29,5 +30,5 @@
     `include "sync_reg.v"
     `include "system_controller.v"
     `include "top.v"
-    `include "braille_driver_cotroller.v"
+    `include "actuator_driver_cotroller.v"
 `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index aee6365..5ceb500 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -82,7 +82,7 @@
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-braille_driver_controller mprj
+actuator_driver_controller mprj
 (
 `ifdef USE_POWER_PINS
 	.vccd1(vccd1),	// User area 1 1.8V power