verilog/rtl/user_project_includes.v

// +------------+----------+---------------+-----------------------------------------------------------+--------+
// | project id | title    | author        | repo                                                      | commit |
// +------------+----------+---------------+-----------------------------------------------------------+--------+
// | 9          | Parallax | Renldas Zioma | https://github.com/rejunity/zero-to-asic-wrapped-parallax | main   |
// +------------+----------+---------------+-----------------------------------------------------------+--------+
`include "zero-to-asic-wrapped-parallax/wrapper.v" // 9