| /root/pll-based_capacitance-to-digital_converter_mpw4/Makefile |
| /root/pll-based_capacitance-to-digital_converter_mpw4/docs/Makefile |
| /root/pll-based_capacitance-to-digital_converter_mpw4/docs/environment.yml |
| /root/pll-based_capacitance-to-digital_converter_mpw4/docs/source/conf.py |
| /root/pll-based_capacitance-to-digital_converter_mpw4/docs/source/index.rst |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/BUFFMIN_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/CAPOSC_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/DFF_v4p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/INV3X_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/INVMIN_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/INV_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/INVandCAP_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/OSC_v3p2.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/PASSGATE_v1p2.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/SDC_v2p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/invmin_magic_v1p1.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/sky130_fd_pr__cap_mim_m3_1_9K4XRG.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/sky130_fd_pr__cap_mim_m3_2_4SGG6N.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/sky130_fd_pr__cap_mim_m3_2_7PBNAZ.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/sky130_fd_pr__nfet_01v8_59MFY5.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/sky130_fd_pr__nfet_01v8_6H9P4D.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/sky130_fd_pr__pfet_01v8_MA8JHN.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/user_analog_project_wrapper.ext |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/user_analog_project_wrapper.mag.buf1checkok |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/user_analog_project_wrapper.mag.mpw5buf1 |
| /root/pll-based_capacitance-to-digital_converter_mpw4/mag/user_analog_project_wrapper.mag.mpw5orig |
| /root/pll-based_capacitance-to-digital_converter_mpw4/netgen/run_lvs_por.sh |
| /root/pll-based_capacitance-to-digital_converter_mpw4/netgen/run_lvs_wrapper_verilog.sh |
| /root/pll-based_capacitance-to-digital_converter_mpw4/netgen/run_lvs_wrapper_xschem.sh |
| /root/pll-based_capacitance-to-digital_converter_mpw4/netgen/user_analog_project_wrapper.spice.BAK |
| /root/pll-based_capacitance-to-digital_converter_mpw4/netgen/user_analog_project_wrapper.spice.mpw5orig |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/dv/Makefile |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/dv/mprj_por/Makefile |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/dv/mprj_por/mprj_por.c |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/rtl/example_por.v |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/rtl/uprj_analog_netlists.v |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/rtl/user_analog_proj_example.v |
| /root/pll-based_capacitance-to-digital_converter_mpw4/verilog/rtl/user_analog_project_wrapper.v |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/.spiceinit |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/INV3X_v1p1.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/INV3X_v1p1.sym |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/INV_v1p1.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/INV_v1p1.sym |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/PASSGATE_v1p2.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/PASSGATE_v1p2.sym |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/SDC_v2p1.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/SDC_v2p1.sym |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/analog_wrapper_tb.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/example_por.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/example_por.sym |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/example_por_tb.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/example_por_tb.spice.orig |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/test.data |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/test_SDC_CINsweep_v6p1.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/test_SDC_CINsweep_v7p1_mpw5.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/user_analog_project_wrapper.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/user_analog_project_wrapper.sym |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/user_analog_project_wrapper_expor.sch |
| /root/pll-based_capacitance-to-digital_converter_mpw4/xschem/xschemrc |
