)]}'
{
  "log": [
    {
      "commit": "edf0c25f77f1bdcf651cdeabf54aaff44123382f",
      "tree": "fc232374286547385c81a688b4f5c8cdcffcf427",
      "parents": [
        "7b41c992e6f0a3d5b5b2775ffe7ad47d00266e11"
      ],
      "author": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jan 09 09:05:10 2022 -0800"
      },
      "committer": {
        "name": "Jeff DiCorpo",
        "email": "jeffdi@efabless.com",
        "time": "Sun Jan 09 09:05:10 2022 -0800"
      },
      "message": "final gds oasis\n"
    },
    {
      "commit": "7b41c992e6f0a3d5b5b2775ffe7ad47d00266e11",
      "tree": "ad55a550cec36be0cffc91df68e86a304a5bd28d",
      "parents": [
        "aa34177640129bf8c415f5bc086bf3dbdfe7d183"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Wed Jan 05 18:55:50 2022 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Wed Jan 05 18:55:50 2022 +0100"
      },
      "message": "No double instance of each cell.\n\nSee: https://gitlab.com/Chips4Makers/PDKMaster/-/commit/a46f22053e098f776ccf1de929ce79541e5d615c\n"
    },
    {
      "commit": "aa34177640129bf8c415f5bc086bf3dbdfe7d183",
      "tree": "4cc5d4d22c6eae5cec5d8d9c60595b727e023938",
      "parents": [
        "de8f5c986ca240d7c5bf4929ddf57632b4dd1c98"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Wed Jan 05 09:36:55 2022 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Wed Jan 05 09:36:55 2022 +0100"
      },
      "message": "Remove mag directory.\n"
    },
    {
      "commit": "de8f5c986ca240d7c5bf4929ddf57632b4dd1c98",
      "tree": "ddf55b9c84421fe902e2560c447cccb1b8918015",
      "parents": [
        "ddb4bb55947727de363f221e648a13f52b4c384a"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Tue Jan 04 20:25:28 2022 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Tue Jan 04 20:25:28 2022 +0100"
      },
      "message": "First verification results.\n\nAll seem to be working well, RO may be too fast to still get data out.\n"
    },
    {
      "commit": "ddb4bb55947727de363f221e648a13f52b4c384a",
      "tree": "9cffa4632663ddd0918c67a19e760e4a1e370ff7",
      "parents": [
        "c22ccddab828bb4d23544756706fd28047df05b0"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Sun Jan 02 19:57:43 2022 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Sun Jan 02 19:57:43 2022 +0100"
      },
      "message": "Updated dimensions\n\nReduce IO cell size and set IO nmos \u0026 pmos w to target aroun 20mA drive\nstrength.\n"
    },
    {
      "commit": "c22ccddab828bb4d23544756706fd28047df05b0",
      "tree": "2276d648e014fc3d1f5d43575e2f71f0426c342e",
      "parents": [
        "6368073fdfec560f9c360e0faacd12c02c6e0060"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Sat Jan 01 10:50:33 2022 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Sat Jan 01 10:50:33 2022 +0100"
      },
      "message": "Description of the IORO input/output signals.\n"
    },
    {
      "commit": "6368073fdfec560f9c360e0faacd12c02c6e0060",
      "tree": "7a7444eca951ad73b968f6c4221810edd4e0e2ee",
      "parents": [
        "b14b99906c702471c081d927d5ec35e301a16ae4"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Fri Dec 31 20:11:45 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Fri Dec 31 20:11:45 2021 +0100"
      },
      "message": "Provided a README file,\n"
    },
    {
      "commit": "b14b99906c702471c081d927d5ec35e301a16ae4",
      "tree": "69f8e3618d06c26fbfef20e4a55c942f828969ef",
      "parents": [
        "802df7f188e48dae07f33960d1ba7d6ad7f6d893"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Fri Dec 31 17:40:12 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Fri Dec 31 17:41:44 2021 +0100"
      },
      "message": "Updated IO cells with tap in the output driver/ESD clamp.\n\nThis is code update in c4m-flexio library.\n"
    },
    {
      "commit": "802df7f188e48dae07f33960d1ba7d6ad7f6d893",
      "tree": "731316512d9708db4da4adfd3a41e5e52ec76a67",
      "parents": [
        "a1aa4b339a07e94faa67cc3ab1d09def501b54aa"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 16:59:05 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 16:59:05 2021 +0100"
      },
      "message": "Try another fix for netlist\n"
    },
    {
      "commit": "a1aa4b339a07e94faa67cc3ab1d09def501b54aa",
      "tree": "c9fc0d891f85e2361d40d316255df7b467587a8a",
      "parents": [
        "97a281fe44fe769dc8e729edce653f87cb606cd4"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 16:28:31 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 16:28:31 2021 +0100"
      },
      "message": "Fix spice netlist\n"
    },
    {
      "commit": "97a281fe44fe769dc8e729edce653f87cb606cd4",
      "tree": "9d4c6f440e6d1ff1cabee8cca00d184be6094c0c",
      "parents": [
        "b8c38215e8fd9694c1e0d04e5fe332c9b9fa4539"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 15:47:12 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 15:47:12 2021 +0100"
      },
      "message": "Update spice netlist.\n\nLet\u0027s see if update partial spice netlist can solve the precheck\nconsistency check.\n"
    },
    {
      "commit": "b8c38215e8fd9694c1e0d04e5fe332c9b9fa4539",
      "tree": "6ee78b467bc49b03941997c5bf69f4ee4dd54ecb",
      "parents": [
        "3edf109110bbd9d6c070c9a585412812afcb82f0"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 15:46:23 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 15:46:23 2021 +0100"
      },
      "message": "cleansing\n"
    },
    {
      "commit": "3edf109110bbd9d6c070c9a585412812afcb82f0",
      "tree": "64978fab50fd3aeb86c2cf3e5913dbd0aef850c8",
      "parents": [
        "5622bfbacf2d20f13f7f7c1128c7adcdead911d1"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 15:46:11 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 15:46:11 2021 +0100"
      },
      "message": "Fix some DRC errors\n"
    },
    {
      "commit": "5622bfbacf2d20f13f7f7c1128c7adcdead911d1",
      "tree": "c8dc564dc3faf8ad283113237f0700aab37c96f3",
      "parents": [
        "6e0fb962c936fb56c74b371b7da06fcd287bbca1"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 12:13:56 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 12:13:56 2021 +0100"
      },
      "message": "Try to let verilog structure match the gds file.\n"
    },
    {
      "commit": "6e0fb962c936fb56c74b371b7da06fcd287bbca1",
      "tree": "145b64649da8eeab48b85974a6ad05ff99cadfe0",
      "parents": [
        "12d70c9cd2dcba55ede06668f13f30963af04d1d"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 10:50:09 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Thu Dec 30 10:50:09 2021 +0100"
      },
      "message": "First connected out version\n\n* Add logic inside IORO signal to enable and drive output of RO.\n* Connected input/outputs of instantiated subcells to pins on the top cell.\n"
    },
    {
      "commit": "12d70c9cd2dcba55ede06668f13f30963af04d1d",
      "tree": "31cef16210032201e6bfcf175ba57a0f93415f86",
      "parents": [
        "e4ba15592ecca06948f66933302961683a52a4c7"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Tue Dec 28 11:03:02 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Tue Dec 28 11:03:02 2021 +0100"
      },
      "message": "generate.py: Split gen_gds() in subfunctions.\n"
    },
    {
      "commit": "e4ba15592ecca06948f66933302961683a52a4c7",
      "tree": "b82b7021075b9aeface58522aba913794afad43f",
      "parents": [
        "e35fc5fc3ce8f6ef789c0d5bb3adc24b72ce7633"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 16:28:22 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 16:28:22 2021 +0100"
      },
      "message": "Manually fix poly resistor.\n\nThis seems to be bug in klayout (support) code.\n"
    },
    {
      "commit": "e35fc5fc3ce8f6ef789c0d5bb3adc24b72ce7633",
      "tree": "e95dda235b5dd39cb36c6b79a662560e7f157266",
      "parents": [
        "dc20867b86c080bd1155872b99adbc935a9c58da"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 16:24:24 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 16:24:24 2021 +0100"
      },
      "message": "Add saveopts for writing from klayout.\n"
    },
    {
      "commit": "dc20867b86c080bd1155872b99adbc935a9c58da",
      "tree": "9178732d056d8c107ecbadc8c1e9785741406077",
      "parents": [
        "2455de7aee4832c24e43e8c9e965275278278ee8"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 15:24:54 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 15:24:54 2021 +0100"
      },
      "message": "DRC updates\n\n- reduce clamp w for LU rules (TODO: taps on source of clamp)\n- remove pad layer to avoid possible bad interaction with RDL layer.\n"
    },
    {
      "commit": "2455de7aee4832c24e43e8c9e965275278278ee8",
      "tree": "87cfaa4a6cc5b25ec8acb75adca1389d369ec184",
      "parents": [
        "a248e8779c92e9ae03e2c73161e789a2afad75e6"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 14:29:18 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 14:29:18 2021 +0100"
      },
      "message": "Update with bigger NWELL spacing.\n"
    },
    {
      "commit": "a248e8779c92e9ae03e2c73161e789a2afad75e6",
      "tree": "277cb71ec9df2ca7a81b4cd55c182076a1ea38c9",
      "parents": [
        "b7dbb2e301f8df8fe6aad05941c50e552670ac41"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 13:53:21 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 13:53:21 2021 +0100"
      },
      "message": "Try another license.\n"
    },
    {
      "commit": "b7dbb2e301f8df8fe6aad05941c50e552670ac41",
      "tree": "b1c21ea303d010ff3d9fa8561a2d93cf46e1cc2b",
      "parents": [
        "3275e68ff965febbebb1794a4136e274a249ddf4"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 13:25:34 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 13:25:34 2021 +0100"
      },
      "message": "Change LICENSE to GPL V2.0 or later.\n"
    },
    {
      "commit": "3275e68ff965febbebb1794a4136e274a249ddf4",
      "tree": "83aee3d1260327347e2521d8c59d69f9aa10f696",
      "parents": [
        "76361c2a456ff05d5444ea3405755b877ee8f42c"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:33:38 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:33:38 2021 +0100"
      },
      "message": "Remove original gds file.\n"
    },
    {
      "commit": "76361c2a456ff05d5444ea3405755b877ee8f42c",
      "tree": "22ccf5f6bc1799515fe6761d173c11539dd18c7a",
      "parents": [
        "4ad60ed4f8433944b3fdc635b77b89cba78369a9"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:16:29 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:16:29 2021 +0100"
      },
      "message": "Add first version of IO test vehicle.\n"
    },
    {
      "commit": "4ad60ed4f8433944b3fdc635b77b89cba78369a9",
      "tree": "c8c25c5795334f701e3c6d9615836e8576b48663",
      "parents": [
        "b71242bb4c162366c377886a52c8a603e713e2cd"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:14:57 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:14:57 2021 +0100"
      },
      "message": "Ignore python and doit generated files.\n"
    },
    {
      "commit": "b71242bb4c162366c377886a52c8a603e713e2cd",
      "tree": "d37e700ca56de18a4bf14665538fddba51488bd7",
      "parents": [
        "77439112467e3c38041a496a68eaf09ee2564821"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:11:48 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:11:48 2021 +0100"
      },
      "message": "Add empty analog wrapper.\n"
    },
    {
      "commit": "77439112467e3c38041a496a68eaf09ee2564821",
      "tree": "2805b6cb4741203027d05a8a14f93f221fbaa627",
      "parents": [
        "b77f13000c4a8445704b7857c7dff779d94dcb9b"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:10:43 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Mon Dec 27 10:10:43 2021 +0100"
      },
      "message": "Use CERN OHL-S 2.0 licence.\n"
    },
    {
      "commit": "b77f13000c4a8445704b7857c7dff779d94dcb9b",
      "tree": "2dd44f5048e57f0cbecf952539d57df3dea82033",
      "parents": [
        "0bccf80831f117210ffaeaa610b2994b0585365d",
        "1d231e853a5a19c2f7781378b3093a6e90e9869c"
      ],
      "author": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Sun Dec 26 14:37:16 2021 +0100"
      },
      "committer": {
        "name": "Staf Verhaegen",
        "email": "staf@fibraservi.eu",
        "time": "Sun Dec 26 14:37:16 2021 +0100"
      },
      "message": "Merge upstream caravel_user_project_analog into main\n"
    },
    {
      "commit": "0bccf80831f117210ffaeaa610b2994b0585365d",
      "tree": "17466f671072048600d09fc9aee8f20bcd81a648",
      "parents": [],
      "author": {
        "name": "Staf Verhaegen (FibraServi)",
        "email": "github@fibraservi.eu",
        "time": "Sun Dec 26 13:15:25 2021 +0000"
      },
      "committer": {
        "name": "Staf Verhaegen (FibraServi)",
        "email": "github@fibraservi.eu",
        "time": "Sun Dec 26 13:15:25 2021 +0000"
      },
      "message": "Configure SAST in `.gitlab-ci.yml`, creating this file if it does not already exist"
    },
    {
      "commit": "1d231e853a5a19c2f7781378b3093a6e90e9869c",
      "tree": "686edc225872336525566264f1e19560d81e6419",
      "parents": [
        "ea5ff7d937a3422c805b506215ae5242935638b2"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sun Dec 19 17:03:41 2021 -0500"
      },
      "message": "Modified the xschem schematics so that the wrapper level correctly\nrepresents the metal resistors that were added to the layout to\nmaintain all the pins on isolated nets.  The LVS with the xschem\nnetlist is now correct with the modified layout.  The verilog\nnetlist has not yet been updated.\n"
    },
    {
      "commit": "ea5ff7d937a3422c805b506215ae5242935638b2",
      "tree": "76d81ffcbd54654fb9857c795d14849d62e8d675",
      "parents": [
        "4afe80a9c6351d7ac4dd01538be61801a0e14d26"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat Dec 18 10:44:16 2021 -0500"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Sat Dec 18 10:44:16 2021 -0500"
      },
      "message": "Updated the layout to properly use the metal resistors in front of\npins that are connected to the same net.  Updated the GDS with this\nchange, and also to properly generate hierarchical layers, which\napparently had not been done previously.  Verilog and schematic\nhave not yet been updated with the metal resistor change, and so\nwill fail LVS until they are.\n"
    },
    {
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      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:45:49 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Fri May 07 19:45:49 2021 +0200"
      },
      "message": "Update info.yaml to have the user_level_netlist point to the rtl netlist\n"
    },
    {
      "commit": "35111e937c8511a8b33738f0e3629158811dd0f5",
      "tree": "094eb763b3d4947b8b21d9e8f78874610932d52f",
      "parents": [
        "dba051e726bcb22cdf4106c3bd1fe34450daf44c"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 09:52:15 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Fri May 07 09:52:15 2021 -0400"
      },
      "message": "Corrected ngspice testbenches for change in the name of the parameter\nto turn on/off the mismatch parameters.  Restored the boundary layer\nto the example user project layout, moved the boundary layer origin\nand everything else to the grid origin, and rewrote GDS for the\nexample project.\n"
    },
    {
      "commit": "dba051e726bcb22cdf4106c3bd1fe34450daf44c",
      "tree": "443918287b0e0c7c99602cf7bb016d5ec6057fbe",
      "parents": [
        "5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 15:14:34 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 15:14:34 2021 -0400"
      },
      "message": "Modifications to the wrapper testbench schematic (not quite working\nyet, though).\n"
    },
    {
      "commit": "5cc020df86c96d7d61ceda22a9f5b2e5c309b0f7",
      "tree": "3839b58f5e7c2df6cc3bd737b04f59502d7460f7",
      "parents": [
        "a26abdd4844c5057f87540780fca689753eab258"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 11:54:28 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 11:54:28 2021 -0400"
      },
      "message": "Added xschem schematic and symbol for the analog project wrapper, and a\nscript to run netgen LVS against the schematic.\n"
    },
    {
      "commit": "a26abdd4844c5057f87540780fca689753eab258",
      "tree": "42b93d7a3efde5537294072381345123dc788437",
      "parents": [
        "60e4dcb489b69ac3732a1a71efecdfeae9cc61eb"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 10:36:21 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu May 06 10:36:21 2021 -0400"
      },
      "message": "Redid the layout for the example analog project based on the updated\nwrapper layout.  Generated GDS and extracted netlist.\n"
    },
    {
      "commit": "60e4dcb489b69ac3732a1a71efecdfeae9cc61eb",
      "tree": "1be4834144cc29e3d384574a65e161f8170a7030",
      "parents": [
        "8a1d5f234270784c8d08f6e2b0b0bf374bddf34f"
      ],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed May 05 23:41:20 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Wed May 05 23:41:20 2021 +0200"
      },
      "message": "Update Makefile\n"
    },
    {
      "commit": "8a1d5f234270784c8d08f6e2b0b0bf374bddf34f",
      "tree": "28e86ff15d3d9c7b7135dcfd185dff90696809fa",
      "parents": [
        "6bb21656d8c3480c4577920e3b5c3b946e3d5c8b"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 21:56:02 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 21:56:02 2021 -0400"
      },
      "message": "Corrected the info.yaml file to point to the caravan.v file as the\ntop level netlist.\n"
    }
  ],
  "next": "6bb21656d8c3480c4577920e3b5c3b946e3d5c8b"
}