diff --git a/doitcode/generate.py b/doitcode/generate.py
index 04aec13..ae61864 100644
--- a/doitcode/generate.py
+++ b/doitcode/generate.py
@@ -9,7 +9,7 @@
 pya = cast(Any, _pya)
 
 from pdkmaster.technology import geometry as _geo, primitive as _prm
-from pdkmaster.design import layout as _lay, library as _lib
+from pdkmaster.design import circuit, layout as _lay, library as _lib
 from pdkmaster.io.klayout import export as _klexp
 
 from c4m.pdk import sky130
@@ -125,61 +125,48 @@
     m2_width = tech.computed.min_width(m2, down=True, up=True, min_enclosure=True)
 
     net = nets.d_core
-    bottom = max(d_m1pin_bounds1.top, d_m1pin_bounds2.top) + m1.min_space
-    width = d_m1pin_bounds2.right - d_m1pin_bounds1.left
-    _l_via = layouter.wire_layout(
-        net=net, wire=via,
-        bottom_width=width, bottom_enclosure="wide",
-        top_width=width, top_height=m2_width, top_enclosure="wide",
-    )
+    # bottom = max(d_m1pin_bounds1.top, d_m1pin_bounds2.top) + 2*m2.min_space
+    bottom = max(d_m1pin_bounds1.top, d_m1pin_bounds2.top) + 0.5 # big m3 space rule
+    _l_via = layouter.wire_layout(net=net, wire=via, rows=2)
     _m1_bounds = _l_via.bounds(mask=m1.mask)
-    x = 0.5*(d_m1pin_bounds2.right + d_m1pin_bounds1.left)
+    x = d_m1pin_bounds1.center.x
     y = bottom - _m1_bounds.bottom
-    l_via = layouter.place(_l_via, x=x, y=y)
-    m1_bounds = l_via.bounds(mask=m1.mask)
-    m2_bounds = l_via.bounds(mask=m2.mask)
-    layouter.add_wire(
-        net=net, wire=m1, shape=_geo.Rect.from_rect(rect=d_m1pin_bounds1, top=m1_bounds.top),
-    )
-    layouter.add_wire(
-        net=net, wire=m1, shape=_geo.Rect.from_rect(rect=d_m1pin_bounds2, top=m1_bounds.top),
-    )
-    _l_m2 = layouter.wire_layout(
-        net=net, wire=m2, pin=m2pin, width=m2_bounds.width, height=m2_width,
-    )
-    _m2_bounds = _l_m2.bounds()
-    x = m2_bounds.left - _m2_bounds.left
-    y = m2_bounds.bottom - _m2_bounds.bottom
-    l_m2 = layouter.place(_l_m2, x=x, y=y)
+    l1_via = layouter.place(_l_via, x=x, y=y)
+    m1_bounds1 = l1_via.bounds(mask=m1.mask)
+    m2_bounds1 = l1_via.bounds(mask=m2.mask)
+    x = d_m1pin_bounds2.center.x
+    l2_via = layouter.place(_l_via, x=x, y=y)
+    m1_bounds2 = l2_via.bounds(mask=m1.mask)
+    m2_bounds2 = l2_via.bounds(mask=m2.mask)
+
+    rect = _geo.Rect.from_rect(rect=d_m1pin_bounds1, top=m1_bounds1.top)
+    layouter.add_wire(net=net, wire=m1, shape=rect)
+    rect = _geo.Rect.from_rect(rect=d_m1pin_bounds2, top=m1_bounds2.top)
+    layouter.add_wire(net=net, wire=m1, shape=rect)
+    rect = _geo.Rect.from_rect(rect=m2_bounds1, right=m2_bounds2.right)
+    l_m2 = layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=rect)
     dm2_bounds = l_m2.bounds()
 
     net = nets.de_core
     bottom = dm2_bounds.top + m2.min_space
-    width = de_m1pin_bounds2.right - de_m1pin_bounds1.left
-    _l_via = layouter.wire_layout(
-        net=net, wire=via,
-        bottom_width=width, bottom_enclosure="wide",
-        top_width=width, top_height=m2_width, top_enclosure="wide",
-    )
+    _l_via = layouter.wire_layout(net=net, wire=via, rows=2)
     _m1_bounds = _l_via.bounds(mask=m1.mask)
-    x = 0.5*(de_m1pin_bounds2.right + de_m1pin_bounds1.left)
+    x = de_m1pin_bounds1.center.x
     y = bottom - _m1_bounds.bottom
-    l_via = layouter.place(_l_via, x=x, y=y)
-    m1_bounds = l_via.bounds(mask=m1.mask)
-    m2_bounds = l_via.bounds(mask=m2.mask)
-    layouter.add_wire(
-        net=net, wire=m1, shape=_geo.Rect.from_rect(rect=de_m1pin_bounds1, top=m1_bounds.top),
-    )
-    layouter.add_wire(
-        net=net, wire=m1, shape=_geo.Rect.from_rect(rect=de_m1pin_bounds2, top=m1_bounds.top),
-    )
-    _l_m2 = layouter.wire_layout(
-        net=net, wire=m2, pin=m2pin, width=m2_bounds.width, height=m2_width,
-    )
-    _m2_bounds = _l_m2.bounds()
-    x = m2_bounds.left - _m2_bounds.left
-    y = m2_bounds.bottom - _m2_bounds.bottom
-    layouter.place(_l_m2, x=x, y=y)
+    l1_via = layouter.place(_l_via, x=x, y=y)
+    m1_bounds1 = l1_via.bounds(mask=m1.mask)
+    m2_bounds1 = l1_via.bounds(mask=m2.mask)
+    x = de_m1pin_bounds2.center.x
+    l2_via = layouter.place(_l_via, x=x, y=y)
+    m1_bounds2 = l2_via.bounds(mask=m1.mask)
+    m2_bounds2 = l2_via.bounds(mask=m2.mask)
+
+    rect = _geo.Rect.from_rect(rect=de_m1pin_bounds1, top=m1_bounds1.top)
+    layouter.add_wire(net=net, wire=m1, shape=rect)
+    rect = _geo.Rect.from_rect(rect=de_m1pin_bounds2, top=m1_bounds2.top)
+    layouter.add_wire(net=net, wire=m1, shape=rect)
+    rect = _geo.Rect.from_rect(rect=m2_bounds1, right=m2_bounds2.right)
+    layouter.add_wire(net=net, wire=m2, pin=m2pin, shape=rect)
 
     assert isinstance(lay.boundary, _geo.Rect)
     layouter.layout.boundary = _geo.Rect.from_rect(rect=lay.boundary, left=0.0)
@@ -508,7 +495,9 @@
     _l_mcon = layouter.wire_layout(net=net, wire=mcon, rows=2)
     _li_bounds = _l_mcon.bounds(mask=li.mask)
     x = nandlipin_bounds.center.x
-    y = nandlipin_bounds.top - _li_bounds.top
+    # Shift a little below highest possible top to avoid being too close to vdd
+    # connection via
+    y = nandlipin_bounds.top - _li_bounds.top - m2.min_space
     l_mcon = layouter.place(_l_mcon, x=x, y=y)
     nandm1_bounds = l_mcon.bounds(mask=m1.mask)
     x = nandm1_bounds.center.x
@@ -578,9 +567,10 @@
             net=net, wire=via_layer, bottom_height=h, top_height=h, x=x, y=y,
         )
     # via4 needs bigger line
-    l_via4 = layouter.add_wire(net=net, wire=via4, rows=2, x=x, y=y)
+    # Use 2 columns so width is > min_width
+    l_via4 = layouter.add_wire(net=net, wire=via4, columns=2, x=x, y=y)
     m5_bounds1 = l_via4.bounds(mask=m5.mask)
-    _l_via4 = layouter.wire_layout(net=net, wire=via4, rows=2)
+    _l_via4 = layouter.wire_layout(net=net, wire=via4, columns=2)
     _m4_bounds = _l_via4.bounds(mask=m4.mask)
     y = vddpadm4pin_bounds.top - _m4_bounds.top
     l_via4 = layouter.place(_l_via4, x=x, y=y)
diff --git a/gds/user_analog_project_wrapper.gds.gz b/gds/user_analog_project_wrapper.gds.gz
index d9732d8..c605933 100644
--- a/gds/user_analog_project_wrapper.gds.gz
+++ b/gds/user_analog_project_wrapper.gds.gz
Binary files differ