/root/cmos_rail-to-rail_comparator/Makefile
/root/cmos_rail-to-rail_comparator/docs/environment.yml
/root/cmos_rail-to-rail_comparator/docs/Makefile
/root/cmos_rail-to-rail_comparator/docs/source/index.rst
/root/cmos_rail-to-rail_comparator/docs/source/conf.py
/root/cmos_rail-to-rail_comparator/verilog/dv/Makefile
/root/cmos_rail-to-rail_comparator/verilog/dv/mprj_por/mprj_por_tb.v
/root/cmos_rail-to-rail_comparator/verilog/dv/mprj_por/Makefile
/root/cmos_rail-to-rail_comparator/verilog/dv/mprj_por/mprj_por.c
/root/cmos_rail-to-rail_comparator/verilog/rtl/example_por.v
/root/cmos_rail-to-rail_comparator/verilog/rtl/comparator.v
/root/cmos_rail-to-rail_comparator/verilog/rtl/uprj_analog_netlists.v
/root/cmos_rail-to-rail_comparator/verilog/rtl/comparator_bias.v
/root/cmos_rail-to-rail_comparator/verilog/rtl/user_analog_proj_example.v
/root/cmos_rail-to-rail_comparator/verilog/rtl/user_analog_project_wrapper.v
/root/cmos_rail-to-rail_comparator/xschem/xschemrc
/root/cmos_rail-to-rail_comparator/xschem/comparator.sym
/root/cmos_rail-to-rail_comparator/xschem/tb_comparator.sch
/root/cmos_rail-to-rail_comparator/xschem/user_analog_project_wrapper.sym
/root/cmos_rail-to-rail_comparator/xschem/comparator_bias.sym
/root/cmos_rail-to-rail_comparator/xschem/comparator_bias.sch
/root/cmos_rail-to-rail_comparator/xschem/user_analog_project_wrapper.sch
/root/cmos_rail-to-rail_comparator/xschem/analog_wrapper_tb.sch
/root/cmos_rail-to-rail_comparator/xschem/comparator.sch
/root/cmos_rail-to-rail_comparator/xschem/.spiceinit
/root/cmos_rail-to-rail_comparator/openlane/Makefile
/root/cmos_rail-to-rail_comparator/netgen/run_lvs_wrapper_verilog.sh
/root/cmos_rail-to-rail_comparator/netgen/run_lvs_por.sh
/root/cmos_rail-to-rail_comparator/netgen/run_lvs_wrapper_xschem.sh