2021-12-30 05:47:18 - [INFO] - {{Project Git Info}} Repository: https://github.com/maherbenhouria/caravel_user_project_analog.git | Branch: main | Commit: 58371fc1a28d00b23ef44898c2353b66d53499cf
2021-12-30 05:47:18 - [INFO] - {{INSTALLING CARAVEL}} Running `make install` in cmos_rail-to-rail_comparator
2021-12-30 05:47:27 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: cmos_rail-to-rail_comparator
2021-12-30 05:47:31 - [INFO] - {{Project GDS Info}} user_analog_project_wrapper: 8e3521f75972501c663fc0b1219305624d63e742
2021-12-30 05:47:31 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.245
2021-12-30 05:47:31 - [INFO] - {{PDKs Info}} Open PDKs: 476f7428f7f686de51a5164c702629a9b9f2da46 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-12-30 05:47:31 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'cmos_rail-to-rail_comparator/jobs/mpw_precheck/df73585b-1b84-4ba1-93ec-63da1b293f30/logs'
2021-12-30 05:47:31 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-12-30 05:47:31 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2021-12-30 05:47:32 - [INFO] - An approved LICENSE (Apache-2.0) was found in cmos_rail-to-rail_comparator.
2021-12-30 05:47:32 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-12-30 05:47:33 - [INFO] - An approved LICENSE (Apache-2.0) was found in cmos_rail-to-rail_comparator.
2021-12-30 05:47:34 - [INFO] - An approved LICENSE (Apache-2.0) was found in cmos_rail-to-rail_comparator.
2021-12-30 05:47:34 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-12-30 05:47:34 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 29 non-compliant file(s) with the SPDX Standard.
2021-12-30 05:47:34 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['cmos_rail-to-rail_comparator/Makefile', 'cmos_rail-to-rail_comparator/docs/environment.yml', 'cmos_rail-to-rail_comparator/docs/Makefile', 'cmos_rail-to-rail_comparator/docs/source/index.rst', 'cmos_rail-to-rail_comparator/docs/source/conf.py', 'cmos_rail-to-rail_comparator/verilog/dv/Makefile', 'cmos_rail-to-rail_comparator/verilog/dv/mprj_por/mprj_por_tb.v', 'cmos_rail-to-rail_comparator/verilog/dv/mprj_por/Makefile', 'cmos_rail-to-rail_comparator/verilog/dv/mprj_por/mprj_por.c', 'cmos_rail-to-rail_comparator/verilog/rtl/example_por.v', 'cmos_rail-to-rail_comparator/verilog/rtl/comparator.v', 'cmos_rail-to-rail_comparator/verilog/rtl/uprj_analog_netlists.v', 'cmos_rail-to-rail_comparator/verilog/rtl/comparator_bias.v', 'cmos_rail-to-rail_comparator/verilog/rtl/user_analog_proj_example.v', 'cmos_rail-to-rail_comparator/verilog/rtl/user_analog_project_wrapper.v']
2021-12-30 05:47:34 - [INFO] - For the full SPDX compliance report check: cmos_rail-to-rail_comparator/jobs/mpw_precheck/df73585b-1b84-4ba1-93ec-63da1b293f30/logs/spdx_compliance_report.log
2021-12-30 05:47:34 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2021-12-30 05:47:34 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-12-30 05:47:34 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2021-12-30 05:47:34 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-12-30 05:47:34 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-12-30 05:47:34 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2021-12-30 05:47:34 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-12-30 05:47:34 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2021-12-30 05:47:34 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_analog_project_wrapper.v
2021-12-30 05:47:34 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_analog_project_wrapper.v
2021-12-30 05:47:34 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
2021-12-30 05:47:34 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
2021-12-30 05:47:36 - [INFO] - HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan. 
2021-12-30 05:47:36 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances). 
2021-12-30 05:47:36 - [INFO] - MODELING CHECK PASSED: Netlist caravan is structural.
2021-12-30 05:47:36 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_analog_project_wrapper are correctly connected in the top level netlist caravan.
2021-12-30 05:47:36 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravan netlist passed all consistency checks.
2021-12-30 05:47:36 - [INFO] - PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
2021-12-30 05:47:36 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (11 instances). 
2021-12-30 05:47:36 - [INFO] - MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
2021-12-30 05:47:36 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
2021-12-30 05:47:36 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
2021-12-30 05:47:36 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-12-30 05:47:36 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2021-12-30 05:47:36 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_analog_project_wrapper_empty.gds.gz
2021-12-30 05:47:36 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_analog_project_wrapper_empty.gds.gz
2021-12-30 05:47:39 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view cmos_rail-to-rail_comparator/jobs/mpw_precheck/df73585b-1b84-4ba1-93ec-63da1b293f30/outputs/user_analog_project_wrapper.xor.gds
2021-12-30 05:47:39 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-12-30 05:47:39 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2021-12-30 05:47:41 - [INFO] - 0 DRC violations
2021-12-30 05:47:41 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:41 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2021-12-30 05:47:43 - [INFO] - No DRC Violations found
2021-12-30 05:47:43 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:43 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2021-12-30 05:47:46 - [INFO] - No DRC Violations found
2021-12-30 05:47:46 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:46 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2021-12-30 05:47:48 - [INFO] - No DRC Violations found
2021-12-30 05:47:48 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:48 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2021-12-30 05:47:49 - [INFO] - No DRC Violations found
2021-12-30 05:47:49 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:49 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2021-12-30 05:47:51 - [INFO] - No DRC Violations found
2021-12-30 05:47:51 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:51 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2021-12-30 05:47:52 - [INFO] - No DRC Violations found
2021-12-30 05:47:52 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
2021-12-30 05:47:52 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'cmos_rail-to-rail_comparator/jobs/mpw_precheck/df73585b-1b84-4ba1-93ec-63da1b293f30/logs'
2021-12-30 05:47:52 - [INFO] - {{SUCCESS}} All Checks Passed !!!