)]}'
{
  "commit": "c459148a62cc64f44d2c6ec8464eb5e4fd027fc3",
  "tree": "703175235e5eb2f2e0b61ea02e391664d84f8789",
  "parents": [
    "3502cdefcdacd65a189a877b61619d890b92cf0e"
  ],
  "author": {
    "name": "maherbenhouria",
    "email": "maher.benhouria@gmail.com",
    "time": "Thu Dec 30 00:28:28 2021 -0500"
  },
  "committer": {
    "name": "maherbenhouria",
    "email": "maher.benhouria@gmail.com",
    "time": "Thu Dec 30 00:28:28 2021 -0500"
  },
  "message": "updated verilog description\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "79cf28bba1be2464c70ae4f67d54041697966a47",
      "new_mode": 33188,
      "new_path": "verilog/rtl/comparator.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "95eb29501e68ecc55f0ecc7db111f37619c98717",
      "new_mode": 33188,
      "new_path": "verilog/rtl/comparator_bias.v"
    },
    {
      "type": "modify",
      "old_id": "94412daf1dafed3cc3d160a33fd66818b58bdfdb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_analog_proj_example.v",
      "new_id": "6012e59a421dee662b8d2e470bcb3a56c7377699",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_analog_proj_example.v"
    }
  ]
}
