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        "time": "Thu Apr 29 16:40:10 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:40:10 2021 -0400"
      },
      "message": "Changed the schematics so that the resistor does not set a W\nvalue, but the underlying model does anyway so this has no effect\non the LVS, which still flags property errors.\n"
    },
    {
      "commit": "796099ed315805cfb93927d461c2a3f987660daa",
      "tree": "a8daa2bef539b81d4dcd68725ac203fd681f8f4f",
      "parents": [
        "dfc24ad0d2edaec6065144b7e2600c8d02bdd592"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:30:42 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:30:42 2021 -0400"
      },
      "message": "Corrected the schematic for the proper orientation of the topmost\ncapacitor;  the circuit now passes LVS.\n"
    },
    {
      "commit": "dfc24ad0d2edaec6065144b7e2600c8d02bdd592",
      "tree": "ab3abe59c6d04da54485c3087f85db84355b1ec6",
      "parents": [
        "fb1300105269c80e54ebc41efd883396ddbc382f"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:18:51 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Thu Apr 29 16:18:51 2021 -0400"
      },
      "message": "Added xschem schematic of the POR and testbench simulations and\nresults.\n"
    },
    {
      "commit": "fb1300105269c80e54ebc41efd883396ddbc382f",
      "tree": "9508e96380dc29acf6a6c46fad52e5ce171d0bed",
      "parents": [
        "a44a60b225e824c4eeb61bd99fed0d6da25ee6b0"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:08:25 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:08:25 2021 -0400"
      },
      "message": "Simple layout, unwired (needs modifications to the project wrapper)\n"
    },
    {
      "commit": "a44a60b225e824c4eeb61bd99fed0d6da25ee6b0",
      "tree": "f283a100f106709d046072587377dee6e5656f78",
      "parents": [
        "6af7408dc6bbf5dde440266476933cebd69f3ba7"
      ],
      "author": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:05:41 2021 -0400"
      },
      "committer": {
        "name": "Tim Edwards",
        "email": "tim@opencircuitdesign.com",
        "time": "Wed Apr 28 14:05:41 2021 -0400"
      },
      "message": "Preliminary work on the analog user project example.  Added verilog RTL and\ntestbench.  The design passes the testbench.\n"
    },
    {
      "commit": "6af7408dc6bbf5dde440266476933cebd69f3ba7",
      "tree": "c6e60b12e76336e2f23956900965769c1215ade5",
      "parents": [],
      "author": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Mon Apr 26 14:56:35 2021 +0200"
      },
      "committer": {
        "name": "manarabdelaty",
        "email": "manarabdelatty@aucegypt.edu",
        "time": "Mon Apr 26 14:56:35 2021 +0200"
      },
      "message": "Initial commit\n"
    }
  ]
}