tree f283a100f106709d046072587377dee6e5656f78
parent 6af7408dc6bbf5dde440266476933cebd69f3ba7
author Tim Edwards <tim@opencircuitdesign.com> 1619633141 -0400
committer Tim Edwards <tim@opencircuitdesign.com> 1619633141 -0400

Preliminary work on the analog user project example.  Added verilog RTL and
testbench.  The design passes the testbench.