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Caravel
qspi testbench
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This testbench is mainly a copy of the gpio testbench and uses the
same checks for pass/fail status.  The difference is that the startup
C code puts the SPI flash into QSPI/DDR/CRM modes for fastest access
and enables the GPIO channels 36 and 37 to work as the flash IO2 and
IO3 channels.  If the channel and spimemio setup works correctly,
then the testbench simulation will pass.