diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index eb8508b..4cdd692 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index 0bd209a..d048acc 100644
--- a/lef/user_project_wrapper.lef
+++ b/lef/user_project_wrapper.lef
@@ -4264,11 +4264,11 @@
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 59.090 2934.450 62.190 ;
+        RECT -14.830 49.090 2934.450 52.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 129.090 2934.450 132.190 ;
+        RECT -14.830 124.090 2934.450 127.190 ;
     END
     PORT
       LAYER met5 ;
@@ -4276,59 +4276,55 @@
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 269.090 2934.450 272.190 ;
+        RECT -14.830 274.090 2934.450 277.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 339.090 2934.450 342.190 ;
+        RECT -14.830 349.090 2934.450 352.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 409.090 2934.450 412.190 ;
+        RECT -14.830 424.090 2934.450 427.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 479.090 2934.450 482.190 ;
+        RECT -14.830 499.090 2934.450 502.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 549.090 2934.450 552.190 ;
+        RECT -14.830 574.090 2934.450 577.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 619.090 2934.450 622.190 ;
+        RECT -14.830 649.090 2934.450 652.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 689.090 2934.450 692.190 ;
+        RECT -14.830 724.090 2934.450 727.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 759.090 2934.450 762.190 ;
+        RECT -14.830 799.090 2934.450 802.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 829.090 2934.450 832.190 ;
+        RECT -14.830 874.090 2934.450 877.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 899.090 2934.450 902.190 ;
+        RECT -14.830 949.090 2934.450 952.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 969.090 2934.450 972.190 ;
+        RECT -14.830 1024.090 2934.450 1027.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1039.090 2934.450 1042.190 ;
+        RECT -14.830 1099.090 2934.450 1102.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1109.090 2934.450 1112.190 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 1179.090 2934.450 1182.190 ;
+        RECT -14.830 1174.090 2934.450 1177.190 ;
     END
     PORT
       LAYER met5 ;
@@ -4336,59 +4332,55 @@
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1319.090 2934.450 1322.190 ;
+        RECT -14.830 1324.090 2934.450 1327.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1389.090 2934.450 1392.190 ;
+        RECT -14.830 1399.090 2934.450 1402.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1459.090 2934.450 1462.190 ;
+        RECT -14.830 1474.090 2934.450 1477.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1529.090 2934.450 1532.190 ;
+        RECT -14.830 1549.090 2934.450 1552.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1599.090 2934.450 1602.190 ;
+        RECT -14.830 1624.090 2934.450 1627.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1669.090 2934.450 1672.190 ;
+        RECT -14.830 1699.090 2934.450 1702.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1739.090 2934.450 1742.190 ;
+        RECT -14.830 1774.090 2934.450 1777.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1809.090 2934.450 1812.190 ;
+        RECT -14.830 1849.090 2934.450 1852.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1879.090 2934.450 1882.190 ;
+        RECT -14.830 1924.090 2934.450 1927.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1949.090 2934.450 1952.190 ;
+        RECT -14.830 1999.090 2934.450 2002.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2019.090 2934.450 2022.190 ;
+        RECT -14.830 2074.090 2934.450 2077.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2089.090 2934.450 2092.190 ;
+        RECT -14.830 2149.090 2934.450 2152.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2159.090 2934.450 2162.190 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 2229.090 2934.450 2232.190 ;
+        RECT -14.830 2224.090 2934.450 2227.190 ;
     END
     PORT
       LAYER met5 ;
@@ -4396,59 +4388,55 @@
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2369.090 2934.450 2372.190 ;
+        RECT -14.830 2374.090 2934.450 2377.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2439.090 2934.450 2442.190 ;
+        RECT -14.830 2449.090 2934.450 2452.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2509.090 2934.450 2512.190 ;
+        RECT -14.830 2524.090 2934.450 2527.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2579.090 2934.450 2582.190 ;
+        RECT -14.830 2599.090 2934.450 2602.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2649.090 2934.450 2652.190 ;
+        RECT -14.830 2674.090 2934.450 2677.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2719.090 2934.450 2722.190 ;
+        RECT -14.830 2749.090 2934.450 2752.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2789.090 2934.450 2792.190 ;
+        RECT -14.830 2824.090 2934.450 2827.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2859.090 2934.450 2862.190 ;
+        RECT -14.830 2899.090 2934.450 2902.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2929.090 2934.450 2932.190 ;
+        RECT -14.830 2974.090 2934.450 2977.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2999.090 2934.450 3002.190 ;
+        RECT -14.830 3049.090 2934.450 3052.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3069.090 2934.450 3072.190 ;
+        RECT -14.830 3124.090 2934.450 3127.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3139.090 2934.450 3142.190 ;
+        RECT -14.830 3199.090 2934.450 3202.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3209.090 2934.450 3212.190 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3279.090 2934.450 3282.190 ;
+        RECT -14.830 3274.090 2934.450 3277.190 ;
     END
     PORT
       LAYER met5 ;
@@ -4456,11 +4444,11 @@
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3419.090 2934.450 3422.190 ;
+        RECT -14.830 3424.090 2934.450 3427.190 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3489.090 2934.450 3492.190 ;
+        RECT -14.830 3499.090 2934.450 3502.190 ;
     END
     PORT
       LAYER met5 ;
@@ -5968,199 +5956,187 @@
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 94.090 2934.450 97.190 ;
+        RECT -14.830 86.590 2934.450 89.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 164.090 2934.450 167.190 ;
+        RECT -14.830 161.590 2934.450 164.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 234.090 2934.450 237.190 ;
+        RECT -14.830 236.590 2934.450 239.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 304.090 2934.450 307.190 ;
+        RECT -14.830 311.590 2934.450 314.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 374.090 2934.450 377.190 ;
+        RECT -14.830 386.590 2934.450 389.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 444.090 2934.450 447.190 ;
+        RECT -14.830 461.590 2934.450 464.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 514.090 2934.450 517.190 ;
+        RECT -14.830 536.590 2934.450 539.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 584.090 2934.450 587.190 ;
+        RECT -14.830 611.590 2934.450 614.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 654.090 2934.450 657.190 ;
+        RECT -14.830 686.590 2934.450 689.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 724.090 2934.450 727.190 ;
+        RECT -14.830 761.590 2934.450 764.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 794.090 2934.450 797.190 ;
+        RECT -14.830 836.590 2934.450 839.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 864.090 2934.450 867.190 ;
+        RECT -14.830 911.590 2934.450 914.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 934.090 2934.450 937.190 ;
+        RECT -14.830 986.590 2934.450 989.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1004.090 2934.450 1007.190 ;
+        RECT -14.830 1061.590 2934.450 1064.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1074.090 2934.450 1077.190 ;
+        RECT -14.830 1136.590 2934.450 1139.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1144.090 2934.450 1147.190 ;
+        RECT -14.830 1211.590 2934.450 1214.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1214.090 2934.450 1217.190 ;
+        RECT -14.830 1286.590 2934.450 1289.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1284.090 2934.450 1287.190 ;
+        RECT -14.830 1361.590 2934.450 1364.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1354.090 2934.450 1357.190 ;
+        RECT -14.830 1436.590 2934.450 1439.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1424.090 2934.450 1427.190 ;
+        RECT -14.830 1511.590 2934.450 1514.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1494.090 2934.450 1497.190 ;
+        RECT -14.830 1586.590 2934.450 1589.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1564.090 2934.450 1567.190 ;
+        RECT -14.830 1661.590 2934.450 1664.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1634.090 2934.450 1637.190 ;
+        RECT -14.830 1736.590 2934.450 1739.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1704.090 2934.450 1707.190 ;
+        RECT -14.830 1811.590 2934.450 1814.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1774.090 2934.450 1777.190 ;
+        RECT -14.830 1886.590 2934.450 1889.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1844.090 2934.450 1847.190 ;
+        RECT -14.830 1961.590 2934.450 1964.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1914.090 2934.450 1917.190 ;
+        RECT -14.830 2036.590 2934.450 2039.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 1984.090 2934.450 1987.190 ;
+        RECT -14.830 2111.590 2934.450 2114.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2054.090 2934.450 2057.190 ;
+        RECT -14.830 2186.590 2934.450 2189.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2124.090 2934.450 2127.190 ;
+        RECT -14.830 2261.590 2934.450 2264.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2194.090 2934.450 2197.190 ;
+        RECT -14.830 2336.590 2934.450 2339.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2264.090 2934.450 2267.190 ;
+        RECT -14.830 2411.590 2934.450 2414.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2334.090 2934.450 2337.190 ;
+        RECT -14.830 2486.590 2934.450 2489.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2404.090 2934.450 2407.190 ;
+        RECT -14.830 2561.590 2934.450 2564.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2474.090 2934.450 2477.190 ;
+        RECT -14.830 2636.590 2934.450 2639.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2544.090 2934.450 2547.190 ;
+        RECT -14.830 2711.590 2934.450 2714.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2614.090 2934.450 2617.190 ;
+        RECT -14.830 2786.590 2934.450 2789.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2684.090 2934.450 2687.190 ;
+        RECT -14.830 2861.590 2934.450 2864.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2754.090 2934.450 2757.190 ;
+        RECT -14.830 2936.590 2934.450 2939.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2824.090 2934.450 2827.190 ;
+        RECT -14.830 3011.590 2934.450 3014.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2894.090 2934.450 2897.190 ;
+        RECT -14.830 3086.590 2934.450 3089.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 2964.090 2934.450 2967.190 ;
+        RECT -14.830 3161.590 2934.450 3164.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3034.090 2934.450 3037.190 ;
+        RECT -14.830 3236.590 2934.450 3239.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3104.090 2934.450 3107.190 ;
+        RECT -14.830 3311.590 2934.450 3314.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3174.090 2934.450 3177.190 ;
+        RECT -14.830 3386.590 2934.450 3389.690 ;
     END
     PORT
       LAYER met5 ;
-        RECT -14.830 3244.090 2934.450 3247.190 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3314.090 2934.450 3317.190 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3384.090 2934.450 3387.190 ;
-    END
-    PORT
-      LAYER met5 ;
-        RECT -14.830 3454.090 2934.450 3457.190 ;
+        RECT -14.830 3461.590 2934.450 3464.690 ;
     END
     PORT
       LAYER met5 ;
@@ -8509,9 +8485,9 @@
   END wbs_we_i
   OBS
       LAYER li1 ;
-        RECT 5.520 5.525 2914.100 3508.885 ;
+        RECT 5.520 6.545 2916.255 3508.885 ;
       LAYER met1 ;
-        RECT 2.830 4.120 2917.250 3509.040 ;
+        RECT 2.830 0.040 2917.250 3509.040 ;
       LAYER met2 ;
         RECT 2.860 3517.320 40.150 3518.050 ;
         RECT 41.270 3517.320 121.110 3518.050 ;
@@ -8551,499 +8527,499 @@
         RECT 2798.970 3517.320 2878.810 3518.050 ;
         RECT 2879.930 3517.320 2917.220 3518.050 ;
         RECT 2.860 2.680 2917.220 3517.320 ;
-        RECT 3.550 2.400 7.950 2.680 ;
-        RECT 9.070 2.400 13.930 2.680 ;
-        RECT 15.050 2.400 19.910 2.680 ;
-        RECT 21.030 2.400 25.890 2.680 ;
-        RECT 27.010 2.400 31.870 2.680 ;
-        RECT 32.990 2.400 37.850 2.680 ;
-        RECT 38.970 2.400 43.370 2.680 ;
-        RECT 44.490 2.400 49.350 2.680 ;
-        RECT 50.470 2.400 55.330 2.680 ;
-        RECT 56.450 2.400 61.310 2.680 ;
-        RECT 62.430 2.400 67.290 2.680 ;
-        RECT 68.410 2.400 73.270 2.680 ;
-        RECT 74.390 2.400 79.250 2.680 ;
-        RECT 80.370 2.400 84.770 2.680 ;
-        RECT 85.890 2.400 90.750 2.680 ;
-        RECT 91.870 2.400 96.730 2.680 ;
-        RECT 97.850 2.400 102.710 2.680 ;
-        RECT 103.830 2.400 108.690 2.680 ;
-        RECT 109.810 2.400 114.670 2.680 ;
-        RECT 115.790 2.400 120.650 2.680 ;
-        RECT 121.770 2.400 126.170 2.680 ;
-        RECT 127.290 2.400 132.150 2.680 ;
-        RECT 133.270 2.400 138.130 2.680 ;
-        RECT 139.250 2.400 144.110 2.680 ;
-        RECT 145.230 2.400 150.090 2.680 ;
-        RECT 151.210 2.400 156.070 2.680 ;
-        RECT 157.190 2.400 161.590 2.680 ;
-        RECT 162.710 2.400 167.570 2.680 ;
-        RECT 168.690 2.400 173.550 2.680 ;
-        RECT 174.670 2.400 179.530 2.680 ;
-        RECT 180.650 2.400 185.510 2.680 ;
-        RECT 186.630 2.400 191.490 2.680 ;
-        RECT 192.610 2.400 197.470 2.680 ;
-        RECT 198.590 2.400 202.990 2.680 ;
-        RECT 204.110 2.400 208.970 2.680 ;
-        RECT 210.090 2.400 214.950 2.680 ;
-        RECT 216.070 2.400 220.930 2.680 ;
-        RECT 222.050 2.400 226.910 2.680 ;
-        RECT 228.030 2.400 232.890 2.680 ;
-        RECT 234.010 2.400 238.870 2.680 ;
-        RECT 239.990 2.400 244.390 2.680 ;
-        RECT 245.510 2.400 250.370 2.680 ;
-        RECT 251.490 2.400 256.350 2.680 ;
-        RECT 257.470 2.400 262.330 2.680 ;
-        RECT 263.450 2.400 268.310 2.680 ;
-        RECT 269.430 2.400 274.290 2.680 ;
-        RECT 275.410 2.400 279.810 2.680 ;
-        RECT 280.930 2.400 285.790 2.680 ;
-        RECT 286.910 2.400 291.770 2.680 ;
-        RECT 292.890 2.400 297.750 2.680 ;
-        RECT 298.870 2.400 303.730 2.680 ;
-        RECT 304.850 2.400 309.710 2.680 ;
-        RECT 310.830 2.400 315.690 2.680 ;
-        RECT 316.810 2.400 321.210 2.680 ;
-        RECT 322.330 2.400 327.190 2.680 ;
-        RECT 328.310 2.400 333.170 2.680 ;
-        RECT 334.290 2.400 339.150 2.680 ;
-        RECT 340.270 2.400 345.130 2.680 ;
-        RECT 346.250 2.400 351.110 2.680 ;
-        RECT 352.230 2.400 357.090 2.680 ;
-        RECT 358.210 2.400 362.610 2.680 ;
-        RECT 363.730 2.400 368.590 2.680 ;
-        RECT 369.710 2.400 374.570 2.680 ;
-        RECT 375.690 2.400 380.550 2.680 ;
-        RECT 381.670 2.400 386.530 2.680 ;
-        RECT 387.650 2.400 392.510 2.680 ;
-        RECT 393.630 2.400 398.030 2.680 ;
-        RECT 399.150 2.400 404.010 2.680 ;
-        RECT 405.130 2.400 409.990 2.680 ;
-        RECT 411.110 2.400 415.970 2.680 ;
-        RECT 417.090 2.400 421.950 2.680 ;
-        RECT 423.070 2.400 427.930 2.680 ;
-        RECT 429.050 2.400 433.910 2.680 ;
-        RECT 435.030 2.400 439.430 2.680 ;
-        RECT 440.550 2.400 445.410 2.680 ;
-        RECT 446.530 2.400 451.390 2.680 ;
-        RECT 452.510 2.400 457.370 2.680 ;
-        RECT 458.490 2.400 463.350 2.680 ;
-        RECT 464.470 2.400 469.330 2.680 ;
-        RECT 470.450 2.400 475.310 2.680 ;
-        RECT 476.430 2.400 480.830 2.680 ;
-        RECT 481.950 2.400 486.810 2.680 ;
-        RECT 487.930 2.400 492.790 2.680 ;
-        RECT 493.910 2.400 498.770 2.680 ;
-        RECT 499.890 2.400 504.750 2.680 ;
-        RECT 505.870 2.400 510.730 2.680 ;
-        RECT 511.850 2.400 516.250 2.680 ;
-        RECT 517.370 2.400 522.230 2.680 ;
-        RECT 523.350 2.400 528.210 2.680 ;
-        RECT 529.330 2.400 534.190 2.680 ;
-        RECT 535.310 2.400 540.170 2.680 ;
-        RECT 541.290 2.400 546.150 2.680 ;
-        RECT 547.270 2.400 552.130 2.680 ;
-        RECT 553.250 2.400 557.650 2.680 ;
-        RECT 558.770 2.400 563.630 2.680 ;
-        RECT 564.750 2.400 569.610 2.680 ;
-        RECT 570.730 2.400 575.590 2.680 ;
-        RECT 576.710 2.400 581.570 2.680 ;
-        RECT 582.690 2.400 587.550 2.680 ;
-        RECT 588.670 2.400 593.530 2.680 ;
-        RECT 594.650 2.400 599.050 2.680 ;
-        RECT 600.170 2.400 605.030 2.680 ;
-        RECT 606.150 2.400 611.010 2.680 ;
-        RECT 612.130 2.400 616.990 2.680 ;
-        RECT 618.110 2.400 622.970 2.680 ;
-        RECT 624.090 2.400 628.950 2.680 ;
-        RECT 630.070 2.400 634.470 2.680 ;
-        RECT 635.590 2.400 640.450 2.680 ;
-        RECT 641.570 2.400 646.430 2.680 ;
-        RECT 647.550 2.400 652.410 2.680 ;
-        RECT 653.530 2.400 658.390 2.680 ;
-        RECT 659.510 2.400 664.370 2.680 ;
-        RECT 665.490 2.400 670.350 2.680 ;
-        RECT 671.470 2.400 675.870 2.680 ;
-        RECT 676.990 2.400 681.850 2.680 ;
-        RECT 682.970 2.400 687.830 2.680 ;
-        RECT 688.950 2.400 693.810 2.680 ;
-        RECT 694.930 2.400 699.790 2.680 ;
-        RECT 700.910 2.400 705.770 2.680 ;
-        RECT 706.890 2.400 711.750 2.680 ;
-        RECT 712.870 2.400 717.270 2.680 ;
-        RECT 718.390 2.400 723.250 2.680 ;
-        RECT 724.370 2.400 729.230 2.680 ;
-        RECT 730.350 2.400 735.210 2.680 ;
-        RECT 736.330 2.400 741.190 2.680 ;
-        RECT 742.310 2.400 747.170 2.680 ;
-        RECT 748.290 2.400 752.690 2.680 ;
-        RECT 753.810 2.400 758.670 2.680 ;
-        RECT 759.790 2.400 764.650 2.680 ;
-        RECT 765.770 2.400 770.630 2.680 ;
-        RECT 771.750 2.400 776.610 2.680 ;
-        RECT 777.730 2.400 782.590 2.680 ;
-        RECT 783.710 2.400 788.570 2.680 ;
-        RECT 789.690 2.400 794.090 2.680 ;
-        RECT 795.210 2.400 800.070 2.680 ;
-        RECT 801.190 2.400 806.050 2.680 ;
-        RECT 807.170 2.400 812.030 2.680 ;
-        RECT 813.150 2.400 818.010 2.680 ;
-        RECT 819.130 2.400 823.990 2.680 ;
-        RECT 825.110 2.400 829.970 2.680 ;
-        RECT 831.090 2.400 835.490 2.680 ;
-        RECT 836.610 2.400 841.470 2.680 ;
-        RECT 842.590 2.400 847.450 2.680 ;
-        RECT 848.570 2.400 853.430 2.680 ;
-        RECT 854.550 2.400 859.410 2.680 ;
-        RECT 860.530 2.400 865.390 2.680 ;
-        RECT 866.510 2.400 870.910 2.680 ;
-        RECT 872.030 2.400 876.890 2.680 ;
-        RECT 878.010 2.400 882.870 2.680 ;
-        RECT 883.990 2.400 888.850 2.680 ;
-        RECT 889.970 2.400 894.830 2.680 ;
-        RECT 895.950 2.400 900.810 2.680 ;
-        RECT 901.930 2.400 906.790 2.680 ;
-        RECT 907.910 2.400 912.310 2.680 ;
-        RECT 913.430 2.400 918.290 2.680 ;
-        RECT 919.410 2.400 924.270 2.680 ;
-        RECT 925.390 2.400 930.250 2.680 ;
-        RECT 931.370 2.400 936.230 2.680 ;
-        RECT 937.350 2.400 942.210 2.680 ;
-        RECT 943.330 2.400 948.190 2.680 ;
-        RECT 949.310 2.400 953.710 2.680 ;
-        RECT 954.830 2.400 959.690 2.680 ;
-        RECT 960.810 2.400 965.670 2.680 ;
-        RECT 966.790 2.400 971.650 2.680 ;
-        RECT 972.770 2.400 977.630 2.680 ;
-        RECT 978.750 2.400 983.610 2.680 ;
-        RECT 984.730 2.400 989.130 2.680 ;
-        RECT 990.250 2.400 995.110 2.680 ;
-        RECT 996.230 2.400 1001.090 2.680 ;
-        RECT 1002.210 2.400 1007.070 2.680 ;
-        RECT 1008.190 2.400 1013.050 2.680 ;
-        RECT 1014.170 2.400 1019.030 2.680 ;
-        RECT 1020.150 2.400 1025.010 2.680 ;
-        RECT 1026.130 2.400 1030.530 2.680 ;
-        RECT 1031.650 2.400 1036.510 2.680 ;
-        RECT 1037.630 2.400 1042.490 2.680 ;
-        RECT 1043.610 2.400 1048.470 2.680 ;
-        RECT 1049.590 2.400 1054.450 2.680 ;
-        RECT 1055.570 2.400 1060.430 2.680 ;
-        RECT 1061.550 2.400 1066.410 2.680 ;
-        RECT 1067.530 2.400 1071.930 2.680 ;
-        RECT 1073.050 2.400 1077.910 2.680 ;
-        RECT 1079.030 2.400 1083.890 2.680 ;
-        RECT 1085.010 2.400 1089.870 2.680 ;
-        RECT 1090.990 2.400 1095.850 2.680 ;
-        RECT 1096.970 2.400 1101.830 2.680 ;
-        RECT 1102.950 2.400 1107.350 2.680 ;
-        RECT 1108.470 2.400 1113.330 2.680 ;
-        RECT 1114.450 2.400 1119.310 2.680 ;
-        RECT 1120.430 2.400 1125.290 2.680 ;
-        RECT 1126.410 2.400 1131.270 2.680 ;
-        RECT 1132.390 2.400 1137.250 2.680 ;
-        RECT 1138.370 2.400 1143.230 2.680 ;
-        RECT 1144.350 2.400 1148.750 2.680 ;
-        RECT 1149.870 2.400 1154.730 2.680 ;
-        RECT 1155.850 2.400 1160.710 2.680 ;
-        RECT 1161.830 2.400 1166.690 2.680 ;
-        RECT 1167.810 2.400 1172.670 2.680 ;
-        RECT 1173.790 2.400 1178.650 2.680 ;
-        RECT 1179.770 2.400 1184.630 2.680 ;
-        RECT 1185.750 2.400 1190.150 2.680 ;
-        RECT 1191.270 2.400 1196.130 2.680 ;
-        RECT 1197.250 2.400 1202.110 2.680 ;
-        RECT 1203.230 2.400 1208.090 2.680 ;
-        RECT 1209.210 2.400 1214.070 2.680 ;
-        RECT 1215.190 2.400 1220.050 2.680 ;
-        RECT 1221.170 2.400 1225.570 2.680 ;
-        RECT 1226.690 2.400 1231.550 2.680 ;
-        RECT 1232.670 2.400 1237.530 2.680 ;
-        RECT 1238.650 2.400 1243.510 2.680 ;
-        RECT 1244.630 2.400 1249.490 2.680 ;
-        RECT 1250.610 2.400 1255.470 2.680 ;
-        RECT 1256.590 2.400 1261.450 2.680 ;
-        RECT 1262.570 2.400 1266.970 2.680 ;
-        RECT 1268.090 2.400 1272.950 2.680 ;
-        RECT 1274.070 2.400 1278.930 2.680 ;
-        RECT 1280.050 2.400 1284.910 2.680 ;
-        RECT 1286.030 2.400 1290.890 2.680 ;
-        RECT 1292.010 2.400 1296.870 2.680 ;
-        RECT 1297.990 2.400 1302.850 2.680 ;
-        RECT 1303.970 2.400 1308.370 2.680 ;
-        RECT 1309.490 2.400 1314.350 2.680 ;
-        RECT 1315.470 2.400 1320.330 2.680 ;
-        RECT 1321.450 2.400 1326.310 2.680 ;
-        RECT 1327.430 2.400 1332.290 2.680 ;
-        RECT 1333.410 2.400 1338.270 2.680 ;
-        RECT 1339.390 2.400 1343.790 2.680 ;
-        RECT 1344.910 2.400 1349.770 2.680 ;
-        RECT 1350.890 2.400 1355.750 2.680 ;
-        RECT 1356.870 2.400 1361.730 2.680 ;
-        RECT 1362.850 2.400 1367.710 2.680 ;
-        RECT 1368.830 2.400 1373.690 2.680 ;
-        RECT 1374.810 2.400 1379.670 2.680 ;
-        RECT 1380.790 2.400 1385.190 2.680 ;
-        RECT 1386.310 2.400 1391.170 2.680 ;
-        RECT 1392.290 2.400 1397.150 2.680 ;
-        RECT 1398.270 2.400 1403.130 2.680 ;
-        RECT 1404.250 2.400 1409.110 2.680 ;
-        RECT 1410.230 2.400 1415.090 2.680 ;
-        RECT 1416.210 2.400 1421.070 2.680 ;
-        RECT 1422.190 2.400 1426.590 2.680 ;
-        RECT 1427.710 2.400 1432.570 2.680 ;
-        RECT 1433.690 2.400 1438.550 2.680 ;
-        RECT 1439.670 2.400 1444.530 2.680 ;
-        RECT 1445.650 2.400 1450.510 2.680 ;
-        RECT 1451.630 2.400 1456.490 2.680 ;
-        RECT 1457.610 2.400 1462.470 2.680 ;
-        RECT 1463.590 2.400 1467.990 2.680 ;
-        RECT 1469.110 2.400 1473.970 2.680 ;
-        RECT 1475.090 2.400 1479.950 2.680 ;
-        RECT 1481.070 2.400 1485.930 2.680 ;
-        RECT 1487.050 2.400 1491.910 2.680 ;
-        RECT 1493.030 2.400 1497.890 2.680 ;
-        RECT 1499.010 2.400 1503.410 2.680 ;
-        RECT 1504.530 2.400 1509.390 2.680 ;
-        RECT 1510.510 2.400 1515.370 2.680 ;
-        RECT 1516.490 2.400 1521.350 2.680 ;
-        RECT 1522.470 2.400 1527.330 2.680 ;
-        RECT 1528.450 2.400 1533.310 2.680 ;
-        RECT 1534.430 2.400 1539.290 2.680 ;
-        RECT 1540.410 2.400 1544.810 2.680 ;
-        RECT 1545.930 2.400 1550.790 2.680 ;
-        RECT 1551.910 2.400 1556.770 2.680 ;
-        RECT 1557.890 2.400 1562.750 2.680 ;
-        RECT 1563.870 2.400 1568.730 2.680 ;
-        RECT 1569.850 2.400 1574.710 2.680 ;
-        RECT 1575.830 2.400 1580.690 2.680 ;
-        RECT 1581.810 2.400 1586.210 2.680 ;
-        RECT 1587.330 2.400 1592.190 2.680 ;
-        RECT 1593.310 2.400 1598.170 2.680 ;
-        RECT 1599.290 2.400 1604.150 2.680 ;
-        RECT 1605.270 2.400 1610.130 2.680 ;
-        RECT 1611.250 2.400 1616.110 2.680 ;
-        RECT 1617.230 2.400 1621.630 2.680 ;
-        RECT 1622.750 2.400 1627.610 2.680 ;
-        RECT 1628.730 2.400 1633.590 2.680 ;
-        RECT 1634.710 2.400 1639.570 2.680 ;
-        RECT 1640.690 2.400 1645.550 2.680 ;
-        RECT 1646.670 2.400 1651.530 2.680 ;
-        RECT 1652.650 2.400 1657.510 2.680 ;
-        RECT 1658.630 2.400 1663.030 2.680 ;
-        RECT 1664.150 2.400 1669.010 2.680 ;
-        RECT 1670.130 2.400 1674.990 2.680 ;
-        RECT 1676.110 2.400 1680.970 2.680 ;
-        RECT 1682.090 2.400 1686.950 2.680 ;
-        RECT 1688.070 2.400 1692.930 2.680 ;
-        RECT 1694.050 2.400 1698.910 2.680 ;
-        RECT 1700.030 2.400 1704.430 2.680 ;
-        RECT 1705.550 2.400 1710.410 2.680 ;
-        RECT 1711.530 2.400 1716.390 2.680 ;
-        RECT 1717.510 2.400 1722.370 2.680 ;
-        RECT 1723.490 2.400 1728.350 2.680 ;
-        RECT 1729.470 2.400 1734.330 2.680 ;
-        RECT 1735.450 2.400 1739.850 2.680 ;
-        RECT 1740.970 2.400 1745.830 2.680 ;
-        RECT 1746.950 2.400 1751.810 2.680 ;
-        RECT 1752.930 2.400 1757.790 2.680 ;
-        RECT 1758.910 2.400 1763.770 2.680 ;
-        RECT 1764.890 2.400 1769.750 2.680 ;
-        RECT 1770.870 2.400 1775.730 2.680 ;
-        RECT 1776.850 2.400 1781.250 2.680 ;
-        RECT 1782.370 2.400 1787.230 2.680 ;
-        RECT 1788.350 2.400 1793.210 2.680 ;
-        RECT 1794.330 2.400 1799.190 2.680 ;
-        RECT 1800.310 2.400 1805.170 2.680 ;
-        RECT 1806.290 2.400 1811.150 2.680 ;
-        RECT 1812.270 2.400 1817.130 2.680 ;
-        RECT 1818.250 2.400 1822.650 2.680 ;
-        RECT 1823.770 2.400 1828.630 2.680 ;
-        RECT 1829.750 2.400 1834.610 2.680 ;
-        RECT 1835.730 2.400 1840.590 2.680 ;
-        RECT 1841.710 2.400 1846.570 2.680 ;
-        RECT 1847.690 2.400 1852.550 2.680 ;
-        RECT 1853.670 2.400 1858.070 2.680 ;
-        RECT 1859.190 2.400 1864.050 2.680 ;
-        RECT 1865.170 2.400 1870.030 2.680 ;
-        RECT 1871.150 2.400 1876.010 2.680 ;
-        RECT 1877.130 2.400 1881.990 2.680 ;
-        RECT 1883.110 2.400 1887.970 2.680 ;
-        RECT 1889.090 2.400 1893.950 2.680 ;
-        RECT 1895.070 2.400 1899.470 2.680 ;
-        RECT 1900.590 2.400 1905.450 2.680 ;
-        RECT 1906.570 2.400 1911.430 2.680 ;
-        RECT 1912.550 2.400 1917.410 2.680 ;
-        RECT 1918.530 2.400 1923.390 2.680 ;
-        RECT 1924.510 2.400 1929.370 2.680 ;
-        RECT 1930.490 2.400 1935.350 2.680 ;
-        RECT 1936.470 2.400 1940.870 2.680 ;
-        RECT 1941.990 2.400 1946.850 2.680 ;
-        RECT 1947.970 2.400 1952.830 2.680 ;
-        RECT 1953.950 2.400 1958.810 2.680 ;
-        RECT 1959.930 2.400 1964.790 2.680 ;
-        RECT 1965.910 2.400 1970.770 2.680 ;
-        RECT 1971.890 2.400 1976.290 2.680 ;
-        RECT 1977.410 2.400 1982.270 2.680 ;
-        RECT 1983.390 2.400 1988.250 2.680 ;
-        RECT 1989.370 2.400 1994.230 2.680 ;
-        RECT 1995.350 2.400 2000.210 2.680 ;
-        RECT 2001.330 2.400 2006.190 2.680 ;
-        RECT 2007.310 2.400 2012.170 2.680 ;
-        RECT 2013.290 2.400 2017.690 2.680 ;
-        RECT 2018.810 2.400 2023.670 2.680 ;
-        RECT 2024.790 2.400 2029.650 2.680 ;
-        RECT 2030.770 2.400 2035.630 2.680 ;
-        RECT 2036.750 2.400 2041.610 2.680 ;
-        RECT 2042.730 2.400 2047.590 2.680 ;
-        RECT 2048.710 2.400 2053.570 2.680 ;
-        RECT 2054.690 2.400 2059.090 2.680 ;
-        RECT 2060.210 2.400 2065.070 2.680 ;
-        RECT 2066.190 2.400 2071.050 2.680 ;
-        RECT 2072.170 2.400 2077.030 2.680 ;
-        RECT 2078.150 2.400 2083.010 2.680 ;
-        RECT 2084.130 2.400 2088.990 2.680 ;
-        RECT 2090.110 2.400 2094.510 2.680 ;
-        RECT 2095.630 2.400 2100.490 2.680 ;
-        RECT 2101.610 2.400 2106.470 2.680 ;
-        RECT 2107.590 2.400 2112.450 2.680 ;
-        RECT 2113.570 2.400 2118.430 2.680 ;
-        RECT 2119.550 2.400 2124.410 2.680 ;
-        RECT 2125.530 2.400 2130.390 2.680 ;
-        RECT 2131.510 2.400 2135.910 2.680 ;
-        RECT 2137.030 2.400 2141.890 2.680 ;
-        RECT 2143.010 2.400 2147.870 2.680 ;
-        RECT 2148.990 2.400 2153.850 2.680 ;
-        RECT 2154.970 2.400 2159.830 2.680 ;
-        RECT 2160.950 2.400 2165.810 2.680 ;
-        RECT 2166.930 2.400 2171.790 2.680 ;
-        RECT 2172.910 2.400 2177.310 2.680 ;
-        RECT 2178.430 2.400 2183.290 2.680 ;
-        RECT 2184.410 2.400 2189.270 2.680 ;
-        RECT 2190.390 2.400 2195.250 2.680 ;
-        RECT 2196.370 2.400 2201.230 2.680 ;
-        RECT 2202.350 2.400 2207.210 2.680 ;
-        RECT 2208.330 2.400 2212.730 2.680 ;
-        RECT 2213.850 2.400 2218.710 2.680 ;
-        RECT 2219.830 2.400 2224.690 2.680 ;
-        RECT 2225.810 2.400 2230.670 2.680 ;
-        RECT 2231.790 2.400 2236.650 2.680 ;
-        RECT 2237.770 2.400 2242.630 2.680 ;
-        RECT 2243.750 2.400 2248.610 2.680 ;
-        RECT 2249.730 2.400 2254.130 2.680 ;
-        RECT 2255.250 2.400 2260.110 2.680 ;
-        RECT 2261.230 2.400 2266.090 2.680 ;
-        RECT 2267.210 2.400 2272.070 2.680 ;
-        RECT 2273.190 2.400 2278.050 2.680 ;
-        RECT 2279.170 2.400 2284.030 2.680 ;
-        RECT 2285.150 2.400 2290.010 2.680 ;
-        RECT 2291.130 2.400 2295.530 2.680 ;
-        RECT 2296.650 2.400 2301.510 2.680 ;
-        RECT 2302.630 2.400 2307.490 2.680 ;
-        RECT 2308.610 2.400 2313.470 2.680 ;
-        RECT 2314.590 2.400 2319.450 2.680 ;
-        RECT 2320.570 2.400 2325.430 2.680 ;
-        RECT 2326.550 2.400 2330.950 2.680 ;
-        RECT 2332.070 2.400 2336.930 2.680 ;
-        RECT 2338.050 2.400 2342.910 2.680 ;
-        RECT 2344.030 2.400 2348.890 2.680 ;
-        RECT 2350.010 2.400 2354.870 2.680 ;
-        RECT 2355.990 2.400 2360.850 2.680 ;
-        RECT 2361.970 2.400 2366.830 2.680 ;
-        RECT 2367.950 2.400 2372.350 2.680 ;
-        RECT 2373.470 2.400 2378.330 2.680 ;
-        RECT 2379.450 2.400 2384.310 2.680 ;
-        RECT 2385.430 2.400 2390.290 2.680 ;
-        RECT 2391.410 2.400 2396.270 2.680 ;
-        RECT 2397.390 2.400 2402.250 2.680 ;
-        RECT 2403.370 2.400 2408.230 2.680 ;
-        RECT 2409.350 2.400 2413.750 2.680 ;
-        RECT 2414.870 2.400 2419.730 2.680 ;
-        RECT 2420.850 2.400 2425.710 2.680 ;
-        RECT 2426.830 2.400 2431.690 2.680 ;
-        RECT 2432.810 2.400 2437.670 2.680 ;
-        RECT 2438.790 2.400 2443.650 2.680 ;
-        RECT 2444.770 2.400 2449.170 2.680 ;
-        RECT 2450.290 2.400 2455.150 2.680 ;
-        RECT 2456.270 2.400 2461.130 2.680 ;
-        RECT 2462.250 2.400 2467.110 2.680 ;
-        RECT 2468.230 2.400 2473.090 2.680 ;
-        RECT 2474.210 2.400 2479.070 2.680 ;
-        RECT 2480.190 2.400 2485.050 2.680 ;
-        RECT 2486.170 2.400 2490.570 2.680 ;
-        RECT 2491.690 2.400 2496.550 2.680 ;
-        RECT 2497.670 2.400 2502.530 2.680 ;
-        RECT 2503.650 2.400 2508.510 2.680 ;
-        RECT 2509.630 2.400 2514.490 2.680 ;
-        RECT 2515.610 2.400 2520.470 2.680 ;
-        RECT 2521.590 2.400 2526.450 2.680 ;
-        RECT 2527.570 2.400 2531.970 2.680 ;
-        RECT 2533.090 2.400 2537.950 2.680 ;
-        RECT 2539.070 2.400 2543.930 2.680 ;
-        RECT 2545.050 2.400 2549.910 2.680 ;
-        RECT 2551.030 2.400 2555.890 2.680 ;
-        RECT 2557.010 2.400 2561.870 2.680 ;
-        RECT 2562.990 2.400 2567.390 2.680 ;
-        RECT 2568.510 2.400 2573.370 2.680 ;
-        RECT 2574.490 2.400 2579.350 2.680 ;
-        RECT 2580.470 2.400 2585.330 2.680 ;
-        RECT 2586.450 2.400 2591.310 2.680 ;
-        RECT 2592.430 2.400 2597.290 2.680 ;
-        RECT 2598.410 2.400 2603.270 2.680 ;
-        RECT 2604.390 2.400 2608.790 2.680 ;
-        RECT 2609.910 2.400 2614.770 2.680 ;
-        RECT 2615.890 2.400 2620.750 2.680 ;
-        RECT 2621.870 2.400 2626.730 2.680 ;
-        RECT 2627.850 2.400 2632.710 2.680 ;
-        RECT 2633.830 2.400 2638.690 2.680 ;
-        RECT 2639.810 2.400 2644.670 2.680 ;
-        RECT 2645.790 2.400 2650.190 2.680 ;
-        RECT 2651.310 2.400 2656.170 2.680 ;
-        RECT 2657.290 2.400 2662.150 2.680 ;
-        RECT 2663.270 2.400 2668.130 2.680 ;
-        RECT 2669.250 2.400 2674.110 2.680 ;
-        RECT 2675.230 2.400 2680.090 2.680 ;
-        RECT 2681.210 2.400 2685.610 2.680 ;
-        RECT 2686.730 2.400 2691.590 2.680 ;
-        RECT 2692.710 2.400 2697.570 2.680 ;
-        RECT 2698.690 2.400 2703.550 2.680 ;
-        RECT 2704.670 2.400 2709.530 2.680 ;
-        RECT 2710.650 2.400 2715.510 2.680 ;
-        RECT 2716.630 2.400 2721.490 2.680 ;
-        RECT 2722.610 2.400 2727.010 2.680 ;
-        RECT 2728.130 2.400 2732.990 2.680 ;
-        RECT 2734.110 2.400 2738.970 2.680 ;
-        RECT 2740.090 2.400 2744.950 2.680 ;
-        RECT 2746.070 2.400 2750.930 2.680 ;
-        RECT 2752.050 2.400 2756.910 2.680 ;
-        RECT 2758.030 2.400 2762.890 2.680 ;
-        RECT 2764.010 2.400 2768.410 2.680 ;
-        RECT 2769.530 2.400 2774.390 2.680 ;
-        RECT 2775.510 2.400 2780.370 2.680 ;
-        RECT 2781.490 2.400 2786.350 2.680 ;
-        RECT 2787.470 2.400 2792.330 2.680 ;
-        RECT 2793.450 2.400 2798.310 2.680 ;
-        RECT 2799.430 2.400 2803.830 2.680 ;
-        RECT 2804.950 2.400 2809.810 2.680 ;
-        RECT 2810.930 2.400 2815.790 2.680 ;
-        RECT 2816.910 2.400 2821.770 2.680 ;
-        RECT 2822.890 2.400 2827.750 2.680 ;
-        RECT 2828.870 2.400 2833.730 2.680 ;
-        RECT 2834.850 2.400 2839.710 2.680 ;
-        RECT 2840.830 2.400 2845.230 2.680 ;
-        RECT 2846.350 2.400 2851.210 2.680 ;
-        RECT 2852.330 2.400 2857.190 2.680 ;
-        RECT 2858.310 2.400 2863.170 2.680 ;
-        RECT 2864.290 2.400 2869.150 2.680 ;
-        RECT 2870.270 2.400 2875.130 2.680 ;
-        RECT 2876.250 2.400 2881.110 2.680 ;
-        RECT 2882.230 2.400 2886.630 2.680 ;
-        RECT 2887.750 2.400 2892.610 2.680 ;
-        RECT 2893.730 2.400 2898.590 2.680 ;
-        RECT 2899.710 2.400 2904.570 2.680 ;
-        RECT 2905.690 2.400 2910.550 2.680 ;
-        RECT 2911.670 2.400 2916.530 2.680 ;
+        RECT 3.550 0.010 7.950 2.680 ;
+        RECT 9.070 0.010 13.930 2.680 ;
+        RECT 15.050 0.010 19.910 2.680 ;
+        RECT 21.030 0.010 25.890 2.680 ;
+        RECT 27.010 0.010 31.870 2.680 ;
+        RECT 32.990 0.010 37.850 2.680 ;
+        RECT 38.970 0.010 43.370 2.680 ;
+        RECT 44.490 0.010 49.350 2.680 ;
+        RECT 50.470 0.010 55.330 2.680 ;
+        RECT 56.450 0.010 61.310 2.680 ;
+        RECT 62.430 0.010 67.290 2.680 ;
+        RECT 68.410 0.010 73.270 2.680 ;
+        RECT 74.390 0.010 79.250 2.680 ;
+        RECT 80.370 0.010 84.770 2.680 ;
+        RECT 85.890 0.010 90.750 2.680 ;
+        RECT 91.870 0.010 96.730 2.680 ;
+        RECT 97.850 0.010 102.710 2.680 ;
+        RECT 103.830 0.010 108.690 2.680 ;
+        RECT 109.810 0.010 114.670 2.680 ;
+        RECT 115.790 0.010 120.650 2.680 ;
+        RECT 121.770 0.010 126.170 2.680 ;
+        RECT 127.290 0.010 132.150 2.680 ;
+        RECT 133.270 0.010 138.130 2.680 ;
+        RECT 139.250 0.010 144.110 2.680 ;
+        RECT 145.230 0.010 150.090 2.680 ;
+        RECT 151.210 0.010 156.070 2.680 ;
+        RECT 157.190 0.010 161.590 2.680 ;
+        RECT 162.710 0.010 167.570 2.680 ;
+        RECT 168.690 0.010 173.550 2.680 ;
+        RECT 174.670 0.010 179.530 2.680 ;
+        RECT 180.650 0.010 185.510 2.680 ;
+        RECT 186.630 0.010 191.490 2.680 ;
+        RECT 192.610 0.010 197.470 2.680 ;
+        RECT 198.590 0.010 202.990 2.680 ;
+        RECT 204.110 0.010 208.970 2.680 ;
+        RECT 210.090 0.010 214.950 2.680 ;
+        RECT 216.070 0.010 220.930 2.680 ;
+        RECT 222.050 0.010 226.910 2.680 ;
+        RECT 228.030 0.010 232.890 2.680 ;
+        RECT 234.010 0.010 238.870 2.680 ;
+        RECT 239.990 0.010 244.390 2.680 ;
+        RECT 245.510 0.010 250.370 2.680 ;
+        RECT 251.490 0.010 256.350 2.680 ;
+        RECT 257.470 0.010 262.330 2.680 ;
+        RECT 263.450 0.010 268.310 2.680 ;
+        RECT 269.430 0.010 274.290 2.680 ;
+        RECT 275.410 0.010 279.810 2.680 ;
+        RECT 280.930 0.010 285.790 2.680 ;
+        RECT 286.910 0.010 291.770 2.680 ;
+        RECT 292.890 0.010 297.750 2.680 ;
+        RECT 298.870 0.010 303.730 2.680 ;
+        RECT 304.850 0.010 309.710 2.680 ;
+        RECT 310.830 0.010 315.690 2.680 ;
+        RECT 316.810 0.010 321.210 2.680 ;
+        RECT 322.330 0.010 327.190 2.680 ;
+        RECT 328.310 0.010 333.170 2.680 ;
+        RECT 334.290 0.010 339.150 2.680 ;
+        RECT 340.270 0.010 345.130 2.680 ;
+        RECT 346.250 0.010 351.110 2.680 ;
+        RECT 352.230 0.010 357.090 2.680 ;
+        RECT 358.210 0.010 362.610 2.680 ;
+        RECT 363.730 0.010 368.590 2.680 ;
+        RECT 369.710 0.010 374.570 2.680 ;
+        RECT 375.690 0.010 380.550 2.680 ;
+        RECT 381.670 0.010 386.530 2.680 ;
+        RECT 387.650 0.010 392.510 2.680 ;
+        RECT 393.630 0.010 398.030 2.680 ;
+        RECT 399.150 0.010 404.010 2.680 ;
+        RECT 405.130 0.010 409.990 2.680 ;
+        RECT 411.110 0.010 415.970 2.680 ;
+        RECT 417.090 0.010 421.950 2.680 ;
+        RECT 423.070 0.010 427.930 2.680 ;
+        RECT 429.050 0.010 433.910 2.680 ;
+        RECT 435.030 0.010 439.430 2.680 ;
+        RECT 440.550 0.010 445.410 2.680 ;
+        RECT 446.530 0.010 451.390 2.680 ;
+        RECT 452.510 0.010 457.370 2.680 ;
+        RECT 458.490 0.010 463.350 2.680 ;
+        RECT 464.470 0.010 469.330 2.680 ;
+        RECT 470.450 0.010 475.310 2.680 ;
+        RECT 476.430 0.010 480.830 2.680 ;
+        RECT 481.950 0.010 486.810 2.680 ;
+        RECT 487.930 0.010 492.790 2.680 ;
+        RECT 493.910 0.010 498.770 2.680 ;
+        RECT 499.890 0.010 504.750 2.680 ;
+        RECT 505.870 0.010 510.730 2.680 ;
+        RECT 511.850 0.010 516.250 2.680 ;
+        RECT 517.370 0.010 522.230 2.680 ;
+        RECT 523.350 0.010 528.210 2.680 ;
+        RECT 529.330 0.010 534.190 2.680 ;
+        RECT 535.310 0.010 540.170 2.680 ;
+        RECT 541.290 0.010 546.150 2.680 ;
+        RECT 547.270 0.010 552.130 2.680 ;
+        RECT 553.250 0.010 557.650 2.680 ;
+        RECT 558.770 0.010 563.630 2.680 ;
+        RECT 564.750 0.010 569.610 2.680 ;
+        RECT 570.730 0.010 575.590 2.680 ;
+        RECT 576.710 0.010 581.570 2.680 ;
+        RECT 582.690 0.010 587.550 2.680 ;
+        RECT 588.670 0.010 593.530 2.680 ;
+        RECT 594.650 0.010 599.050 2.680 ;
+        RECT 600.170 0.010 605.030 2.680 ;
+        RECT 606.150 0.010 611.010 2.680 ;
+        RECT 612.130 0.010 616.990 2.680 ;
+        RECT 618.110 0.010 622.970 2.680 ;
+        RECT 624.090 0.010 628.950 2.680 ;
+        RECT 630.070 0.010 634.470 2.680 ;
+        RECT 635.590 0.010 640.450 2.680 ;
+        RECT 641.570 0.010 646.430 2.680 ;
+        RECT 647.550 0.010 652.410 2.680 ;
+        RECT 653.530 0.010 658.390 2.680 ;
+        RECT 659.510 0.010 664.370 2.680 ;
+        RECT 665.490 0.010 670.350 2.680 ;
+        RECT 671.470 0.010 675.870 2.680 ;
+        RECT 676.990 0.010 681.850 2.680 ;
+        RECT 682.970 0.010 687.830 2.680 ;
+        RECT 688.950 0.010 693.810 2.680 ;
+        RECT 694.930 0.010 699.790 2.680 ;
+        RECT 700.910 0.010 705.770 2.680 ;
+        RECT 706.890 0.010 711.750 2.680 ;
+        RECT 712.870 0.010 717.270 2.680 ;
+        RECT 718.390 0.010 723.250 2.680 ;
+        RECT 724.370 0.010 729.230 2.680 ;
+        RECT 730.350 0.010 735.210 2.680 ;
+        RECT 736.330 0.010 741.190 2.680 ;
+        RECT 742.310 0.010 747.170 2.680 ;
+        RECT 748.290 0.010 752.690 2.680 ;
+        RECT 753.810 0.010 758.670 2.680 ;
+        RECT 759.790 0.010 764.650 2.680 ;
+        RECT 765.770 0.010 770.630 2.680 ;
+        RECT 771.750 0.010 776.610 2.680 ;
+        RECT 777.730 0.010 782.590 2.680 ;
+        RECT 783.710 0.010 788.570 2.680 ;
+        RECT 789.690 0.010 794.090 2.680 ;
+        RECT 795.210 0.010 800.070 2.680 ;
+        RECT 801.190 0.010 806.050 2.680 ;
+        RECT 807.170 0.010 812.030 2.680 ;
+        RECT 813.150 0.010 818.010 2.680 ;
+        RECT 819.130 0.010 823.990 2.680 ;
+        RECT 825.110 0.010 829.970 2.680 ;
+        RECT 831.090 0.010 835.490 2.680 ;
+        RECT 836.610 0.010 841.470 2.680 ;
+        RECT 842.590 0.010 847.450 2.680 ;
+        RECT 848.570 0.010 853.430 2.680 ;
+        RECT 854.550 0.010 859.410 2.680 ;
+        RECT 860.530 0.010 865.390 2.680 ;
+        RECT 866.510 0.010 870.910 2.680 ;
+        RECT 872.030 0.010 876.890 2.680 ;
+        RECT 878.010 0.010 882.870 2.680 ;
+        RECT 883.990 0.010 888.850 2.680 ;
+        RECT 889.970 0.010 894.830 2.680 ;
+        RECT 895.950 0.010 900.810 2.680 ;
+        RECT 901.930 0.010 906.790 2.680 ;
+        RECT 907.910 0.010 912.310 2.680 ;
+        RECT 913.430 0.010 918.290 2.680 ;
+        RECT 919.410 0.010 924.270 2.680 ;
+        RECT 925.390 0.010 930.250 2.680 ;
+        RECT 931.370 0.010 936.230 2.680 ;
+        RECT 937.350 0.010 942.210 2.680 ;
+        RECT 943.330 0.010 948.190 2.680 ;
+        RECT 949.310 0.010 953.710 2.680 ;
+        RECT 954.830 0.010 959.690 2.680 ;
+        RECT 960.810 0.010 965.670 2.680 ;
+        RECT 966.790 0.010 971.650 2.680 ;
+        RECT 972.770 0.010 977.630 2.680 ;
+        RECT 978.750 0.010 983.610 2.680 ;
+        RECT 984.730 0.010 989.130 2.680 ;
+        RECT 990.250 0.010 995.110 2.680 ;
+        RECT 996.230 0.010 1001.090 2.680 ;
+        RECT 1002.210 0.010 1007.070 2.680 ;
+        RECT 1008.190 0.010 1013.050 2.680 ;
+        RECT 1014.170 0.010 1019.030 2.680 ;
+        RECT 1020.150 0.010 1025.010 2.680 ;
+        RECT 1026.130 0.010 1030.530 2.680 ;
+        RECT 1031.650 0.010 1036.510 2.680 ;
+        RECT 1037.630 0.010 1042.490 2.680 ;
+        RECT 1043.610 0.010 1048.470 2.680 ;
+        RECT 1049.590 0.010 1054.450 2.680 ;
+        RECT 1055.570 0.010 1060.430 2.680 ;
+        RECT 1061.550 0.010 1066.410 2.680 ;
+        RECT 1067.530 0.010 1071.930 2.680 ;
+        RECT 1073.050 0.010 1077.910 2.680 ;
+        RECT 1079.030 0.010 1083.890 2.680 ;
+        RECT 1085.010 0.010 1089.870 2.680 ;
+        RECT 1090.990 0.010 1095.850 2.680 ;
+        RECT 1096.970 0.010 1101.830 2.680 ;
+        RECT 1102.950 0.010 1107.350 2.680 ;
+        RECT 1108.470 0.010 1113.330 2.680 ;
+        RECT 1114.450 0.010 1119.310 2.680 ;
+        RECT 1120.430 0.010 1125.290 2.680 ;
+        RECT 1126.410 0.010 1131.270 2.680 ;
+        RECT 1132.390 0.010 1137.250 2.680 ;
+        RECT 1138.370 0.010 1143.230 2.680 ;
+        RECT 1144.350 0.010 1148.750 2.680 ;
+        RECT 1149.870 0.010 1154.730 2.680 ;
+        RECT 1155.850 0.010 1160.710 2.680 ;
+        RECT 1161.830 0.010 1166.690 2.680 ;
+        RECT 1167.810 0.010 1172.670 2.680 ;
+        RECT 1173.790 0.010 1178.650 2.680 ;
+        RECT 1179.770 0.010 1184.630 2.680 ;
+        RECT 1185.750 0.010 1190.150 2.680 ;
+        RECT 1191.270 0.010 1196.130 2.680 ;
+        RECT 1197.250 0.010 1202.110 2.680 ;
+        RECT 1203.230 0.010 1208.090 2.680 ;
+        RECT 1209.210 0.010 1214.070 2.680 ;
+        RECT 1215.190 0.010 1220.050 2.680 ;
+        RECT 1221.170 0.010 1225.570 2.680 ;
+        RECT 1226.690 0.010 1231.550 2.680 ;
+        RECT 1232.670 0.010 1237.530 2.680 ;
+        RECT 1238.650 0.010 1243.510 2.680 ;
+        RECT 1244.630 0.010 1249.490 2.680 ;
+        RECT 1250.610 0.010 1255.470 2.680 ;
+        RECT 1256.590 0.010 1261.450 2.680 ;
+        RECT 1262.570 0.010 1266.970 2.680 ;
+        RECT 1268.090 0.010 1272.950 2.680 ;
+        RECT 1274.070 0.010 1278.930 2.680 ;
+        RECT 1280.050 0.010 1284.910 2.680 ;
+        RECT 1286.030 0.010 1290.890 2.680 ;
+        RECT 1292.010 0.010 1296.870 2.680 ;
+        RECT 1297.990 0.010 1302.850 2.680 ;
+        RECT 1303.970 0.010 1308.370 2.680 ;
+        RECT 1309.490 0.010 1314.350 2.680 ;
+        RECT 1315.470 0.010 1320.330 2.680 ;
+        RECT 1321.450 0.010 1326.310 2.680 ;
+        RECT 1327.430 0.010 1332.290 2.680 ;
+        RECT 1333.410 0.010 1338.270 2.680 ;
+        RECT 1339.390 0.010 1343.790 2.680 ;
+        RECT 1344.910 0.010 1349.770 2.680 ;
+        RECT 1350.890 0.010 1355.750 2.680 ;
+        RECT 1356.870 0.010 1361.730 2.680 ;
+        RECT 1362.850 0.010 1367.710 2.680 ;
+        RECT 1368.830 0.010 1373.690 2.680 ;
+        RECT 1374.810 0.010 1379.670 2.680 ;
+        RECT 1380.790 0.010 1385.190 2.680 ;
+        RECT 1386.310 0.010 1391.170 2.680 ;
+        RECT 1392.290 0.010 1397.150 2.680 ;
+        RECT 1398.270 0.010 1403.130 2.680 ;
+        RECT 1404.250 0.010 1409.110 2.680 ;
+        RECT 1410.230 0.010 1415.090 2.680 ;
+        RECT 1416.210 0.010 1421.070 2.680 ;
+        RECT 1422.190 0.010 1426.590 2.680 ;
+        RECT 1427.710 0.010 1432.570 2.680 ;
+        RECT 1433.690 0.010 1438.550 2.680 ;
+        RECT 1439.670 0.010 1444.530 2.680 ;
+        RECT 1445.650 0.010 1450.510 2.680 ;
+        RECT 1451.630 0.010 1456.490 2.680 ;
+        RECT 1457.610 0.010 1462.470 2.680 ;
+        RECT 1463.590 0.010 1467.990 2.680 ;
+        RECT 1469.110 0.010 1473.970 2.680 ;
+        RECT 1475.090 0.010 1479.950 2.680 ;
+        RECT 1481.070 0.010 1485.930 2.680 ;
+        RECT 1487.050 0.010 1491.910 2.680 ;
+        RECT 1493.030 0.010 1497.890 2.680 ;
+        RECT 1499.010 0.010 1503.410 2.680 ;
+        RECT 1504.530 0.010 1509.390 2.680 ;
+        RECT 1510.510 0.010 1515.370 2.680 ;
+        RECT 1516.490 0.010 1521.350 2.680 ;
+        RECT 1522.470 0.010 1527.330 2.680 ;
+        RECT 1528.450 0.010 1533.310 2.680 ;
+        RECT 1534.430 0.010 1539.290 2.680 ;
+        RECT 1540.410 0.010 1544.810 2.680 ;
+        RECT 1545.930 0.010 1550.790 2.680 ;
+        RECT 1551.910 0.010 1556.770 2.680 ;
+        RECT 1557.890 0.010 1562.750 2.680 ;
+        RECT 1563.870 0.010 1568.730 2.680 ;
+        RECT 1569.850 0.010 1574.710 2.680 ;
+        RECT 1575.830 0.010 1580.690 2.680 ;
+        RECT 1581.810 0.010 1586.210 2.680 ;
+        RECT 1587.330 0.010 1592.190 2.680 ;
+        RECT 1593.310 0.010 1598.170 2.680 ;
+        RECT 1599.290 0.010 1604.150 2.680 ;
+        RECT 1605.270 0.010 1610.130 2.680 ;
+        RECT 1611.250 0.010 1616.110 2.680 ;
+        RECT 1617.230 0.010 1621.630 2.680 ;
+        RECT 1622.750 0.010 1627.610 2.680 ;
+        RECT 1628.730 0.010 1633.590 2.680 ;
+        RECT 1634.710 0.010 1639.570 2.680 ;
+        RECT 1640.690 0.010 1645.550 2.680 ;
+        RECT 1646.670 0.010 1651.530 2.680 ;
+        RECT 1652.650 0.010 1657.510 2.680 ;
+        RECT 1658.630 0.010 1663.030 2.680 ;
+        RECT 1664.150 0.010 1669.010 2.680 ;
+        RECT 1670.130 0.010 1674.990 2.680 ;
+        RECT 1676.110 0.010 1680.970 2.680 ;
+        RECT 1682.090 0.010 1686.950 2.680 ;
+        RECT 1688.070 0.010 1692.930 2.680 ;
+        RECT 1694.050 0.010 1698.910 2.680 ;
+        RECT 1700.030 0.010 1704.430 2.680 ;
+        RECT 1705.550 0.010 1710.410 2.680 ;
+        RECT 1711.530 0.010 1716.390 2.680 ;
+        RECT 1717.510 0.010 1722.370 2.680 ;
+        RECT 1723.490 0.010 1728.350 2.680 ;
+        RECT 1729.470 0.010 1734.330 2.680 ;
+        RECT 1735.450 0.010 1739.850 2.680 ;
+        RECT 1740.970 0.010 1745.830 2.680 ;
+        RECT 1746.950 0.010 1751.810 2.680 ;
+        RECT 1752.930 0.010 1757.790 2.680 ;
+        RECT 1758.910 0.010 1763.770 2.680 ;
+        RECT 1764.890 0.010 1769.750 2.680 ;
+        RECT 1770.870 0.010 1775.730 2.680 ;
+        RECT 1776.850 0.010 1781.250 2.680 ;
+        RECT 1782.370 0.010 1787.230 2.680 ;
+        RECT 1788.350 0.010 1793.210 2.680 ;
+        RECT 1794.330 0.010 1799.190 2.680 ;
+        RECT 1800.310 0.010 1805.170 2.680 ;
+        RECT 1806.290 0.010 1811.150 2.680 ;
+        RECT 1812.270 0.010 1817.130 2.680 ;
+        RECT 1818.250 0.010 1822.650 2.680 ;
+        RECT 1823.770 0.010 1828.630 2.680 ;
+        RECT 1829.750 0.010 1834.610 2.680 ;
+        RECT 1835.730 0.010 1840.590 2.680 ;
+        RECT 1841.710 0.010 1846.570 2.680 ;
+        RECT 1847.690 0.010 1852.550 2.680 ;
+        RECT 1853.670 0.010 1858.070 2.680 ;
+        RECT 1859.190 0.010 1864.050 2.680 ;
+        RECT 1865.170 0.010 1870.030 2.680 ;
+        RECT 1871.150 0.010 1876.010 2.680 ;
+        RECT 1877.130 0.010 1881.990 2.680 ;
+        RECT 1883.110 0.010 1887.970 2.680 ;
+        RECT 1889.090 0.010 1893.950 2.680 ;
+        RECT 1895.070 0.010 1899.470 2.680 ;
+        RECT 1900.590 0.010 1905.450 2.680 ;
+        RECT 1906.570 0.010 1911.430 2.680 ;
+        RECT 1912.550 0.010 1917.410 2.680 ;
+        RECT 1918.530 0.010 1923.390 2.680 ;
+        RECT 1924.510 0.010 1929.370 2.680 ;
+        RECT 1930.490 0.010 1935.350 2.680 ;
+        RECT 1936.470 0.010 1940.870 2.680 ;
+        RECT 1941.990 0.010 1946.850 2.680 ;
+        RECT 1947.970 0.010 1952.830 2.680 ;
+        RECT 1953.950 0.010 1958.810 2.680 ;
+        RECT 1959.930 0.010 1964.790 2.680 ;
+        RECT 1965.910 0.010 1970.770 2.680 ;
+        RECT 1971.890 0.010 1976.290 2.680 ;
+        RECT 1977.410 0.010 1982.270 2.680 ;
+        RECT 1983.390 0.010 1988.250 2.680 ;
+        RECT 1989.370 0.010 1994.230 2.680 ;
+        RECT 1995.350 0.010 2000.210 2.680 ;
+        RECT 2001.330 0.010 2006.190 2.680 ;
+        RECT 2007.310 0.010 2012.170 2.680 ;
+        RECT 2013.290 0.010 2017.690 2.680 ;
+        RECT 2018.810 0.010 2023.670 2.680 ;
+        RECT 2024.790 0.010 2029.650 2.680 ;
+        RECT 2030.770 0.010 2035.630 2.680 ;
+        RECT 2036.750 0.010 2041.610 2.680 ;
+        RECT 2042.730 0.010 2047.590 2.680 ;
+        RECT 2048.710 0.010 2053.570 2.680 ;
+        RECT 2054.690 0.010 2059.090 2.680 ;
+        RECT 2060.210 0.010 2065.070 2.680 ;
+        RECT 2066.190 0.010 2071.050 2.680 ;
+        RECT 2072.170 0.010 2077.030 2.680 ;
+        RECT 2078.150 0.010 2083.010 2.680 ;
+        RECT 2084.130 0.010 2088.990 2.680 ;
+        RECT 2090.110 0.010 2094.510 2.680 ;
+        RECT 2095.630 0.010 2100.490 2.680 ;
+        RECT 2101.610 0.010 2106.470 2.680 ;
+        RECT 2107.590 0.010 2112.450 2.680 ;
+        RECT 2113.570 0.010 2118.430 2.680 ;
+        RECT 2119.550 0.010 2124.410 2.680 ;
+        RECT 2125.530 0.010 2130.390 2.680 ;
+        RECT 2131.510 0.010 2135.910 2.680 ;
+        RECT 2137.030 0.010 2141.890 2.680 ;
+        RECT 2143.010 0.010 2147.870 2.680 ;
+        RECT 2148.990 0.010 2153.850 2.680 ;
+        RECT 2154.970 0.010 2159.830 2.680 ;
+        RECT 2160.950 0.010 2165.810 2.680 ;
+        RECT 2166.930 0.010 2171.790 2.680 ;
+        RECT 2172.910 0.010 2177.310 2.680 ;
+        RECT 2178.430 0.010 2183.290 2.680 ;
+        RECT 2184.410 0.010 2189.270 2.680 ;
+        RECT 2190.390 0.010 2195.250 2.680 ;
+        RECT 2196.370 0.010 2201.230 2.680 ;
+        RECT 2202.350 0.010 2207.210 2.680 ;
+        RECT 2208.330 0.010 2212.730 2.680 ;
+        RECT 2213.850 0.010 2218.710 2.680 ;
+        RECT 2219.830 0.010 2224.690 2.680 ;
+        RECT 2225.810 0.010 2230.670 2.680 ;
+        RECT 2231.790 0.010 2236.650 2.680 ;
+        RECT 2237.770 0.010 2242.630 2.680 ;
+        RECT 2243.750 0.010 2248.610 2.680 ;
+        RECT 2249.730 0.010 2254.130 2.680 ;
+        RECT 2255.250 0.010 2260.110 2.680 ;
+        RECT 2261.230 0.010 2266.090 2.680 ;
+        RECT 2267.210 0.010 2272.070 2.680 ;
+        RECT 2273.190 0.010 2278.050 2.680 ;
+        RECT 2279.170 0.010 2284.030 2.680 ;
+        RECT 2285.150 0.010 2290.010 2.680 ;
+        RECT 2291.130 0.010 2295.530 2.680 ;
+        RECT 2296.650 0.010 2301.510 2.680 ;
+        RECT 2302.630 0.010 2307.490 2.680 ;
+        RECT 2308.610 0.010 2313.470 2.680 ;
+        RECT 2314.590 0.010 2319.450 2.680 ;
+        RECT 2320.570 0.010 2325.430 2.680 ;
+        RECT 2326.550 0.010 2330.950 2.680 ;
+        RECT 2332.070 0.010 2336.930 2.680 ;
+        RECT 2338.050 0.010 2342.910 2.680 ;
+        RECT 2344.030 0.010 2348.890 2.680 ;
+        RECT 2350.010 0.010 2354.870 2.680 ;
+        RECT 2355.990 0.010 2360.850 2.680 ;
+        RECT 2361.970 0.010 2366.830 2.680 ;
+        RECT 2367.950 0.010 2372.350 2.680 ;
+        RECT 2373.470 0.010 2378.330 2.680 ;
+        RECT 2379.450 0.010 2384.310 2.680 ;
+        RECT 2385.430 0.010 2390.290 2.680 ;
+        RECT 2391.410 0.010 2396.270 2.680 ;
+        RECT 2397.390 0.010 2402.250 2.680 ;
+        RECT 2403.370 0.010 2408.230 2.680 ;
+        RECT 2409.350 0.010 2413.750 2.680 ;
+        RECT 2414.870 0.010 2419.730 2.680 ;
+        RECT 2420.850 0.010 2425.710 2.680 ;
+        RECT 2426.830 0.010 2431.690 2.680 ;
+        RECT 2432.810 0.010 2437.670 2.680 ;
+        RECT 2438.790 0.010 2443.650 2.680 ;
+        RECT 2444.770 0.010 2449.170 2.680 ;
+        RECT 2450.290 0.010 2455.150 2.680 ;
+        RECT 2456.270 0.010 2461.130 2.680 ;
+        RECT 2462.250 0.010 2467.110 2.680 ;
+        RECT 2468.230 0.010 2473.090 2.680 ;
+        RECT 2474.210 0.010 2479.070 2.680 ;
+        RECT 2480.190 0.010 2485.050 2.680 ;
+        RECT 2486.170 0.010 2490.570 2.680 ;
+        RECT 2491.690 0.010 2496.550 2.680 ;
+        RECT 2497.670 0.010 2502.530 2.680 ;
+        RECT 2503.650 0.010 2508.510 2.680 ;
+        RECT 2509.630 0.010 2514.490 2.680 ;
+        RECT 2515.610 0.010 2520.470 2.680 ;
+        RECT 2521.590 0.010 2526.450 2.680 ;
+        RECT 2527.570 0.010 2531.970 2.680 ;
+        RECT 2533.090 0.010 2537.950 2.680 ;
+        RECT 2539.070 0.010 2543.930 2.680 ;
+        RECT 2545.050 0.010 2549.910 2.680 ;
+        RECT 2551.030 0.010 2555.890 2.680 ;
+        RECT 2557.010 0.010 2561.870 2.680 ;
+        RECT 2562.990 0.010 2567.390 2.680 ;
+        RECT 2568.510 0.010 2573.370 2.680 ;
+        RECT 2574.490 0.010 2579.350 2.680 ;
+        RECT 2580.470 0.010 2585.330 2.680 ;
+        RECT 2586.450 0.010 2591.310 2.680 ;
+        RECT 2592.430 0.010 2597.290 2.680 ;
+        RECT 2598.410 0.010 2603.270 2.680 ;
+        RECT 2604.390 0.010 2608.790 2.680 ;
+        RECT 2609.910 0.010 2614.770 2.680 ;
+        RECT 2615.890 0.010 2620.750 2.680 ;
+        RECT 2621.870 0.010 2626.730 2.680 ;
+        RECT 2627.850 0.010 2632.710 2.680 ;
+        RECT 2633.830 0.010 2638.690 2.680 ;
+        RECT 2639.810 0.010 2644.670 2.680 ;
+        RECT 2645.790 0.010 2650.190 2.680 ;
+        RECT 2651.310 0.010 2656.170 2.680 ;
+        RECT 2657.290 0.010 2662.150 2.680 ;
+        RECT 2663.270 0.010 2668.130 2.680 ;
+        RECT 2669.250 0.010 2674.110 2.680 ;
+        RECT 2675.230 0.010 2680.090 2.680 ;
+        RECT 2681.210 0.010 2685.610 2.680 ;
+        RECT 2686.730 0.010 2691.590 2.680 ;
+        RECT 2692.710 0.010 2697.570 2.680 ;
+        RECT 2698.690 0.010 2703.550 2.680 ;
+        RECT 2704.670 0.010 2709.530 2.680 ;
+        RECT 2710.650 0.010 2715.510 2.680 ;
+        RECT 2716.630 0.010 2721.490 2.680 ;
+        RECT 2722.610 0.010 2727.010 2.680 ;
+        RECT 2728.130 0.010 2732.990 2.680 ;
+        RECT 2734.110 0.010 2738.970 2.680 ;
+        RECT 2740.090 0.010 2744.950 2.680 ;
+        RECT 2746.070 0.010 2750.930 2.680 ;
+        RECT 2752.050 0.010 2756.910 2.680 ;
+        RECT 2758.030 0.010 2762.890 2.680 ;
+        RECT 2764.010 0.010 2768.410 2.680 ;
+        RECT 2769.530 0.010 2774.390 2.680 ;
+        RECT 2775.510 0.010 2780.370 2.680 ;
+        RECT 2781.490 0.010 2786.350 2.680 ;
+        RECT 2787.470 0.010 2792.330 2.680 ;
+        RECT 2793.450 0.010 2798.310 2.680 ;
+        RECT 2799.430 0.010 2803.830 2.680 ;
+        RECT 2804.950 0.010 2809.810 2.680 ;
+        RECT 2810.930 0.010 2815.790 2.680 ;
+        RECT 2816.910 0.010 2821.770 2.680 ;
+        RECT 2822.890 0.010 2827.750 2.680 ;
+        RECT 2828.870 0.010 2833.730 2.680 ;
+        RECT 2834.850 0.010 2839.710 2.680 ;
+        RECT 2840.830 0.010 2845.230 2.680 ;
+        RECT 2846.350 0.010 2851.210 2.680 ;
+        RECT 2852.330 0.010 2857.190 2.680 ;
+        RECT 2858.310 0.010 2863.170 2.680 ;
+        RECT 2864.290 0.010 2869.150 2.680 ;
+        RECT 2870.270 0.010 2875.130 2.680 ;
+        RECT 2876.250 0.010 2881.110 2.680 ;
+        RECT 2882.230 0.010 2886.630 2.680 ;
+        RECT 2887.750 0.010 2892.610 2.680 ;
+        RECT 2893.730 0.010 2898.590 2.680 ;
+        RECT 2899.710 0.010 2904.570 2.680 ;
+        RECT 2905.690 0.010 2910.550 2.680 ;
+        RECT 2911.670 0.010 2916.530 2.680 ;
       LAYER met3 ;
         RECT 2.400 3487.700 2917.600 3508.965 ;
         RECT 2.800 3487.020 2917.600 3487.700 ;
@@ -9259,7 +9235,7 @@
         RECT 2.400 33.300 2917.200 33.980 ;
         RECT 2.800 31.980 2917.200 33.300 ;
         RECT 2.800 31.300 2917.600 31.980 ;
-        RECT 2.400 5.615 2917.600 31.300 ;
+        RECT 2.400 0.175 2917.600 31.300 ;
       LAYER met4 ;
         RECT -43.630 -38.270 -40.530 3557.950 ;
         RECT -38.830 -33.470 -35.730 3553.150 ;
@@ -10243,106 +10219,100 @@
         RECT -29.230 3540.450 2948.850 3543.550 ;
         RECT -24.430 3535.650 2944.050 3538.750 ;
         RECT -19.630 3530.850 2939.250 3533.950 ;
-        RECT 0.000 3493.790 2920.000 3519.650 ;
-        RECT 0.000 3458.790 2920.000 3487.490 ;
-        RECT 0.000 3423.790 2920.000 3452.490 ;
-        RECT 0.000 3388.790 2920.000 3417.490 ;
-        RECT 0.000 3353.790 2920.000 3382.490 ;
-        RECT 0.000 3318.790 2920.000 3347.490 ;
-        RECT 0.000 3283.790 2920.000 3312.490 ;
-        RECT 0.000 3248.790 2920.000 3277.490 ;
-        RECT 0.000 3213.790 2920.000 3242.490 ;
-        RECT 0.000 3178.790 2920.000 3207.490 ;
-        RECT 0.000 3143.790 2920.000 3172.490 ;
-        RECT 0.000 3108.790 2920.000 3137.490 ;
-        RECT 0.000 3073.790 2920.000 3102.490 ;
-        RECT 0.000 3038.790 2920.000 3067.490 ;
-        RECT 0.000 3003.790 2920.000 3032.490 ;
-        RECT 0.000 2968.790 2920.000 2997.490 ;
-        RECT 0.000 2933.790 2920.000 2962.490 ;
-        RECT 0.000 2898.790 2920.000 2927.490 ;
-        RECT 0.000 2863.790 2920.000 2892.490 ;
-        RECT 0.000 2828.790 2920.000 2857.490 ;
-        RECT 0.000 2793.790 2920.000 2822.490 ;
-        RECT 0.000 2758.790 2920.000 2787.490 ;
-        RECT 0.000 2723.790 2920.000 2752.490 ;
-        RECT 0.000 2688.790 2920.000 2717.490 ;
-        RECT 0.000 2653.790 2920.000 2682.490 ;
-        RECT 0.000 2618.790 2920.000 2647.490 ;
-        RECT 0.000 2583.790 2920.000 2612.490 ;
-        RECT 0.000 2548.790 2920.000 2577.490 ;
-        RECT 0.000 2513.790 2920.000 2542.490 ;
-        RECT 0.000 2478.790 2920.000 2507.490 ;
-        RECT 0.000 2443.790 2920.000 2472.490 ;
-        RECT 0.000 2408.790 2920.000 2437.490 ;
-        RECT 0.000 2373.790 2920.000 2402.490 ;
-        RECT 0.000 2338.790 2920.000 2367.490 ;
-        RECT 0.000 2303.790 2920.000 2332.490 ;
-        RECT 0.000 2268.790 2920.000 2297.490 ;
-        RECT 0.000 2233.790 2920.000 2262.490 ;
-        RECT 0.000 2198.790 2920.000 2227.490 ;
-        RECT 0.000 2163.790 2920.000 2192.490 ;
-        RECT 0.000 2128.790 2920.000 2157.490 ;
-        RECT 0.000 2093.790 2920.000 2122.490 ;
-        RECT 0.000 2058.790 2920.000 2087.490 ;
-        RECT 0.000 2023.790 2920.000 2052.490 ;
-        RECT 0.000 1988.790 2920.000 2017.490 ;
-        RECT 0.000 1953.790 2920.000 1982.490 ;
-        RECT 0.000 1918.790 2920.000 1947.490 ;
-        RECT 0.000 1883.790 2920.000 1912.490 ;
-        RECT 0.000 1848.790 2920.000 1877.490 ;
-        RECT 0.000 1813.790 2920.000 1842.490 ;
-        RECT 0.000 1778.790 2920.000 1807.490 ;
-        RECT 0.000 1743.790 2920.000 1772.490 ;
-        RECT 0.000 1708.790 2920.000 1737.490 ;
-        RECT 0.000 1673.790 2920.000 1702.490 ;
-        RECT 0.000 1638.790 2920.000 1667.490 ;
-        RECT 0.000 1603.790 2920.000 1632.490 ;
-        RECT 0.000 1568.790 2920.000 1597.490 ;
-        RECT 0.000 1533.790 2920.000 1562.490 ;
-        RECT 0.000 1498.790 2920.000 1527.490 ;
-        RECT 0.000 1463.790 2920.000 1492.490 ;
-        RECT 0.000 1428.790 2920.000 1457.490 ;
-        RECT 0.000 1393.790 2920.000 1422.490 ;
-        RECT 0.000 1358.790 2920.000 1387.490 ;
-        RECT 0.000 1323.790 2920.000 1352.490 ;
-        RECT 0.000 1288.790 2920.000 1317.490 ;
-        RECT 0.000 1253.790 2920.000 1282.490 ;
-        RECT 0.000 1218.790 2920.000 1247.490 ;
-        RECT 0.000 1183.790 2920.000 1212.490 ;
-        RECT 0.000 1148.790 2920.000 1177.490 ;
-        RECT 0.000 1113.790 2920.000 1142.490 ;
-        RECT 0.000 1078.790 2920.000 1107.490 ;
-        RECT 0.000 1043.790 2920.000 1072.490 ;
-        RECT 0.000 1008.790 2920.000 1037.490 ;
-        RECT 0.000 973.790 2920.000 1002.490 ;
-        RECT 0.000 938.790 2920.000 967.490 ;
-        RECT 0.000 903.790 2920.000 932.490 ;
-        RECT 0.000 868.790 2920.000 897.490 ;
-        RECT 0.000 833.790 2920.000 862.490 ;
-        RECT 0.000 798.790 2920.000 827.490 ;
-        RECT 0.000 763.790 2920.000 792.490 ;
-        RECT 0.000 728.790 2920.000 757.490 ;
-        RECT 0.000 693.790 2920.000 722.490 ;
-        RECT 0.000 658.790 2920.000 687.490 ;
-        RECT 0.000 623.790 2920.000 652.490 ;
-        RECT 0.000 588.790 2920.000 617.490 ;
-        RECT 0.000 553.790 2920.000 582.490 ;
-        RECT 0.000 518.790 2920.000 547.490 ;
-        RECT 0.000 483.790 2920.000 512.490 ;
-        RECT 0.000 448.790 2920.000 477.490 ;
-        RECT 0.000 413.790 2920.000 442.490 ;
-        RECT 0.000 378.790 2920.000 407.490 ;
-        RECT 0.000 343.790 2920.000 372.490 ;
-        RECT 0.000 308.790 2920.000 337.490 ;
-        RECT 0.000 273.790 2920.000 302.490 ;
-        RECT 0.000 238.790 2920.000 267.490 ;
-        RECT 0.000 203.790 2920.000 232.490 ;
-        RECT 0.000 168.790 2920.000 197.490 ;
-        RECT 0.000 133.790 2920.000 162.490 ;
-        RECT 0.000 98.790 2920.000 127.490 ;
-        RECT 0.000 63.790 2920.000 92.490 ;
-        RECT 0.000 0.030 2920.000 57.490 ;
+        RECT 0.000 3503.790 2920.000 3519.650 ;
+        RECT 0.000 3466.290 2920.000 3497.490 ;
+        RECT 0.000 3428.790 2920.000 3459.990 ;
+        RECT 0.000 3391.290 2920.000 3422.490 ;
+        RECT 0.000 3353.790 2920.000 3384.990 ;
+        RECT 0.000 3316.290 2920.000 3347.490 ;
+        RECT 0.000 3278.790 2920.000 3309.990 ;
+        RECT 0.000 3241.290 2920.000 3272.490 ;
+        RECT 0.000 3203.790 2920.000 3234.990 ;
+        RECT 0.000 3166.290 2920.000 3197.490 ;
+        RECT 0.000 3128.790 2920.000 3159.990 ;
+        RECT 0.000 3091.290 2920.000 3122.490 ;
+        RECT 0.000 3053.790 2920.000 3084.990 ;
+        RECT 0.000 3016.290 2920.000 3047.490 ;
+        RECT 0.000 2978.790 2920.000 3009.990 ;
+        RECT 0.000 2941.290 2920.000 2972.490 ;
+        RECT 0.000 2903.790 2920.000 2934.990 ;
+        RECT 0.000 2866.290 2920.000 2897.490 ;
+        RECT 0.000 2828.790 2920.000 2859.990 ;
+        RECT 0.000 2791.290 2920.000 2822.490 ;
+        RECT 0.000 2753.790 2920.000 2784.990 ;
+        RECT 0.000 2716.290 2920.000 2747.490 ;
+        RECT 0.000 2678.790 2920.000 2709.990 ;
+        RECT 0.000 2641.290 2920.000 2672.490 ;
+        RECT 0.000 2603.790 2920.000 2634.990 ;
+        RECT 0.000 2566.290 2920.000 2597.490 ;
+        RECT 0.000 2528.790 2920.000 2559.990 ;
+        RECT 0.000 2491.290 2920.000 2522.490 ;
+        RECT 0.000 2453.790 2920.000 2484.990 ;
+        RECT 0.000 2416.290 2920.000 2447.490 ;
+        RECT 0.000 2378.790 2920.000 2409.990 ;
+        RECT 0.000 2341.290 2920.000 2372.490 ;
+        RECT 0.000 2303.790 2920.000 2334.990 ;
+        RECT 0.000 2266.290 2920.000 2297.490 ;
+        RECT 0.000 2228.790 2920.000 2259.990 ;
+        RECT 0.000 2191.290 2920.000 2222.490 ;
+        RECT 0.000 2153.790 2920.000 2184.990 ;
+        RECT 0.000 2116.290 2920.000 2147.490 ;
+        RECT 0.000 2078.790 2920.000 2109.990 ;
+        RECT 0.000 2041.290 2920.000 2072.490 ;
+        RECT 0.000 2003.790 2920.000 2034.990 ;
+        RECT 0.000 1966.290 2920.000 1997.490 ;
+        RECT 0.000 1928.790 2920.000 1959.990 ;
+        RECT 0.000 1891.290 2920.000 1922.490 ;
+        RECT 0.000 1853.790 2920.000 1884.990 ;
+        RECT 0.000 1816.290 2920.000 1847.490 ;
+        RECT 0.000 1778.790 2920.000 1809.990 ;
+        RECT 0.000 1741.290 2920.000 1772.490 ;
+        RECT 0.000 1703.790 2920.000 1734.990 ;
+        RECT 0.000 1666.290 2920.000 1697.490 ;
+        RECT 0.000 1628.790 2920.000 1659.990 ;
+        RECT 0.000 1591.290 2920.000 1622.490 ;
+        RECT 0.000 1553.790 2920.000 1584.990 ;
+        RECT 0.000 1516.290 2920.000 1547.490 ;
+        RECT 0.000 1478.790 2920.000 1509.990 ;
+        RECT 0.000 1441.290 2920.000 1472.490 ;
+        RECT 0.000 1403.790 2920.000 1434.990 ;
+        RECT 0.000 1366.290 2920.000 1397.490 ;
+        RECT 0.000 1328.790 2920.000 1359.990 ;
+        RECT 0.000 1291.290 2920.000 1322.490 ;
+        RECT 0.000 1253.790 2920.000 1284.990 ;
+        RECT 0.000 1216.290 2920.000 1247.490 ;
+        RECT 0.000 1178.790 2920.000 1209.990 ;
+        RECT 0.000 1141.290 2920.000 1172.490 ;
+        RECT 0.000 1103.790 2920.000 1134.990 ;
+        RECT 0.000 1066.290 2920.000 1097.490 ;
+        RECT 0.000 1028.790 2920.000 1059.990 ;
+        RECT 0.000 991.290 2920.000 1022.490 ;
+        RECT 0.000 953.790 2920.000 984.990 ;
+        RECT 0.000 916.290 2920.000 947.490 ;
+        RECT 0.000 878.790 2920.000 909.990 ;
+        RECT 0.000 841.290 2920.000 872.490 ;
+        RECT 0.000 803.790 2920.000 834.990 ;
+        RECT 0.000 766.290 2920.000 797.490 ;
+        RECT 0.000 728.790 2920.000 759.990 ;
+        RECT 0.000 691.290 2920.000 722.490 ;
+        RECT 0.000 653.790 2920.000 684.990 ;
+        RECT 0.000 616.290 2920.000 647.490 ;
+        RECT 0.000 578.790 2920.000 609.990 ;
+        RECT 0.000 541.290 2920.000 572.490 ;
+        RECT 0.000 503.790 2920.000 534.990 ;
+        RECT 0.000 466.290 2920.000 497.490 ;
+        RECT 0.000 428.790 2920.000 459.990 ;
+        RECT 0.000 391.290 2920.000 422.490 ;
+        RECT 0.000 353.790 2920.000 384.990 ;
+        RECT 0.000 316.290 2920.000 347.490 ;
+        RECT 0.000 278.790 2920.000 309.990 ;
+        RECT 0.000 241.290 2920.000 272.490 ;
+        RECT 0.000 203.790 2920.000 234.990 ;
+        RECT 0.000 166.290 2920.000 197.490 ;
+        RECT 0.000 128.790 2920.000 159.990 ;
+        RECT 0.000 91.290 2920.000 122.490 ;
+        RECT 0.000 53.790 2920.000 84.990 ;
+        RECT 0.000 0.030 2920.000 47.490 ;
         RECT -19.630 -14.270 2939.250 -11.170 ;
         RECT -24.430 -19.070 2944.050 -15.970 ;
         RECT -29.230 -23.870 2948.850 -20.770 ;
diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 4d753d4..459e4ba 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/openlane/config.tcl b/openlane/config.tcl
index 518fff2..f1b7fd1 100644
--- a/openlane/config.tcl
+++ b/openlane/config.tcl
@@ -11,19 +11,23 @@
 set ::env(PL_MAX_DISPLACEMENT_X) 3000
 set ::env(PL_MAX_DISPLACEMENT_Y) 1000
 set ::env(FP_PDN_VOFFSET) 40
-set ::env(FP_PDN_HOFFSET) 50
+set ::env(FP_PDN_HOFFSET) 40
 set ::env(FP_PDN_VPITCH) 70.0
-set ::env(FP_PDN_HPITCH) 70.0
+set ::env(FP_PDN_HPITCH) 75.0
 set ::env(FP_PDN_AUTO_ADJUST) 0
 set ::env(FP_PDN_IRDROP) 0
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) 0.38
+set ::env(PL_TARGET_DENSITY) 0.35
 set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FP_HORIZONTAL_HALO) 20
+set ::env(FP_HORIZONTAL_HALO) 25
 set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 2000.0
 set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
+set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.5
 set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(GLB_RT_ADJUSTMENT) 0.2
+set ::env(GLB_RT_L2_ADJUSTMENT) 0.9
+set ::env(GLB_RT_L3_ADJUSTMENT) 0.7
 set ::env(FP_PDN_MACRO_HOOKS) "fpga_struct_block vccd1 vssd1"
 set ::env(PDN_NO_STRIPE_DOMAINS) [list {vccd2} {vdda1} {vdda2}]
 set ::env(PDN_CFG) "/home/egor/proj/fpga/impl/open/pdn_cfg.tcl"
diff --git a/openlane/user_project_wrapper.sdc b/openlane/user_project_wrapper.sdc
new file mode 100644
index 0000000..d312df8
--- /dev/null
+++ b/openlane/user_project_wrapper.sdc
@@ -0,0 +1,3628 @@
+create_clock -name "wb_clk_i" -add -period 40 [get_ports wb_clk_i]
+create_clock -name "ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf" -add -period 1000 [get_pins ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf/X]
+create_clock -name "ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf" -add -period 1000 [get_pins ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf/X]
+create_clock -name "ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf" -add -period 1000 [get_pins ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf/X]
+
+set_units -time 1ns
+
+#set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+#set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+#puts "\[INFO\]: Setting output delay to: $output_delay_value"
+#puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+if {[info exists CLOCK_PORT]} {
+    set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
+    #set rst_indx [lsearch [all_inputs] [get_port resetn]]
+    set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+    #set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+    set all_inputs_wo_clk_rst $all_inputs_wo_clk
+    puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
+    set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks $::env(CLOCK_PORT)]
+}
+
+# TODO set this as parameter
+set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+#set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks $::env(CLOCK_PORT)]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+
+# Disable all cross-clocking paths
+set_false_path -from [get_clocks wb_clk_i] -to [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks wb_clk_i] -to [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks wb_clk_i] -to [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] -to [get_clocks wb_clk_i] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] -to [get_clocks wb_clk_i] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] -to [get_clocks wb_clk_i] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_block_clk_buf.tech_clkbuf] 
+set_false_path -from [get_clocks ariel_fpga_top_inst.config_hrnode_clk_buf.tech_clkbuf] -to [get_clocks ariel_fpga_top_inst.config_vrnode_clk_buf.tech_clkbuf] 
+
+set BUFIPIN [lindex [lreverse [split [lindex [get_name [lindex [get_pin -hier *tech_buf/*] 0]] 0] /]] 0]
+set BUFOPIN [lindex [lreverse [split [lindex [get_name [lindex [get_pin -hier *tech_buf/*] 1]] 0] /]] 0]
+set_disable_timing [get_cells *loop_breaker*]
+
+# Routing node <-> LB constraints
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:1.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:2.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:3.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:4.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:5.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:6.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:7.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:8.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:9.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:1.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:2.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:3.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:4.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:5.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:6.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:7.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:8.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:9.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:10.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/input*_i]
+set_max_delay -ignore_clock_latency 0.05 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.struct_blocks_x:10.struct_blocks_y:11.struct_block/outputs_o*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+
+# Routing node internal && RN <-> RN constraints
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:1.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:1.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:2.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:2.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:3.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:3.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:4.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:4.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:5.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:5.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:6.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:6.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:7.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:7.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:8.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:8.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:9.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:1.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:1.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:2.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:2.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:3.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:3.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:4.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:4.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:5.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:5.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:6.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:6.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:7.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:7.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:8.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:8.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:9.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:9.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:10.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_up.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_right.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:10.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:11.vertical_routing_network_y:11.routing_node_down.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:11.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.7 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tfinish.tech_buf/$BUFOPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:9.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 0.35 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.horizontal_routing_network_x:10.horizontal_routing_network_y:12.routing_node_left.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.vertical_routing_network_x:10.vertical_routing_network_y:11.routing_node_down.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+
+# From IO to routing nodes constraints
+set_max_delay -ignore_clock_latency 1.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:1.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_max_delay -ignore_clock_latency 1.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:11.*_routing_network_y:*.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:11.*_routing_network_y:*.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_max_delay -ignore_clock_latency 1.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:1.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_max_delay -ignore_clock_latency 1.0 -from [get_ports io_in*] -to [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:12.routing_node_*.node.muxes:*.bufs:*.rnode_in.tech_buf/$BUFIPIN]
+set_max_delay -ignore_clock_latency 2.1 -from [get_pins ariel_fpga_top_inst.fpga_fabric_inst.*_routing_network_x:*.*_routing_network_y:12.routing_node_*.node.muxes:*.rnode_tstart.tech_buf/$BUFIPIN] -to [get_ports io_out*]
+set_input_delay 0 -clock [get_clocks wb_clk_i] [get_ports wbs*_i]
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index 4b8f349..e0d9ba6 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ