diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 4cdd692..62f6835 100644
--- a/gds/user_project_wrapper.gds.gz
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Binary files differ
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef
index d048acc..298e75e 100644
--- a/lef/user_project_wrapper.lef
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diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index 459e4ba..fed162d 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ
diff --git a/openlane/config.tcl b/openlane/config.tcl
index f1b7fd1..dd83943 100644
--- a/openlane/config.tcl
+++ b/openlane/config.tcl
@@ -13,19 +13,20 @@
 set ::env(FP_PDN_VOFFSET) 40
 set ::env(FP_PDN_HOFFSET) 40
 set ::env(FP_PDN_VPITCH) 70.0
-set ::env(FP_PDN_HPITCH) 75.0
+set ::env(FP_PDN_HPITCH) 37.5
 set ::env(FP_PDN_AUTO_ADJUST) 0
 set ::env(FP_PDN_IRDROP) 0
 set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) 0.35
+set ::env(PL_TARGET_DENSITY) 0.3
 set ::env(DIODE_INSERTION_STRATEGY) 0
-set ::env(FP_HORIZONTAL_HALO) 25
+set ::env(FP_HORIZONTAL_HALO) 20
+set ::env(FP_VERTICAL_HALO) 40
 set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 2000.0
 set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
 set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.5
 set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) 1
 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
-set ::env(GLB_RT_ADJUSTMENT) 0.2
+set ::env(GLB_RT_ADJUSTMENT) 0.1
 set ::env(GLB_RT_L2_ADJUSTMENT) 0.9
 set ::env(GLB_RT_L3_ADJUSTMENT) 0.7
 set ::env(FP_PDN_MACRO_HOOKS) "fpga_struct_block vccd1 vssd1"
diff --git a/verilog/gl/user_project_wrapper.v.gz b/verilog/gl/user_project_wrapper.v.gz
index e0d9ba6..0a8d483 100644
--- a/verilog/gl/user_project_wrapper.v.gz
+++ b/verilog/gl/user_project_wrapper.v.gz
Binary files differ