2021-12-31 09:02:40 - [INFO] - {{Project Git Info}} Repository: https://github.com/egorxe/ariel_fpga_openmpw.git | Branch: main | Commit: 4689d04c43f6eb0eaf507c357e99f6e003e3d67d
2021-12-31 09:02:40 - [INFO] - {{INSTALLING CARAVEL}} Running `make install` in open_source_configurable_fpga_fabric
2021-12-31 09:02:49 - [INFO] - {{EXTRACTING GDS}} Extracting GDS files in: open_source_configurable_fpga_fabric
2021-12-31 09:02:59 - [INFO] - {{Project GDS Info}} user_project_wrapper: cbc254594cec139a792e56c658d988aa6c309fd5
2021-12-31 09:02:59 - [INFO] - {{Tools Info}} KLayout: v0.27.5 | Magic: v8.3.245
2021-12-31 09:02:59 - [INFO] - {{PDKs Info}} Open PDKs: 476f7428f7f686de51a5164c702629a9b9f2da46 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
2021-12-31 09:02:59 - [INFO] - {{START}} Precheck Started, the full log 'precheck.log' will be located in 'open_source_configurable_fpga_fabric/jobs/mpw_precheck/7ad3ef37-8cec-4bf6-ae64-f5b4f4bd86eb/logs'
2021-12-31 09:02:59 - [INFO] - {{PRECHECK SEQUENCE}} Precheck will run the following checks: License Makefile Default Documentation Consistency XOR Magic DRC Klayout FEOL Klayout BEOL Klayout Offgrid Klayout Metal Minimum Clear Area Density Klayout Pin Label Purposes Overlapping Drawing Klayout ZeroArea
2021-12-31 09:02:59 - [INFO] - {{STEP UPDATE}} Executing Check 1 of 13: License
2021-12-31 09:03:00 - [INFO] - An approved LICENSE (Apache-2.0) was found in open_source_configurable_fpga_fabric.
2021-12-31 09:03:00 - [INFO] - {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
2021-12-31 09:03:01 - [INFO] - An approved LICENSE (Apache-2.0) was found in open_source_configurable_fpga_fabric.
2021-12-31 09:03:02 - [INFO] - An approved LICENSE (Apache-2.0) was found in open_source_configurable_fpga_fabric.
2021-12-31 09:03:02 - [INFO] - {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
2021-12-31 09:03:02 - [WARNING] - {{SPDX COMPLIANCE CHECK FAILED}} Found 29 non-compliant file(s) with the SPDX Standard.
2021-12-31 09:03:02 - [INFO] - SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['open_source_configurable_fpga_fabric/Makefile', 'open_source_configurable_fpga_fabric/docs/environment.yml', 'open_source_configurable_fpga_fabric/docs/Makefile', 'open_source_configurable_fpga_fabric/docs/source/index.rst', 'open_source_configurable_fpga_fabric/docs/source/conf.py', 'open_source_configurable_fpga_fabric/verilog/dv/Makefile', 'open_source_configurable_fpga_fabric/verilog/dv/la_test2/la_test2_tb.v', 'open_source_configurable_fpga_fabric/verilog/dv/la_test2/la_test2.c', 'open_source_configurable_fpga_fabric/verilog/dv/la_test2/Makefile', 'open_source_configurable_fpga_fabric/verilog/dv/wb_config_loader/Makefile', 'open_source_configurable_fpga_fabric/verilog/dv/wb_config_loader/wb_config_loader.c', 'open_source_configurable_fpga_fabric/verilog/dv/wb_config_loader/wb_cnt.txt_hn_bit.h', 'open_source_configurable_fpga_fabric/verilog/dv/wb_config_loader/wb_cnt.txt_lb_bit.h', 'open_source_configurable_fpga_fabric/verilog/dv/wb_config_loader/wb_cnt.txt_vn_bit.h', 'open_source_configurable_fpga_fabric/verilog/dv/la_test1/la_test1.c']
2021-12-31 09:03:02 - [INFO] - For the full SPDX compliance report check: open_source_configurable_fpga_fabric/jobs/mpw_precheck/7ad3ef37-8cec-4bf6-ae64-f5b4f4bd86eb/logs/spdx_compliance_report.log
2021-12-31 09:03:02 - [INFO] - {{STEP UPDATE}} Executing Check 2 of 13: Makefile
2021-12-31 09:03:02 - [INFO] - {{MAKEFILE CHECK PASSED}} Makefile valid.
2021-12-31 09:03:02 - [INFO] - {{STEP UPDATE}} Executing Check 3 of 13: Default
2021-12-31 09:03:02 - [INFO] - {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
2021-12-31 09:03:03 - [INFO] - {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
2021-12-31 09:03:03 - [INFO] - {{STEP UPDATE}} Executing Check 4 of 13: Documentation
2021-12-31 09:03:03 - [INFO] - {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
2021-12-31 09:03:03 - [INFO] - {{STEP UPDATE}} Executing Check 5 of 13: Consistency
2021-12-31 09:03:03 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_project_wrapper.v
2021-12-31 09:03:04 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/__user_project_wrapper.v
2021-12-31 09:03:04 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
2021-12-31 09:03:04 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/verilog/rtl/defines.v
2021-12-31 09:26:48 - [INFO] - HIERARCHY CHECK PASSED: Module user_project_wrapper is instantiated in caravel. 
2021-12-31 09:26:48 - [INFO] - COMPLEXITY CHECK PASSED: Netlist caravel contains at least 8 instances (90 instances). 
2021-12-31 09:26:48 - [INFO] - MODELING CHECK PASSED: Netlist caravel is structural.
2021-12-31 09:26:48 - [INFO] - SUBMODULE HOOKS CHECK PASSED: All module ports for user_project_wrapper are correctly connected in the top level netlist caravel.
2021-12-31 09:26:48 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in caravel are connected to power
2021-12-31 09:26:48 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} caravel netlist passed all consistency checks.
2021-12-31 09:26:48 - [INFO] - PORTS CHECK PASSED: Netlist user_project_wrapper ports match the golden wrapper ports
2021-12-31 09:26:48 - [INFO] - COMPLEXITY CHECK PASSED: Netlist user_project_wrapper contains at least 1 instances (164957 instances). 
2021-12-31 09:26:48 - [INFO] - MODELING CHECK PASSED: Netlist user_project_wrapper is structural.
2021-12-31 09:26:48 - [INFO] - LAYOUT CHECK PASSED: The GDS layout for user_project_wrapper matches the provided structural netlist.
2021-12-31 09:26:50 - [INFO] - POWER CONNECTIONS CHECK PASSED: All instances in user_project_wrapper are connected to power
2021-12-31 09:26:50 - [INFO] - PORT TYPES CHECK PASSED: Netlist user_project_wrapper port types match the golden wrapper port types.
2021-12-31 09:26:50 - [INFO] - {{NETLIST CONSISTENCY CHECK PASSED}} user_project_wrapper netlist passed all consistency checks.
2021-12-31 09:26:51 - [INFO] - {{CONSISTENCY CHECK PASSED}} The user netlist and the top netlist are valid.
2021-12-31 09:26:51 - [INFO] - {{STEP UPDATE}} Executing Check 6 of 13: XOR
2021-12-31 09:26:51 - [INFO] - Trying to get file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_project_wrapper_empty.gds.gz
2021-12-31 09:26:51 - [INFO] - Got file https://raw.githubusercontent.com/efabless/caravel/e938b7dcf30360591aac7775251abd513bb8f72f/gds/user_project_wrapper_empty.gds.gz
2021-12-31 09:30:56 - [INFO] - {XOR CHECK UPDATE} Total XOR differences: 0, for more details view open_source_configurable_fpga_fabric/jobs/mpw_precheck/7ad3ef37-8cec-4bf6-ae64-f5b4f4bd86eb/outputs/user_project_wrapper.xor.gds
2021-12-31 09:30:56 - [INFO] - {{XOR CHECK PASSED}} The GDS file has no XOR violations.
2021-12-31 09:30:56 - [INFO] - {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
2021-12-31 10:32:42 - [INFO] - 0 DRC violations
2021-12-31 10:32:42 - [INFO] - {{MAGIC DRC CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 10:32:42 - [INFO] - {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
2021-12-31 10:35:26 - [INFO] - No DRC Violations found
2021-12-31 10:35:26 - [INFO] - {{Klayout FEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 10:35:26 - [INFO] - {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
2021-12-31 11:17:57 - [INFO] - No DRC Violations found
2021-12-31 11:17:57 - [INFO] - {{Klayout BEOL CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 11:17:57 - [INFO] - {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
2021-12-31 11:24:08 - [INFO] - No DRC Violations found
2021-12-31 11:24:08 - [INFO] - {{Klayout Offgrid CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 11:24:08 - [INFO] - {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
2021-12-31 11:26:38 - [INFO] - No DRC Violations found
2021-12-31 11:26:38 - [INFO] - {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 11:26:38 - [INFO] - {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
2021-12-31 11:27:48 - [INFO] - No DRC Violations found
2021-12-31 11:27:48 - [INFO] - {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 11:27:48 - [INFO] - {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
2021-12-31 11:28:10 - [INFO] - No DRC Violations found
2021-12-31 11:28:10 - [INFO] - {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_project_wrapper.gds, has no DRC violations.
2021-12-31 11:28:10 - [INFO] - {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'open_source_configurable_fpga_fabric/jobs/mpw_precheck/7ad3ef37-8cec-4bf6-ae64-f5b4f4bd86eb/logs'
2021-12-31 11:28:10 - [INFO] - {{SUCCESS}} All Checks Passed !!!