Merge pull request #51 from efabless/caravel_openframe_2
Caravel openframe 2
diff --git a/.github/scripts/build/run-ship.sh b/.github/scripts/build/run-ship.sh
index 236c00a..d084c00 100644
--- a/.github/scripts/build/run-ship.sh
+++ b/.github/scripts/build/run-ship.sh
@@ -25,7 +25,9 @@
# Install full version of caravel
git clone https://github.com/efabless/caravel --depth 1 $CARAVEL_ROOT
-docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make ship;"
+make install_mcw
+
+docker run -v $UPRJ_ROOT:$UPRJ_ROOT -v $PDK_ROOT:$PDK_ROOT -v $CARAVEL_ROOT:$CARAVEL_ROOT -e UPRJ_ROOT=$UPRJ_ROOT -e PDK_ROOT=$PDK_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -u $(id -u $USER):$(id -g $USER) $IMAGE_NAME bash -c "cd $CARAVEL_ROOT; make uncompress; cd $UPRJ_ROOT; make -f $CARAVEL_ROOT/Makefile ship;"
SHIP_FILE=$UPRJ_ROOT/gds/caravel.gds
diff --git a/.github/workflows/caravel_build.yml b/.github/workflows/caravel_build.yml
index 3217a5e..3978d7f 100644
--- a/.github/workflows/caravel_build.yml
+++ b/.github/workflows/caravel_build.yml
@@ -23,12 +23,12 @@
- name: Install The PDK
run: bash ${GITHUB_WORKSPACE}/.github/scripts/dv/pdkBuild.sh
env:
- OPENLANE_TAG: 2021.09.16_03.28.21
+ OPENLANE_TAG: 2021.12.17_05.07.41
- name: Run make ship
run: bash ${GITHUB_WORKSPACE}/.github/scripts/build/run-ship.sh
env:
- OPENLANE_TAG: 2021.09.16_03.28.21
+ OPENLANE_TAG: 2021.12.17_05.07.41
set_user_id:
runs-on: ubuntu-latest
diff --git a/Makefile b/Makefile
index 188e997..45270d2 100644
--- a/Makefile
+++ b/Makefile
@@ -23,16 +23,14 @@
ifeq ($(CARAVEL_LITE),1)
CARAVEL_NAME := caravel-lite
- CARAVEL_REPO := https://github.com/efabless/caravel-lite
- CARAVEL_BRANCH := main
+ CARAVEL_REPO := https://github.com/efabless/caravel_openframe-lite
+ CARAVEL_TAG := 'rc-8'
else
CARAVEL_NAME := caravel
- CARAVEL_REPO := https://github.com/efabless/caravel
- CARAVEL_BRANCH := master
+ CARAVEL_REPO := https://github.com/efabless/caravel_openframe
+ CARAVEL_TAG := 'rc-8'
endif
-# Install caravel as submodule, (1): submodule, (0): clone
-SUBMODULE?=1
# Include Caravel Makefile Targets
.PHONY: % : check-caravel
@@ -72,19 +70,8 @@
# Install caravel
.PHONY: install
install:
-ifeq ($(SUBMODULE),1)
- @echo "Installing $(CARAVEL_NAME) as a submodule.."
-# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
- $(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
- @if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
- @git submodule update --init
- @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
- $(MAKE) simlink
-else
@echo "Installing $(CARAVEL_NAME).."
- @git clone $(CARAVEL_REPO) $(CARAVEL_ROOT)
- @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
-endif
+ @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
# Create symbolic links to caravel's main files
.PHONY: simlink
@@ -102,30 +89,12 @@
# Update Caravel
.PHONY: update_caravel
update_caravel: check-caravel
-ifeq ($(SUBMODULE),1)
- @git submodule update --init --recursive
- cd $(CARAVEL_ROOT) && \
- git checkout $(CARAVEL_BRANCH) && \
- git pull
-else
- cd $(CARAVEL_ROOT)/ && \
- git checkout $(CARAVEL_BRANCH) && \
- git pull
-endif
+ cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
# Uninstall Caravel
.PHONY: uninstall
uninstall:
-ifeq ($(SUBMODULE),1)
- git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)"
- git add .gitmodules
- git submodule deinit -f $(CARAVEL_ROOT)
- git rm --cached $(CARAVEL_ROOT)
- rm -rf .git/modules/$(CARAVEL_NAME)
rm -rf $(CARAVEL_ROOT)
-else
- rm -rf $(CARAVEL_ROOT)
-endif
# Install Openlane
.PHONY: openlane
diff --git a/verilog/dv/mprj_stimulus/Makefile b/verilog/dv/mprj_stimulus/Makefile
index 3a73b99..b0e4051 100644
--- a/verilog/dv/mprj_stimulus/Makefile
+++ b/verilog/dv/mprj_stimulus/Makefile
@@ -25,6 +25,11 @@
CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+## Management SoC Pointers
+MGMT_SOC_PATH ?= ../../../../caravel_pico
+MGMT_SOC_VERILOG_PATH = $(MGMT_SOC_PATH)/verilog
+MGMT_SOC_RTL_PATH = $(MGMT_SOC_PATH)/verilog/rtl
+
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
@@ -50,12 +55,12 @@
ifeq ($(SIM),RTL)
iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MGMT_SOC_RTL_PATH) \
$< -o $@
else
iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
- -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+ -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) -I $(MGMT_SOC_VERILOG_PATH) \
$< -o $@
endif
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus.c b/verilog/dv/mprj_stimulus/mprj_stimulus.c
index e4d0a2d..7d2c29a 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus.c
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus.c
@@ -31,19 +31,21 @@
// designed to read the project count through the
// logic analyzer probes.
// I/O 6 is configured for the UART Tx line
+
uint32_t testval;
- reg_spimaster_config = 0xa002; // Enable, prescaler = 2
+ reg_hkspi_disable = 1; // Shut off the housekeeping SPI,
+ // so we can use the pins.
reg_mprj_datal = 0x00000000;
reg_mprj_datah = 0x00000000;
- reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;;
- reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
- reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
@@ -71,18 +73,13 @@
reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
- reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
- reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
-
- reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
-
- // Set UART clock to 64 kbaud (enable before I/O configuration)
- reg_uart_clkdiv = 625;
- reg_uart_enable = 1;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
+ reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
/* Apply configuration */
reg_mprj_xfer = 1;
@@ -116,17 +113,24 @@
// Test ability to force data on channel 37
// NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
- reg_mprj_datah = 0xffffffca;
+
+ reg_mprj_datah = 0x0f0f0fc0;
+ reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x0f0f0fca;
+ reg_mprj_datah = 0x0000000a;
+ reg_mprj_datah = 0x0f0f0fc0;
reg_mprj_datah = 0x00000000;
reg_mprj_datah = 0x0f0f0fc5;
- reg_mprj_datah = 0x00000000;
+ reg_mprj_datah = 0x00000005;
// Test ability to read back data generated by the user project
// on the "monitored" outputs. Read from the lower 16 bits and
// copy the value to the upper 16 bits.
testval = reg_mprj_datal;
- reg_mprj_datal = ((testval & 0xff8) << 9) & 0xffff0000;
+ reg_mprj_datal = (testval << 16);
+ testval = reg_mprj_datal;
+ reg_mprj_datal = (testval << 16);
// Flag end of the test
reg_mprj_datal = 0xAB510000;
diff --git a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
index 1409015..0ac0b42 100644
--- a/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
+++ b/verilog/dv/mprj_stimulus/mprj_stimulus_tb.v
@@ -28,17 +28,8 @@
reg RSTB;
reg CSB;
reg power1, power2;
- reg power3, power4;
-
- wire HIGH;
- wire LOW;
- wire TRI;
- assign HIGH = 1'b1;
- assign LOW = 1'b0;
- assign TRI = 1'bz;
wire gpio;
- wire uart_tx;
wire [37:0] mprj_io;
wire [15:0] checkbits;
wire [3:0] status;
@@ -46,8 +37,10 @@
// Signals Assignment
assign checkbits = mprj_io[31:16];
assign status = mprj_io[35:32];
- assign uart_tx = mprj_io[6];
- assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
+
+ // Force CSB high until simulation is underway
+ // Note: The CSB GPIO pin default needs to be set to a pull-up. . .
+ assign mprj_io[3] = CSB;
always #12.5 clock <= (clock === 1'b0);
@@ -74,23 +67,29 @@
$display("Monitor: mprj_stimulus test started");
wait(status == 4'ha);
wait(status == 4'h5);
- // Value 0009 reflects copying user-controlled outputs to memory and back
- // to management-controlled outputs.
- wait(checkbits == 16'h0009);
+
+ // Values reflect copying user-controlled outputs to memory and back
+ // to management-controlled outputs. Note that there is a slight
+ // discrepancy in timing when using gate level simulation; either
+ // of the specified values is okay.
+
+ wait(checkbits == 16'h0840 || checkbits == 16'h0841);
+ wait(checkbits == 16'h0a00 || checkbits == 16'h0a01);
+
wait(checkbits == 16'hAB51);
$display("Monitor: mprj_stimulus test Passed");
#10000;
$finish;
end
- // Reset Operation
+ // Reset Operation
initial begin
RSTB <= 1'b0;
- CSB <= 1'b1; // Force CSB high
+ CSB <= 1'b1;
#2000;
- RSTB <= 1'b1; // Release reset
- #170000;
- CSB = 1'b0; // CSB can be released
+ RSTB <= 1'b1; // Release reset
+ #200000;
+ CSB <= 1'bz; // Stop driving CSB
end
initial begin // Power-up sequence
@@ -148,10 +147,5 @@
.io3() // not used
);
- // Testbench UART
- tbuart tbuart (
- .ser_rx(uart_tx)
- );
-
endmodule
`default_nettype wire
