diff --git a/gds/Ibtida_top_dffram_cv.gds.gz b/gds/Ibtida_top_dffram_cv.gds.gz
index 7a85ffd..718cd79 100644
--- a/gds/Ibtida_top_dffram_cv.gds.gz
+++ b/gds/Ibtida_top_dffram_cv.gds.gz
Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index b0ade1e..101e717 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag
index 6c1cd81..6f53a60 100644
--- a/mag/user_project_wrapper.mag
+++ b/mag/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636928078
+timestamp 1637017205
 << locali >>
 rect 190377 57443 190411 57749
 rect 190929 57103 190963 57477
@@ -41892,7 +41892,7 @@
 rect 592618 -7622 592650 -7386
 rect -8726 -7654 592650 -7622
 use Ibtida_top_dffram_cv  mprj
-timestamp 1636928078
+timestamp 1637017205
 transform 1 0 72000 0 1 60000
 box 0 0 447948 592008
 << labels >>
diff --git a/maglef/user_project_wrapper.mag b/maglef/user_project_wrapper.mag
index 831d2f0..07cbbed 100644
--- a/maglef/user_project_wrapper.mag
+++ b/maglef/user_project_wrapper.mag
@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1636928876
+timestamp 1637017926
 << obsli1 >>
 rect 72000 3145 519948 652008
 << obsm1 >>
@@ -3926,7 +3926,7 @@
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 584000 704000
 string LEFview TRUE
-string GDS_FILE /openlane/designs/user_project_wrapper_14_nov/runs/14_Nov_all_decaps/results/magic/user_project_wrapper.gds
+string GDS_FILE /openlane/designs/user_project_wrapper_14_nov/runs/decap3_fill1_2/results/magic/user_project_wrapper.gds
 string GDS_END 234117710
 string GDS_START 232833302
 << end >>
diff --git a/signoff/final_summary_report.csv b/signoff/final_summary_report.csv
index c99948a..8307ee8 100644
--- a/signoff/final_summary_report.csv
+++ b/signoff/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/openlane/designs/user_project_wrapper_14_nov,user_project_wrapper,14_Nov_all_decaps,flow_completed,2h42m7s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,462.66,1,0,0,0,0,0,0,0,0,0,-1,-1,380694,1804,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,2.31,1.54,0.04,0.0,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/openlane/designs/user_project_wrapper_14_nov,user_project_wrapper,decap3_fill1_2,flow_completed,2h42m53s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,453.55,1,0,0,0,0,0,0,0,0,0,-1,-1,380694,1804,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,2.31,1.54,0.04,0.0,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 723e47c..a3fb970 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/openlane/designs/user_project_wrapper,user_project_wrapper,14-nov-fill-decap3,flow_completed,2h35m7s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,454.94,1,0,0,0,0,0,0,0,0,0,-1,-1,380694,1804,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,2.31,1.54,0.04,0.0,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,2h50m55s,-1,0.19458281444582815,10.2784,0.09729140722291407,-1,453.23,1,0,0,0,0,0,0,0,0,0,-1,-1,380694,1804,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,2.31,1.54,0.04,0.0,-1,27,645,27,645,0,0,0,1,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0