| // THIS FILE IS AUTOGENERATED BY wb_interconA_gen |
| // ANY MANUAL CHANGES WILL BE LOST |
| wire [31:0] wb_m2s_cpu0_ibus_adr; |
| wire [31:0] wb_m2s_cpu0_ibus_dat; |
| wire [3:0] wb_m2s_cpu0_ibus_sel; |
| wire wb_m2s_cpu0_ibus_we; |
| wire wb_m2s_cpu0_ibus_cyc; |
| wire wb_m2s_cpu0_ibus_stb; |
| wire [2:0] wb_m2s_cpu0_ibus_cti; |
| wire [1:0] wb_m2s_cpu0_ibus_bte; |
| wire [31:0] wb_s2m_cpu0_ibus_dat; |
| wire wb_s2m_cpu0_ibus_ack; |
| wire wb_s2m_cpu0_ibus_err; |
| wire wb_s2m_cpu0_ibus_rty; |
| wire [31:0] wb_m2s_cpu0_dbus_adr; |
| wire [31:0] wb_m2s_cpu0_dbus_dat; |
| wire [3:0] wb_m2s_cpu0_dbus_sel; |
| wire wb_m2s_cpu0_dbus_we; |
| wire wb_m2s_cpu0_dbus_cyc; |
| wire wb_m2s_cpu0_dbus_stb; |
| wire [2:0] wb_m2s_cpu0_dbus_cti; |
| wire [1:0] wb_m2s_cpu0_dbus_bte; |
| wire [31:0] wb_s2m_cpu0_dbus_dat; |
| wire wb_s2m_cpu0_dbus_ack; |
| wire wb_s2m_cpu0_dbus_err; |
| wire wb_s2m_cpu0_dbus_rty; |
| wire [31:0] wb_m2s_mgmt_adr; |
| wire [31:0] wb_m2s_mgmt_dat; |
| wire [3:0] wb_m2s_mgmt_sel; |
| wire wb_m2s_mgmt_we; |
| wire wb_m2s_mgmt_cyc; |
| wire wb_m2s_mgmt_stb; |
| wire [2:0] wb_m2s_mgmt_cti; |
| wire [1:0] wb_m2s_mgmt_bte; |
| wire [31:0] wb_s2m_mgmt_dat; |
| wire wb_s2m_mgmt_ack; |
| wire wb_s2m_mgmt_err; |
| wire wb_s2m_mgmt_rty; |
| wire [31:0] wb_m2s_timer0_adr; |
| wire [31:0] wb_m2s_timer0_dat; |
| wire [3:0] wb_m2s_timer0_sel; |
| wire wb_m2s_timer0_we; |
| wire wb_m2s_timer0_cyc; |
| wire wb_m2s_timer0_stb; |
| wire [2:0] wb_m2s_timer0_cti; |
| wire [1:0] wb_m2s_timer0_bte; |
| wire [31:0] wb_s2m_timer0_dat; |
| wire wb_s2m_timer0_ack; |
| wire wb_s2m_timer0_err; |
| wire wb_s2m_timer0_rty; |
| wire [31:0] wb_m2s_uart0_adr; |
| wire [31:0] wb_m2s_uart0_dat; |
| wire [3:0] wb_m2s_uart0_sel; |
| wire wb_m2s_uart0_we; |
| wire wb_m2s_uart0_cyc; |
| wire wb_m2s_uart0_stb; |
| wire [2:0] wb_m2s_uart0_cti; |
| wire [1:0] wb_m2s_uart0_bte; |
| wire [31:0] wb_s2m_uart0_dat; |
| wire wb_s2m_uart0_ack; |
| wire wb_s2m_uart0_err; |
| wire wb_s2m_uart0_rty; |
| wire [31:0] wb_m2s_led0_adr; |
| wire [31:0] wb_m2s_led0_dat; |
| wire [3:0] wb_m2s_led0_sel; |
| wire wb_m2s_led0_we; |
| wire wb_m2s_led0_cyc; |
| wire wb_m2s_led0_stb; |
| wire [2:0] wb_m2s_led0_cti; |
| wire [1:0] wb_m2s_led0_bte; |
| wire [31:0] wb_s2m_led0_dat; |
| wire wb_s2m_led0_ack; |
| wire wb_s2m_led0_err; |
| wire wb_s2m_led0_rty; |
| wire [31:0] wb_m2s_cpu0_rom_adr; |
| wire [31:0] wb_m2s_cpu0_rom_dat; |
| wire [3:0] wb_m2s_cpu0_rom_sel; |
| wire wb_m2s_cpu0_rom_we; |
| wire wb_m2s_cpu0_rom_cyc; |
| wire wb_m2s_cpu0_rom_stb; |
| wire [2:0] wb_m2s_cpu0_rom_cti; |
| wire [1:0] wb_m2s_cpu0_rom_bte; |
| wire [31:0] wb_s2m_cpu0_rom_dat; |
| wire wb_s2m_cpu0_rom_ack; |
| wire wb_s2m_cpu0_rom_err; |
| wire wb_s2m_cpu0_rom_rty; |
| wire [31:0] wb_m2s_cpu0_ram_adr; |
| wire [31:0] wb_m2s_cpu0_ram_dat; |
| wire [3:0] wb_m2s_cpu0_ram_sel; |
| wire wb_m2s_cpu0_ram_we; |
| wire wb_m2s_cpu0_ram_cyc; |
| wire wb_m2s_cpu0_ram_stb; |
| wire [2:0] wb_m2s_cpu0_ram_cti; |
| wire [1:0] wb_m2s_cpu0_ram_bte; |
| wire [31:0] wb_s2m_cpu0_ram_dat; |
| wire wb_s2m_cpu0_ram_ack; |
| wire wb_s2m_cpu0_ram_err; |
| wire wb_s2m_cpu0_ram_rty; |
| |
| wb_interconA wb_interconA0 |
| (.wb_clk_i (wb_clk), |
| .wb_rst_i (wb_rst), |
| .wb_cpu0_ibus_adr_i (wb_m2s_cpu0_ibus_adr), |
| .wb_cpu0_ibus_dat_i (wb_m2s_cpu0_ibus_dat), |
| .wb_cpu0_ibus_sel_i (wb_m2s_cpu0_ibus_sel), |
| .wb_cpu0_ibus_we_i (wb_m2s_cpu0_ibus_we), |
| .wb_cpu0_ibus_cyc_i (wb_m2s_cpu0_ibus_cyc), |
| .wb_cpu0_ibus_stb_i (wb_m2s_cpu0_ibus_stb), |
| .wb_cpu0_ibus_cti_i (wb_m2s_cpu0_ibus_cti), |
| .wb_cpu0_ibus_bte_i (wb_m2s_cpu0_ibus_bte), |
| .wb_cpu0_ibus_dat_o (wb_s2m_cpu0_ibus_dat), |
| .wb_cpu0_ibus_ack_o (wb_s2m_cpu0_ibus_ack), |
| .wb_cpu0_ibus_err_o (wb_s2m_cpu0_ibus_err), |
| .wb_cpu0_ibus_rty_o (wb_s2m_cpu0_ibus_rty), |
| .wb_cpu0_dbus_adr_i (wb_m2s_cpu0_dbus_adr), |
| .wb_cpu0_dbus_dat_i (wb_m2s_cpu0_dbus_dat), |
| .wb_cpu0_dbus_sel_i (wb_m2s_cpu0_dbus_sel), |
| .wb_cpu0_dbus_we_i (wb_m2s_cpu0_dbus_we), |
| .wb_cpu0_dbus_cyc_i (wb_m2s_cpu0_dbus_cyc), |
| .wb_cpu0_dbus_stb_i (wb_m2s_cpu0_dbus_stb), |
| .wb_cpu0_dbus_cti_i (wb_m2s_cpu0_dbus_cti), |
| .wb_cpu0_dbus_bte_i (wb_m2s_cpu0_dbus_bte), |
| .wb_cpu0_dbus_dat_o (wb_s2m_cpu0_dbus_dat), |
| .wb_cpu0_dbus_ack_o (wb_s2m_cpu0_dbus_ack), |
| .wb_cpu0_dbus_err_o (wb_s2m_cpu0_dbus_err), |
| .wb_cpu0_dbus_rty_o (wb_s2m_cpu0_dbus_rty), |
| .wb_mgmt_adr_i (wb_m2s_mgmt_adr), |
| .wb_mgmt_dat_i (wb_m2s_mgmt_dat), |
| .wb_mgmt_sel_i (wb_m2s_mgmt_sel), |
| .wb_mgmt_we_i (wb_m2s_mgmt_we), |
| .wb_mgmt_cyc_i (wb_m2s_mgmt_cyc), |
| .wb_mgmt_stb_i (wb_m2s_mgmt_stb), |
| .wb_mgmt_cti_i (wb_m2s_mgmt_cti), |
| .wb_mgmt_bte_i (wb_m2s_mgmt_bte), |
| .wb_mgmt_dat_o (wb_s2m_mgmt_dat), |
| .wb_mgmt_ack_o (wb_s2m_mgmt_ack), |
| .wb_mgmt_err_o (wb_s2m_mgmt_err), |
| .wb_mgmt_rty_o (wb_s2m_mgmt_rty), |
| .wb_timer0_adr_o (wb_m2s_timer0_adr), |
| .wb_timer0_dat_o (wb_m2s_timer0_dat), |
| .wb_timer0_sel_o (wb_m2s_timer0_sel), |
| .wb_timer0_we_o (wb_m2s_timer0_we), |
| .wb_timer0_cyc_o (wb_m2s_timer0_cyc), |
| .wb_timer0_stb_o (wb_m2s_timer0_stb), |
| .wb_timer0_cti_o (wb_m2s_timer0_cti), |
| .wb_timer0_bte_o (wb_m2s_timer0_bte), |
| .wb_timer0_dat_i (wb_s2m_timer0_dat), |
| .wb_timer0_ack_i (wb_s2m_timer0_ack), |
| .wb_timer0_err_i (wb_s2m_timer0_err), |
| .wb_timer0_rty_i (wb_s2m_timer0_rty), |
| .wb_uart0_adr_o (wb_m2s_uart0_adr), |
| .wb_uart0_dat_o (wb_m2s_uart0_dat), |
| .wb_uart0_sel_o (wb_m2s_uart0_sel), |
| .wb_uart0_we_o (wb_m2s_uart0_we), |
| .wb_uart0_cyc_o (wb_m2s_uart0_cyc), |
| .wb_uart0_stb_o (wb_m2s_uart0_stb), |
| .wb_uart0_cti_o (wb_m2s_uart0_cti), |
| .wb_uart0_bte_o (wb_m2s_uart0_bte), |
| .wb_uart0_dat_i (wb_s2m_uart0_dat), |
| .wb_uart0_ack_i (wb_s2m_uart0_ack), |
| .wb_uart0_err_i (wb_s2m_uart0_err), |
| .wb_uart0_rty_i (wb_s2m_uart0_rty), |
| .wb_led0_adr_o (wb_m2s_led0_adr), |
| .wb_led0_dat_o (wb_m2s_led0_dat), |
| .wb_led0_sel_o (wb_m2s_led0_sel), |
| .wb_led0_we_o (wb_m2s_led0_we), |
| .wb_led0_cyc_o (wb_m2s_led0_cyc), |
| .wb_led0_stb_o (wb_m2s_led0_stb), |
| .wb_led0_cti_o (wb_m2s_led0_cti), |
| .wb_led0_bte_o (wb_m2s_led0_bte), |
| .wb_led0_dat_i (wb_s2m_led0_dat), |
| .wb_led0_ack_i (wb_s2m_led0_ack), |
| .wb_led0_err_i (wb_s2m_led0_err), |
| .wb_led0_rty_i (wb_s2m_led0_rty), |
| .wb_cpu0_rom_adr_o (wb_m2s_cpu0_rom_adr), |
| .wb_cpu0_rom_dat_o (wb_m2s_cpu0_rom_dat), |
| .wb_cpu0_rom_sel_o (wb_m2s_cpu0_rom_sel), |
| .wb_cpu0_rom_we_o (wb_m2s_cpu0_rom_we), |
| .wb_cpu0_rom_cyc_o (wb_m2s_cpu0_rom_cyc), |
| .wb_cpu0_rom_stb_o (wb_m2s_cpu0_rom_stb), |
| .wb_cpu0_rom_cti_o (wb_m2s_cpu0_rom_cti), |
| .wb_cpu0_rom_bte_o (wb_m2s_cpu0_rom_bte), |
| .wb_cpu0_rom_dat_i (wb_s2m_cpu0_rom_dat), |
| .wb_cpu0_rom_ack_i (wb_s2m_cpu0_rom_ack), |
| .wb_cpu0_rom_err_i (wb_s2m_cpu0_rom_err), |
| .wb_cpu0_rom_rty_i (wb_s2m_cpu0_rom_rty), |
| .wb_cpu0_ram_adr_o (wb_m2s_cpu0_ram_adr), |
| .wb_cpu0_ram_dat_o (wb_m2s_cpu0_ram_dat), |
| .wb_cpu0_ram_sel_o (wb_m2s_cpu0_ram_sel), |
| .wb_cpu0_ram_we_o (wb_m2s_cpu0_ram_we), |
| .wb_cpu0_ram_cyc_o (wb_m2s_cpu0_ram_cyc), |
| .wb_cpu0_ram_stb_o (wb_m2s_cpu0_ram_stb), |
| .wb_cpu0_ram_cti_o (wb_m2s_cpu0_ram_cti), |
| .wb_cpu0_ram_bte_o (wb_m2s_cpu0_ram_bte), |
| .wb_cpu0_ram_dat_i (wb_s2m_cpu0_ram_dat), |
| .wb_cpu0_ram_ack_i (wb_s2m_cpu0_ram_ack), |
| .wb_cpu0_ram_err_i (wb_s2m_cpu0_ram_err), |
| .wb_cpu0_ram_rty_i (wb_s2m_cpu0_ram_rty)); |
| |