diff --git a/openlane/user_proj/config.tcl b/openlane/user_proj/config.tcl
index 4d4f08c..f031102 100755
--- a/openlane/user_proj/config.tcl
+++ b/openlane/user_proj/config.tcl
@@ -39,7 +39,7 @@
         $script_dir/src/wb_led.v \
         $script_dir/src/timer_wb.v"
 
-#set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/includes]
+set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/src]
 
 set ::env(CLOCK_PORT) "wb_clk_i"
 set ::env(CLOCK_PERIOD) 10
diff --git a/openlane/user_proj/src/simpleuart.v b/openlane/user_proj/src/simpleuart.v
index 280f9b2..57d4a23 100644
--- a/openlane/user_proj/src/simpleuart.v
+++ b/openlane/user_proj/src/simpleuart.v
@@ -20,8 +20,8 @@
  *  SPDX-License-Identifier: ISC
  */
 
-module simpleuart_wb # (
-    parameter BASE_ADR = 32'h4000_1000,
+module simpleuartA_wb # (
+    parameter BASE_ADR = 32'h 2000_0000,
     parameter CLK_DIV = 8'h00,
     parameter DATA = 8'h04,
     parameter CONFIG = 8'h08
@@ -44,31 +44,31 @@
     input  ser_rx
 
 );
-    wire [31:0] simpleuart_reg_div_do;
-    wire [31:0] simpleuart_reg_dat_do;
-    wire [31:0] simpleuart_reg_cfg_do;
+    wire [31:0] simpleuartA_reg_div_do;
+    wire [31:0] simpleuartA_reg_dat_do;
+    wire [31:0] simpleuartA_reg_cfg_do;
     wire reg_dat_wait;
 
     wire resetn = ~wb_rst_i;
     wire valid = wb_stb_i && wb_cyc_i; 
-    wire simpleuart_reg_div_sel = valid && (wb_adr_i == (BASE_ADR | CLK_DIV));
-    wire simpleuart_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
-    wire simpleuart_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
+    wire simpleuartA_reg_div_sel = valid && (wb_adr_i == (BASE_ADR | CLK_DIV));
+    wire simpleuartA_reg_dat_sel = valid && (wb_adr_i == (BASE_ADR | DATA));
+    wire simpleuartA_reg_cfg_sel = valid && (wb_adr_i == (BASE_ADR | CONFIG));
 
-    wire [3:0] reg_div_we = simpleuart_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000; 
-    wire reg_dat_we = simpleuart_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;      // simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0
-    wire reg_cfg_we = simpleuart_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; 
+    wire [3:0] reg_div_we = simpleuartA_reg_div_sel ? (wb_sel_i & {4{wb_we_i}}): 4'b 0000; 
+    wire reg_dat_we = simpleuartA_reg_dat_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0;      // simpleuartA_reg_dat_sel ? mem_wstrb[0] : 1'b 0
+    wire reg_cfg_we = simpleuartA_reg_cfg_sel ? (wb_sel_i[0] & wb_we_i): 1'b 0; 
 
     wire [31:0] mem_wdata = wb_dat_i;
-    wire reg_dat_re = simpleuart_reg_dat_sel && !wb_sel_i && ~wb_we_i; // read_enable
+    wire reg_dat_re = simpleuartA_reg_dat_sel && !wb_sel_i && ~wb_we_i; // read_enable
 
-    assign wb_dat_o = simpleuart_reg_div_sel ? simpleuart_reg_div_do:
-		      simpleuart_reg_cfg_sel ? simpleuart_reg_cfg_do:
-					       simpleuart_reg_dat_do;
-    assign wb_ack_o = (simpleuart_reg_div_sel || simpleuart_reg_dat_sel
-			|| simpleuart_reg_cfg_sel) && (!reg_dat_wait);
+    assign wb_dat_o = simpleuartA_reg_div_sel ? simpleuartA_reg_div_do:
+		      simpleuartA_reg_cfg_sel ? simpleuartA_reg_cfg_do:
+					       simpleuartA_reg_dat_do;
+    assign wb_ack_o = (simpleuartA_reg_div_sel || simpleuartA_reg_dat_sel
+			|| simpleuartA_reg_cfg_sel) && (!reg_dat_wait);
     
-    simpleuart simpleuart (
+    simpleuartA simpleuartA (
         .clk    (wb_clk_i),
         .resetn (resetn),
 
@@ -78,22 +78,22 @@
 
         .reg_div_we  (reg_div_we), 
         .reg_div_di  (mem_wdata),
-        .reg_div_do  (simpleuart_reg_div_do),
+        .reg_div_do  (simpleuartA_reg_div_do),
 
         .reg_cfg_we  (reg_cfg_we), 
         .reg_cfg_di  (mem_wdata),
-        .reg_cfg_do  (simpleuart_reg_cfg_do),
+        .reg_cfg_do  (simpleuartA_reg_cfg_do),
 
         .reg_dat_we  (reg_dat_we),
         .reg_dat_re  (reg_dat_re),
         .reg_dat_di  (mem_wdata),
-        .reg_dat_do  (simpleuart_reg_dat_do),
+        .reg_dat_do  (simpleuartA_reg_dat_do),
         .reg_dat_wait(reg_dat_wait)
     );
 
 endmodule
 
-module simpleuart (
+module simpleuartA (
     input clk,
     input resetn,
 
diff --git a/openlane/user_proj/src/soc.v b/openlane/user_proj/src/soc.v
index c50d0ac..afda746 100644
--- a/openlane/user_proj/src/soc.v
+++ b/openlane/user_proj/src/soc.v
@@ -9,8 +9,11 @@
   inout vccd1,	// User area 1 1.8V supply
   inout vssd1,	// User area 1 digital ground
 `endif
-  input clk_i,
-  input rst_i,
+  input clk,
+  input rst,
+
+  input wb_clk,
+  input wb_rst,
 
   output LED,
   input MCU_UART_TX,
@@ -22,14 +25,14 @@
   output jtag_tdo,
   input jtag_tck,
 
-  input mprj_ack_i,
-	input [31:0] mprj_dat_i,
-  output mprj_cyc_o,
-	output mprj_stb_o,
-	output mprj_we_o,
-	output [3:0] mprj_sel_o,
-	output [31:0] mprj_adr_o,
+  output mprj_ack_o,
 	output [31:0] mprj_dat_o,
+	input [31:0] mprj_dat_i,
+  input mprj_cyc_i,
+	input mprj_stb_i,
+	input mprj_we_i,
+	input [3:0] mprj_sel_i,
+	input [31:0] mprj_adr_i,
 
   output [3:0] o_wmask0,
   output [8:0] o_waddr0,
@@ -37,241 +40,30 @@
   input [31:0] i_dout0,
   output o_web0,
   output o_csb0,
-  output [8:0] o_addr1,
-  input [31:0] i_dout1,
-  output o_csb1,
 
   output [3:0] o_wmask0_1,
   output [8:0] o_waddr0_1,
   output [31:0] o_din0_1,
   input [31:0] i_dout0_1,
   output o_web0_1,
-  output o_csb0_1,
-  output [8:0] o_addr1_1,
-  input [31:0] i_dout1_1,
-  output o_csb1_1
+  output o_csb0_1
 );
 
-/***************************************************************************/
-// THE BASE ADDRESSES SHOULD MATCH yb_interconnect.yml
+`include "wb_interconnect.vh"
 parameter ROM_BASE_ADDRESS =    32'h3000_0000;
-parameter RAM_BASE_ADDRESS =    32'h3000_3000;
-parameter TIMER_BASE_ADDRESS =  32'h4000_0000;
-parameter UART_BASE_ADR =       32'h4000_1000;
-parameter LED_BASE_ADR =        32'h4000_2000;
-//`include "openlane_test/wb_interconnect.vh"
-// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
-// ANY MANUAL CHANGES WILL BE LOST
-wire [31:0] wb_m2s_cpu0_ibus_adr;
-wire [31:0] wb_m2s_cpu0_ibus_dat;
-wire  [3:0] wb_m2s_cpu0_ibus_sel;
-wire        wb_m2s_cpu0_ibus_we;
-wire        wb_m2s_cpu0_ibus_cyc;
-wire        wb_m2s_cpu0_ibus_stb;
-wire  [2:0] wb_m2s_cpu0_ibus_cti;
-wire  [1:0] wb_m2s_cpu0_ibus_bte;
-wire [31:0] wb_s2m_cpu0_ibus_dat;
-wire        wb_s2m_cpu0_ibus_ack;
-wire        wb_s2m_cpu0_ibus_err;
-wire        wb_s2m_cpu0_ibus_rty;
-wire [31:0] wb_m2s_cpu0_dbus_adr;
-wire [31:0] wb_m2s_cpu0_dbus_dat;
-wire  [3:0] wb_m2s_cpu0_dbus_sel;
-wire        wb_m2s_cpu0_dbus_we;
-wire        wb_m2s_cpu0_dbus_cyc;
-wire        wb_m2s_cpu0_dbus_stb;
-wire  [2:0] wb_m2s_cpu0_dbus_cti;
-wire  [1:0] wb_m2s_cpu0_dbus_bte;
-wire [31:0] wb_s2m_cpu0_dbus_dat;
-wire        wb_s2m_cpu0_dbus_ack;
-wire        wb_s2m_cpu0_dbus_err;
-wire        wb_s2m_cpu0_dbus_rty;
-wire [31:0] wb_m2s_mgmt_adr;
-wire [31:0] wb_m2s_mgmt_dat;
-wire  [3:0] wb_m2s_mgmt_sel;
-wire        wb_m2s_mgmt_we;
-wire        wb_m2s_mgmt_cyc;
-wire        wb_m2s_mgmt_stb;
-wire  [2:0] wb_m2s_mgmt_cti;
-wire  [1:0] wb_m2s_mgmt_bte;
-wire [31:0] wb_s2m_mgmt_dat;
-wire        wb_s2m_mgmt_ack;
-wire        wb_s2m_mgmt_err;
-wire        wb_s2m_mgmt_rty;
-wire [31:0] wb_m2s_timer0_adr;
-wire [31:0] wb_m2s_timer0_dat;
-wire  [3:0] wb_m2s_timer0_sel;
-wire        wb_m2s_timer0_we;
-wire        wb_m2s_timer0_cyc;
-wire        wb_m2s_timer0_stb;
-wire  [2:0] wb_m2s_timer0_cti;
-wire  [1:0] wb_m2s_timer0_bte;
-wire [31:0] wb_s2m_timer0_dat;
-wire        wb_s2m_timer0_ack;
-wire        wb_s2m_timer0_err;
-wire        wb_s2m_timer0_rty;
-wire [31:0] wb_m2s_uart0_adr;
-wire [31:0] wb_m2s_uart0_dat;
-wire  [3:0] wb_m2s_uart0_sel;
-wire        wb_m2s_uart0_we;
-wire        wb_m2s_uart0_cyc;
-wire        wb_m2s_uart0_stb;
-wire  [2:0] wb_m2s_uart0_cti;
-wire  [1:0] wb_m2s_uart0_bte;
-wire [31:0] wb_s2m_uart0_dat;
-wire        wb_s2m_uart0_ack;
-wire        wb_s2m_uart0_err;
-wire        wb_s2m_uart0_rty;
-wire [31:0] wb_m2s_led0_adr;
-wire [31:0] wb_m2s_led0_dat;
-wire  [3:0] wb_m2s_led0_sel;
-wire        wb_m2s_led0_we;
-wire        wb_m2s_led0_cyc;
-wire        wb_m2s_led0_stb;
-wire  [2:0] wb_m2s_led0_cti;
-wire  [1:0] wb_m2s_led0_bte;
-wire [31:0] wb_s2m_led0_dat;
-wire        wb_s2m_led0_ack;
-wire        wb_s2m_led0_err;
-wire        wb_s2m_led0_rty;
-wire [31:0] wb_m2s_cpu0_rom_adr;
-wire [31:0] wb_m2s_cpu0_rom_dat;
-wire  [3:0] wb_m2s_cpu0_rom_sel;
-wire        wb_m2s_cpu0_rom_we;
-wire        wb_m2s_cpu0_rom_cyc;
-wire        wb_m2s_cpu0_rom_stb;
-wire  [2:0] wb_m2s_cpu0_rom_cti;
-wire  [1:0] wb_m2s_cpu0_rom_bte;
-wire [31:0] wb_s2m_cpu0_rom_dat;
-wire        wb_s2m_cpu0_rom_ack;
-wire        wb_s2m_cpu0_rom_err;
-wire        wb_s2m_cpu0_rom_rty;
-wire [31:0] wb_m2s_cpu0_ram_adr;
-wire [31:0] wb_m2s_cpu0_ram_dat;
-wire  [3:0] wb_m2s_cpu0_ram_sel;
-wire        wb_m2s_cpu0_ram_we;
-wire        wb_m2s_cpu0_ram_cyc;
-wire        wb_m2s_cpu0_ram_stb;
-wire  [2:0] wb_m2s_cpu0_ram_cti;
-wire  [1:0] wb_m2s_cpu0_ram_bte;
-wire [31:0] wb_s2m_cpu0_ram_dat;
-wire        wb_s2m_cpu0_ram_ack;
-wire        wb_s2m_cpu0_ram_err;
-wire        wb_s2m_cpu0_ram_rty;
+parameter RAM_BASE_ADDRESS =    32'h3000_1000;
+parameter TIMER_BASE_ADDRESS =  32'h30ff_ff00;
+parameter UART_BASE_ADR =       32'h30ff_fe00;
+parameter LED_BASE_ADR =        32'h30ff_fd00;
 
-wb_interconnect wb_intercon0(
-  .wb_clk_i           (wb_clk),
-  .wb_rst_i           (wb_rst),
-  .wb_cpu0_ibus_adr_i (wb_m2s_cpu0_ibus_adr),
-  .wb_cpu0_ibus_dat_i (wb_m2s_cpu0_ibus_dat),
-  .wb_cpu0_ibus_sel_i (wb_m2s_cpu0_ibus_sel),
-  .wb_cpu0_ibus_we_i  (wb_m2s_cpu0_ibus_we),
-  .wb_cpu0_ibus_cyc_i (wb_m2s_cpu0_ibus_cyc),
-  .wb_cpu0_ibus_stb_i (wb_m2s_cpu0_ibus_stb),
-  .wb_cpu0_ibus_cti_i (wb_m2s_cpu0_ibus_cti),
-  .wb_cpu0_ibus_bte_i (wb_m2s_cpu0_ibus_bte),
-  .wb_cpu0_ibus_dat_o (wb_s2m_cpu0_ibus_dat),
-  .wb_cpu0_ibus_ack_o (wb_s2m_cpu0_ibus_ack),
-  .wb_cpu0_ibus_err_o (wb_s2m_cpu0_ibus_err),
-  .wb_cpu0_ibus_rty_o (wb_s2m_cpu0_ibus_rty),
-  .wb_cpu0_dbus_adr_i (wb_m2s_cpu0_dbus_adr),
-  .wb_cpu0_dbus_dat_i (wb_m2s_cpu0_dbus_dat),
-  .wb_cpu0_dbus_sel_i (wb_m2s_cpu0_dbus_sel),
-  .wb_cpu0_dbus_we_i  (wb_m2s_cpu0_dbus_we),
-  .wb_cpu0_dbus_cyc_i (wb_m2s_cpu0_dbus_cyc),
-  .wb_cpu0_dbus_stb_i (wb_m2s_cpu0_dbus_stb),
-  .wb_cpu0_dbus_cti_i (wb_m2s_cpu0_dbus_cti),
-  .wb_cpu0_dbus_bte_i (wb_m2s_cpu0_dbus_bte),
-  .wb_cpu0_dbus_dat_o (wb_s2m_cpu0_dbus_dat),
-  .wb_cpu0_dbus_ack_o (wb_s2m_cpu0_dbus_ack),
-  .wb_cpu0_dbus_err_o (wb_s2m_cpu0_dbus_err),
-  .wb_cpu0_dbus_rty_o (wb_s2m_cpu0_dbus_rty),
-  .wb_mgmt_adr_i      (wb_m2s_mgmt_adr),
-  .wb_mgmt_dat_i      (wb_m2s_mgmt_dat),
-  .wb_mgmt_sel_i      (wb_m2s_mgmt_sel),
-  .wb_mgmt_we_i       (wb_m2s_mgmt_we),
-  .wb_mgmt_cyc_i      (wb_m2s_mgmt_cyc),
-  .wb_mgmt_stb_i      (wb_m2s_mgmt_stb),
-  .wb_mgmt_cti_i      (wb_m2s_mgmt_cti),
-  .wb_mgmt_bte_i      (wb_m2s_mgmt_bte),
-  .wb_mgmt_dat_o      (wb_s2m_mgmt_dat),
-  .wb_mgmt_ack_o      (wb_s2m_mgmt_ack),
-  .wb_mgmt_err_o      (wb_s2m_mgmt_err),
-  .wb_mgmt_rty_o      (wb_s2m_mgmt_rty),
-  .wb_timer0_adr_o    (wb_m2s_timer0_adr),
-  .wb_timer0_dat_o    (wb_m2s_timer0_dat),
-  .wb_timer0_sel_o    (wb_m2s_timer0_sel),
-  .wb_timer0_we_o     (wb_m2s_timer0_we),
-  .wb_timer0_cyc_o    (wb_m2s_timer0_cyc),
-  .wb_timer0_stb_o    (wb_m2s_timer0_stb),
-  .wb_timer0_cti_o    (wb_m2s_timer0_cti),
-  .wb_timer0_bte_o    (wb_m2s_timer0_bte),
-  .wb_timer0_dat_i    (wb_s2m_timer0_dat),
-  .wb_timer0_ack_i    (wb_s2m_timer0_ack),
-  .wb_timer0_err_i    (wb_s2m_timer0_err),
-  .wb_timer0_rty_i    (wb_s2m_timer0_rty),
-  .wb_uart0_adr_o     (wb_m2s_uart0_adr),
-  .wb_uart0_dat_o     (wb_m2s_uart0_dat),
-  .wb_uart0_sel_o     (wb_m2s_uart0_sel),
-  .wb_uart0_we_o      (wb_m2s_uart0_we),
-  .wb_uart0_cyc_o     (wb_m2s_uart0_cyc),
-  .wb_uart0_stb_o     (wb_m2s_uart0_stb),
-  .wb_uart0_cti_o     (wb_m2s_uart0_cti),
-  .wb_uart0_bte_o     (wb_m2s_uart0_bte),
-  .wb_uart0_dat_i     (wb_s2m_uart0_dat),
-  .wb_uart0_ack_i     (wb_s2m_uart0_ack),
-  .wb_uart0_err_i     (wb_s2m_uart0_err),
-  .wb_uart0_rty_i     (wb_s2m_uart0_rty),
-  .wb_led0_adr_o      (wb_m2s_led0_adr),
-  .wb_led0_dat_o      (wb_m2s_led0_dat),
-  .wb_led0_sel_o      (wb_m2s_led0_sel),
-  .wb_led0_we_o       (wb_m2s_led0_we),
-  .wb_led0_cyc_o      (wb_m2s_led0_cyc),
-  .wb_led0_stb_o      (wb_m2s_led0_stb),
-  .wb_led0_cti_o      (wb_m2s_led0_cti),
-  .wb_led0_bte_o      (wb_m2s_led0_bte),
-  .wb_led0_dat_i      (wb_s2m_led0_dat),
-  .wb_led0_ack_i      (wb_s2m_led0_ack),
-  .wb_led0_err_i      (wb_s2m_led0_err),
-  .wb_led0_rty_i      (wb_s2m_led0_rty),
-  .wb_cpu0_rom_adr_o  (wb_m2s_cpu0_rom_adr),
-  .wb_cpu0_rom_dat_o  (wb_m2s_cpu0_rom_dat),
-  .wb_cpu0_rom_sel_o  (wb_m2s_cpu0_rom_sel),
-  .wb_cpu0_rom_we_o   (wb_m2s_cpu0_rom_we),
-  .wb_cpu0_rom_cyc_o  (wb_m2s_cpu0_rom_cyc),
-  .wb_cpu0_rom_stb_o  (wb_m2s_cpu0_rom_stb),
-  .wb_cpu0_rom_cti_o  (wb_m2s_cpu0_rom_cti),
-  .wb_cpu0_rom_bte_o  (wb_m2s_cpu0_rom_bte),
-  .wb_cpu0_rom_dat_i  (wb_s2m_cpu0_rom_dat),
-  .wb_cpu0_rom_ack_i  (wb_s2m_cpu0_rom_ack),
-  .wb_cpu0_rom_err_i  (wb_s2m_cpu0_rom_err),
-  .wb_cpu0_rom_rty_i  (wb_s2m_cpu0_rom_rty),
-  .wb_cpu0_ram_adr_o  (wb_m2s_cpu0_ram_adr),
-  .wb_cpu0_ram_dat_o  (wb_m2s_cpu0_ram_dat),
-  .wb_cpu0_ram_sel_o  (wb_m2s_cpu0_ram_sel),
-  .wb_cpu0_ram_we_o   (wb_m2s_cpu0_ram_we),
-  .wb_cpu0_ram_cyc_o  (wb_m2s_cpu0_ram_cyc),
-  .wb_cpu0_ram_stb_o  (wb_m2s_cpu0_ram_stb),
-  .wb_cpu0_ram_cti_o  (wb_m2s_cpu0_ram_cti),
-  .wb_cpu0_ram_bte_o  (wb_m2s_cpu0_ram_bte),
-  .wb_cpu0_ram_dat_i  (wb_s2m_cpu0_ram_dat),
-  .wb_cpu0_ram_ack_i  (wb_s2m_cpu0_ram_ack),
-  .wb_cpu0_ram_err_i  (wb_s2m_cpu0_ram_err),
-  .wb_cpu0_ram_rty_i  (wb_s2m_cpu0_ram_rty)
-);
-/***************************************************************************/
-
-assign mprj_adr_o = wb_m2s_mgmt_adr;
-assign mprj_dat_o = wb_m2s_mgmt_dat;
-assign mprj_sel_o = wb_m2s_mgmt_sel;
-assign mprj_we_o = wb_m2s_mgmt_we;
-assign mprj_cyc_o = wb_m2s_mgmt_cyc;
-assign mprj_stb_o = wb_m2s_mgmt_stb;
-assign wb_s2m_mgmt_dat = mprj_dat_i;
-assign wb_s2m_mgmt_ack = mprj_ack_i;
-
-wire wb_rst = rst_i;
-wire wb_clk = clk_i;
+assign wb_m2s_mgmt_adr = mprj_adr_i;
+assign wb_m2s_mgmt_dat = mprj_dat_i;
+assign wb_m2s_mgmt_sel = mprj_sel_i;
+assign wb_m2s_mgmt_we = mprj_we_i;
+assign wb_m2s_mgmt_cyc = mprj_cyc_i;
+assign wb_m2s_mgmt_stb = mprj_stb_i;
+assign mprj_dat_o = wb_s2m_mgmt_dat;
+assign mprj_ack_o = wb_s2m_mgmt_ack;
 
 `ifdef USE_MEMRAM
 wb_ram cpu0_ram (
@@ -329,17 +121,12 @@
   .wbs_stb_i(wb_m2s_cpu0_ram_stb),
   .wbs_dat_o(wb_s2m_cpu0_ram_dat),
   .wbs_ack_o(wb_s2m_cpu0_ram_ack),
-  .ram_clk0(wb_clk),
   .ram_csb0(o_csb0),
   .ram_web0(o_web0),
   .ram_wmask0(o_wmask0),
   .ram_addr0(o_waddr0),
   .ram_din0(o_din0),
-  .ram_dout0(i_dout0),
-  .ram_clk1(wb_clk),
-  .ram_csb1(o_csb1),
-  .ram_addr1(o_addr1),
-  .ram_dout1(i_dout1)
+  .ram_dout0(i_dout0)
 );
 wb_openram_wrapper #(
   .BASE_ADDR(ROM_BASE_ADDRESS),
@@ -359,17 +146,12 @@
   .wbs_stb_i(wb_m2s_cpu0_rom_stb),
   .wbs_dat_o(wb_s2m_cpu0_rom_dat),
   .wbs_ack_o(wb_s2m_cpu0_rom_ack),
-  .ram_clk0(wb_clk),
   .ram_csb0(o_csb0_1),
   .ram_web0(o_web0_1),
   .ram_wmask0(o_wmask0_1),
   .ram_addr0(o_waddr0_1),
   .ram_din0(o_din0_1),
-  .ram_dout0(i_dout0_1),
-  .ram_clk1(wb_clk),
-  .ram_csb1(o_csb1_1),
-  .ram_addr1(o_addr1_1),
-  .ram_dout1(i_dout1_1)
+  .ram_dout0(i_dout0_1)
 );
 `endif //USE_MEMRAM
 
@@ -397,7 +179,9 @@
 
 // Uart for console logging
 `ifndef USE_OBSOLETE_UART
-simpleuart_wb simpleuart (
+simpleuartA_wb #(
+  .BASE_ADR(UART_BASE_ADR)
+) simpleuartA0 (
   .wb_clk_i(wb_clk),
   .wb_rst_i(wb_rst),
   .wb_adr_i(wb_m2s_uart0_adr),      
@@ -476,8 +260,8 @@
   .vssd1(vssd1),	// User area 1 digital ground
 `endif
 */
-  .clk(wb_clk),
-  .reset(wb_rst),
+  .clk(clk),
+  .reset(rst),
 
   .timerInterrupt(timer_interrupt),
   .externalInterrupt(1'b0),
diff --git a/openlane/user_proj/src/user_proj.v b/openlane/user_proj/src/user_proj.v
index 5b14c17..7af1f78 100644
--- a/openlane/user_proj/src/user_proj.v
+++ b/openlane/user_proj/src/user_proj.v
@@ -42,6 +42,8 @@
     inout vccd1,	// User area 1 1.8V supply
     inout vssd1,	// User area 1 digital ground
 `endif
+    input clk_i,
+    input rst_i,
 
     // Wishbone Slave ports (WB MI A)
     input wb_clk_i,
@@ -75,9 +77,6 @@
     input [31:0] i_dout0,
     output o_web0,
     output o_csb0,
-    output [8:0] o_addr1,
-    input [31:0] i_dout1,
-    output o_csb1,
 
     // SRAM1
     output [3:0] o_wmask0_1,
@@ -85,10 +84,7 @@
     output [31:0] o_din0_1,
     input [31:0] i_dout0_1,
     output o_web0_1,
-    output o_csb0_1,
-    output [8:0] o_addr1_1,
-    input [31:0] i_dout1_1,
-    output o_csb1_1
+    output o_csb0_1
 );
 
 //assign io_oeb = 0;
@@ -99,87 +95,79 @@
 */
 assign irq = 3'b0;
 
-wire ser_rx;
+// ser_rx;in
 assign io_oeb[12] = 1'b1;
-assign ser_rx = io_in[12];
 
-wire ser_tx;
+// ser_tx;out
 assign io_oeb[13] = 1'b0;
-assign io_out[13] = ser_tx;
 
-wire jtag_trstb;
+// srst;in
+assign io_oeb[19] = 1'b1;
+
+// jtag_trstb;in
 assign io_oeb[20] = 1'b1;
-assign jtag_trstb = io_in[20];
 
-wire jtag_tms;
+// jtag_tms;in
 assign io_oeb[21] = 1'b1;
-assign jtag_tms = io_in[21];
 
-wire jtag_tdo;
+// jtag_tdo;out
 assign io_oeb[22] = 1'b0;
-assign io_out[22] = jtag_tdo;
 
-wire jtag_tdi;
+// jtag_tdi;in
 assign io_oeb[23] = 1'b1;
-assign jtag_tdi = io_in[23];
 
-wire jtag_tck;
+//  jtag_tck;in
 assign io_oeb[24] = 1'b1;
-assign jtag_tck = io_in[24];
 
-wire led;
+// led;out
 assign io_oeb[25] = 1'b0;
-assign io_out[25] = led;
 
 soc soc(
 `ifdef USE_POWER_PINS
     .vccd1(vccd1),	// User area 1 1.8V power
     .vssd1(vssd1),	// User area 1 digital ground
 `endif
-    .clk_i(wb_clk_i),
-    .rst_i(wb_rst_i),
+    .clk(clk_i),
+    .rst(rst_i | ~io_oeb[19]),
 
-    .LED(led),
-    .MCU_UART_TX(ser_tx),
-    .MCU_UART_RX(ser_rx),
+    .wb_clk(wb_clk_i),
+    .wb_rst(wb_rst_i),
 
-    .jtag_trst(~jtag_trstb),
-    .jtag_tms(jtag_tms),
-    .jtag_tdi(jtag_tdi),
-    .jtag_tdo(jtag_tdo),
-    .jtag_tck(jtag_tck),
+    .LED(io_out[25]),
+    .MCU_UART_TX(io_out[13]),
+    .MCU_UART_RX(io_in[12]),
+
+    .jtag_trst(~io_in[20]),
+    .jtag_tms(io_in[21]),
+    .jtag_tdi(io_in[23]),
+    .jtag_tdo(io_out[22]),
+    .jtag_tck(io_in[24]),
 
     // User Project Slave ports (WB MI A)
-    .mprj_cyc_o(wbs_cyc_i),
-    .mprj_stb_o(wbs_stb_i),
-    .mprj_we_o(wbs_we_i),
-    .mprj_sel_o(wbs_sel_i),
-    .mprj_adr_o(wbs_adr_i),
-    .mprj_dat_o(wbs_dat_i),
-    .mprj_ack_i(wbs_ack_o),
-    .mprj_dat_i(wbs_dat_o),
+    .mprj_cyc_i(wbs_cyc_i),
+    .mprj_stb_i(wbs_stb_i),
+    .mprj_we_i(wbs_we_i),
+    .mprj_sel_i(wbs_sel_i),
+    .mprj_adr_i(wbs_adr_i),
+    .mprj_dat_i(wbs_dat_i),
+    .mprj_ack_o(wbs_ack_o),
+    .mprj_dat_o(wbs_dat_o),
 
     // SRAM
     .o_wmask0(o_wmask0),
     .o_waddr0(o_waddr0),
     .o_din0(o_din0),
     .i_dout0(i_dout0),
-    .o_addr1(o_addr1),
-    .i_dout1(i_dout1),
     .o_web0(o_web0),
     .o_csb0(o_csb0),
-    .o_csb1(o_csb1),
 
     // SRAM1
     .o_wmask0_1(o_wmask0_1),
     .o_waddr0_1(o_waddr0_1),
     .o_din0_1(o_din0_1),
     .i_dout0_1(i_dout0_1),
-    .o_addr1_1(o_addr1_1),
-    .i_dout1_1(i_dout1_1),
     .o_web0_1(o_web0_1),
-    .o_csb0_1(o_csb0_1),
-    .o_csb1_1(o_csb1_1)
+    .o_csb0_1(o_csb0_1)
 );
 
 endmodule
diff --git a/openlane/user_proj/src/wb_arbiter.v b/openlane/user_proj/src/wb_arbiter.v
index 02a7deb..124fa1e 100644
--- a/openlane/user_proj/src/wb_arbiter.v
+++ b/openlane/user_proj/src/wb_arbiter.v
@@ -25,7 +25,7 @@
 module wb_arbiter
  #(parameter dw = 32,
    parameter aw = 32,
-   parameter num_masters = 0)
+   parameter num_masters = 1)
   (
 `ifdef USE_POWER_PINS
     inout vccd1,	// User area 1 1.8V supply
@@ -91,7 +91,12 @@
    arbiter
      #(.NUM_PORTS (num_masters))
    arbiter0
-     (.clk (wb_clk_i),
+     (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+      .clk (wb_clk_i),
       .rst (wb_rst_i),
       .request (wbm_cyc_i),
       .grant (grant),
diff --git a/openlane/user_proj/src/wb_interconnect.v b/openlane/user_proj/src/wb_interconnect.v
index 9bed0be..9533346 100644
--- a/openlane/user_proj/src/wb_interconnect.v
+++ b/openlane/user_proj/src/wb_interconnect.v
@@ -1,8 +1,25 @@
-// THIS FILE IS AUTOGENERATED BY wb_intercon_gen
+// THIS FILE IS AUTOGENERATED BY wb_interconA_gen
 // ANY MANUAL CHANGES WILL BE LOST
-module wb_interconnect
-   (input         wb_clk_i,
+module wb_interconA
+   (
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    input         wb_clk_i,
     input         wb_rst_i,
+    input  [31:0] wb_mgmt_adr_i,
+    input  [31:0] wb_mgmt_dat_i,
+    input   [3:0] wb_mgmt_sel_i,
+    input         wb_mgmt_we_i,
+    input         wb_mgmt_cyc_i,
+    input         wb_mgmt_stb_i,
+    input   [2:0] wb_mgmt_cti_i,
+    input   [1:0] wb_mgmt_bte_i,
+    output [31:0] wb_mgmt_dat_o,
+    output        wb_mgmt_ack_o,
+    output        wb_mgmt_err_o,
+    output        wb_mgmt_rty_o,
     input  [31:0] wb_cpu0_ibus_adr_i,
     input  [31:0] wb_cpu0_ibus_dat_i,
     input   [3:0] wb_cpu0_ibus_sel_i,
@@ -27,18 +44,6 @@
     output        wb_cpu0_dbus_ack_o,
     output        wb_cpu0_dbus_err_o,
     output        wb_cpu0_dbus_rty_o,
-    input  [31:0] wb_mgmt_adr_i,
-    input  [31:0] wb_mgmt_dat_i,
-    input   [3:0] wb_mgmt_sel_i,
-    input         wb_mgmt_we_i,
-    input         wb_mgmt_cyc_i,
-    input         wb_mgmt_stb_i,
-    input   [2:0] wb_mgmt_cti_i,
-    input   [1:0] wb_mgmt_bte_i,
-    output [31:0] wb_mgmt_dat_o,
-    output        wb_mgmt_ack_o,
-    output        wb_mgmt_err_o,
-    output        wb_mgmt_rty_o,
     output [31:0] wb_timer0_adr_o,
     output [31:0] wb_timer0_dat_o,
     output  [3:0] wb_timer0_sel_o,
@@ -75,18 +80,6 @@
     input         wb_led0_ack_i,
     input         wb_led0_err_i,
     input         wb_led0_rty_i,
-    output [31:0] wb_cpu0_rom_adr_o,
-    output [31:0] wb_cpu0_rom_dat_o,
-    output  [3:0] wb_cpu0_rom_sel_o,
-    output        wb_cpu0_rom_we_o,
-    output        wb_cpu0_rom_cyc_o,
-    output        wb_cpu0_rom_stb_o,
-    output  [2:0] wb_cpu0_rom_cti_o,
-    output  [1:0] wb_cpu0_rom_bte_o,
-    input  [31:0] wb_cpu0_rom_dat_i,
-    input         wb_cpu0_rom_ack_i,
-    input         wb_cpu0_rom_err_i,
-    input         wb_cpu0_rom_rty_i,
     output [31:0] wb_cpu0_ram_adr_o,
     output [31:0] wb_cpu0_ram_dat_o,
     output  [3:0] wb_cpu0_ram_sel_o,
@@ -98,8 +91,80 @@
     input  [31:0] wb_cpu0_ram_dat_i,
     input         wb_cpu0_ram_ack_i,
     input         wb_cpu0_ram_err_i,
-    input         wb_cpu0_ram_rty_i);
+    input         wb_cpu0_ram_rty_i,
+    output [31:0] wb_cpu0_rom_adr_o,
+    output [31:0] wb_cpu0_rom_dat_o,
+    output  [3:0] wb_cpu0_rom_sel_o,
+    output        wb_cpu0_rom_we_o,
+    output        wb_cpu0_rom_cyc_o,
+    output        wb_cpu0_rom_stb_o,
+    output  [2:0] wb_cpu0_rom_cti_o,
+    output  [1:0] wb_cpu0_rom_bte_o,
+    input  [31:0] wb_cpu0_rom_dat_i,
+    input         wb_cpu0_rom_ack_i,
+    input         wb_cpu0_rom_err_i,
+    input         wb_cpu0_rom_rty_i);
 
+wire [31:0] wb_m2s_mgmt_cpu0_rom_adr;
+wire [31:0] wb_m2s_mgmt_cpu0_rom_dat;
+wire  [3:0] wb_m2s_mgmt_cpu0_rom_sel;
+wire        wb_m2s_mgmt_cpu0_rom_we;
+wire        wb_m2s_mgmt_cpu0_rom_cyc;
+wire        wb_m2s_mgmt_cpu0_rom_stb;
+wire  [2:0] wb_m2s_mgmt_cpu0_rom_cti;
+wire  [1:0] wb_m2s_mgmt_cpu0_rom_bte;
+wire [31:0] wb_s2m_mgmt_cpu0_rom_dat;
+wire        wb_s2m_mgmt_cpu0_rom_ack;
+wire        wb_s2m_mgmt_cpu0_rom_err;
+wire        wb_s2m_mgmt_cpu0_rom_rty;
+wire [31:0] wb_m2s_mgmt_cpu0_ram_adr;
+wire [31:0] wb_m2s_mgmt_cpu0_ram_dat;
+wire  [3:0] wb_m2s_mgmt_cpu0_ram_sel;
+wire        wb_m2s_mgmt_cpu0_ram_we;
+wire        wb_m2s_mgmt_cpu0_ram_cyc;
+wire        wb_m2s_mgmt_cpu0_ram_stb;
+wire  [2:0] wb_m2s_mgmt_cpu0_ram_cti;
+wire  [1:0] wb_m2s_mgmt_cpu0_ram_bte;
+wire [31:0] wb_s2m_mgmt_cpu0_ram_dat;
+wire        wb_s2m_mgmt_cpu0_ram_ack;
+wire        wb_s2m_mgmt_cpu0_ram_err;
+wire        wb_s2m_mgmt_cpu0_ram_rty;
+wire [31:0] wb_m2s_mgmt_led0_adr;
+wire [31:0] wb_m2s_mgmt_led0_dat;
+wire  [3:0] wb_m2s_mgmt_led0_sel;
+wire        wb_m2s_mgmt_led0_we;
+wire        wb_m2s_mgmt_led0_cyc;
+wire        wb_m2s_mgmt_led0_stb;
+wire  [2:0] wb_m2s_mgmt_led0_cti;
+wire  [1:0] wb_m2s_mgmt_led0_bte;
+wire [31:0] wb_s2m_mgmt_led0_dat;
+wire        wb_s2m_mgmt_led0_ack;
+wire        wb_s2m_mgmt_led0_err;
+wire        wb_s2m_mgmt_led0_rty;
+wire [31:0] wb_m2s_mgmt_uart0_adr;
+wire [31:0] wb_m2s_mgmt_uart0_dat;
+wire  [3:0] wb_m2s_mgmt_uart0_sel;
+wire        wb_m2s_mgmt_uart0_we;
+wire        wb_m2s_mgmt_uart0_cyc;
+wire        wb_m2s_mgmt_uart0_stb;
+wire  [2:0] wb_m2s_mgmt_uart0_cti;
+wire  [1:0] wb_m2s_mgmt_uart0_bte;
+wire [31:0] wb_s2m_mgmt_uart0_dat;
+wire        wb_s2m_mgmt_uart0_ack;
+wire        wb_s2m_mgmt_uart0_err;
+wire        wb_s2m_mgmt_uart0_rty;
+wire [31:0] wb_m2s_mgmt_timer0_adr;
+wire [31:0] wb_m2s_mgmt_timer0_dat;
+wire  [3:0] wb_m2s_mgmt_timer0_sel;
+wire        wb_m2s_mgmt_timer0_we;
+wire        wb_m2s_mgmt_timer0_cyc;
+wire        wb_m2s_mgmt_timer0_stb;
+wire  [2:0] wb_m2s_mgmt_timer0_cti;
+wire  [1:0] wb_m2s_mgmt_timer0_bte;
+wire [31:0] wb_s2m_mgmt_timer0_dat;
+wire        wb_s2m_mgmt_timer0_ack;
+wire        wb_s2m_mgmt_timer0_err;
+wire        wb_s2m_mgmt_timer0_rty;
 wire [31:0] wb_m2s_cpu0_ibus_cpu0_rom_adr;
 wire [31:0] wb_m2s_cpu0_ibus_cpu0_rom_dat;
 wire  [3:0] wb_m2s_cpu0_ibus_cpu0_rom_sel;
@@ -136,30 +201,6 @@
 wire        wb_s2m_cpu0_dbus_cpu0_ram_ack;
 wire        wb_s2m_cpu0_dbus_cpu0_ram_err;
 wire        wb_s2m_cpu0_dbus_cpu0_ram_rty;
-wire [31:0] wb_m2s_cpu0_dbus_timer0_adr;
-wire [31:0] wb_m2s_cpu0_dbus_timer0_dat;
-wire  [3:0] wb_m2s_cpu0_dbus_timer0_sel;
-wire        wb_m2s_cpu0_dbus_timer0_we;
-wire        wb_m2s_cpu0_dbus_timer0_cyc;
-wire        wb_m2s_cpu0_dbus_timer0_stb;
-wire  [2:0] wb_m2s_cpu0_dbus_timer0_cti;
-wire  [1:0] wb_m2s_cpu0_dbus_timer0_bte;
-wire [31:0] wb_s2m_cpu0_dbus_timer0_dat;
-wire        wb_s2m_cpu0_dbus_timer0_ack;
-wire        wb_s2m_cpu0_dbus_timer0_err;
-wire        wb_s2m_cpu0_dbus_timer0_rty;
-wire [31:0] wb_m2s_cpu0_dbus_uart0_adr;
-wire [31:0] wb_m2s_cpu0_dbus_uart0_dat;
-wire  [3:0] wb_m2s_cpu0_dbus_uart0_sel;
-wire        wb_m2s_cpu0_dbus_uart0_we;
-wire        wb_m2s_cpu0_dbus_uart0_cyc;
-wire        wb_m2s_cpu0_dbus_uart0_stb;
-wire  [2:0] wb_m2s_cpu0_dbus_uart0_cti;
-wire  [1:0] wb_m2s_cpu0_dbus_uart0_bte;
-wire [31:0] wb_s2m_cpu0_dbus_uart0_dat;
-wire        wb_s2m_cpu0_dbus_uart0_ack;
-wire        wb_s2m_cpu0_dbus_uart0_err;
-wire        wb_s2m_cpu0_dbus_uart0_rty;
 wire [31:0] wb_m2s_cpu0_dbus_led0_adr;
 wire [31:0] wb_m2s_cpu0_dbus_led0_dat;
 wire  [3:0] wb_m2s_cpu0_dbus_led0_sel;
@@ -172,73 +213,79 @@
 wire        wb_s2m_cpu0_dbus_led0_ack;
 wire        wb_s2m_cpu0_dbus_led0_err;
 wire        wb_s2m_cpu0_dbus_led0_rty;
-wire [31:0] wb_m2s_mgmt_cpu0_rom_adr;
-wire [31:0] wb_m2s_mgmt_cpu0_rom_dat;
-wire  [3:0] wb_m2s_mgmt_cpu0_rom_sel;
-wire        wb_m2s_mgmt_cpu0_rom_we;
-wire        wb_m2s_mgmt_cpu0_rom_cyc;
-wire        wb_m2s_mgmt_cpu0_rom_stb;
-wire  [2:0] wb_m2s_mgmt_cpu0_rom_cti;
-wire  [1:0] wb_m2s_mgmt_cpu0_rom_bte;
-wire [31:0] wb_s2m_mgmt_cpu0_rom_dat;
-wire        wb_s2m_mgmt_cpu0_rom_ack;
-wire        wb_s2m_mgmt_cpu0_rom_err;
-wire        wb_s2m_mgmt_cpu0_rom_rty;
-wire [31:0] wb_m2s_mgmt_cpu0_ram_adr;
-wire [31:0] wb_m2s_mgmt_cpu0_ram_dat;
-wire  [3:0] wb_m2s_mgmt_cpu0_ram_sel;
-wire        wb_m2s_mgmt_cpu0_ram_we;
-wire        wb_m2s_mgmt_cpu0_ram_cyc;
-wire        wb_m2s_mgmt_cpu0_ram_stb;
-wire  [2:0] wb_m2s_mgmt_cpu0_ram_cti;
-wire  [1:0] wb_m2s_mgmt_cpu0_ram_bte;
-wire [31:0] wb_s2m_mgmt_cpu0_ram_dat;
-wire        wb_s2m_mgmt_cpu0_ram_ack;
-wire        wb_s2m_mgmt_cpu0_ram_err;
-wire        wb_s2m_mgmt_cpu0_ram_rty;
-wire [31:0] wb_m2s_mgmt_timer0_adr;
-wire [31:0] wb_m2s_mgmt_timer0_dat;
-wire  [3:0] wb_m2s_mgmt_timer0_sel;
-wire        wb_m2s_mgmt_timer0_we;
-wire        wb_m2s_mgmt_timer0_cyc;
-wire        wb_m2s_mgmt_timer0_stb;
-wire  [2:0] wb_m2s_mgmt_timer0_cti;
-wire  [1:0] wb_m2s_mgmt_timer0_bte;
-wire [31:0] wb_s2m_mgmt_timer0_dat;
-wire        wb_s2m_mgmt_timer0_ack;
-wire        wb_s2m_mgmt_timer0_err;
-wire        wb_s2m_mgmt_timer0_rty;
-wire [31:0] wb_m2s_mgmt_uart0_adr;
-wire [31:0] wb_m2s_mgmt_uart0_dat;
-wire  [3:0] wb_m2s_mgmt_uart0_sel;
-wire        wb_m2s_mgmt_uart0_we;
-wire        wb_m2s_mgmt_uart0_cyc;
-wire        wb_m2s_mgmt_uart0_stb;
-wire  [2:0] wb_m2s_mgmt_uart0_cti;
-wire  [1:0] wb_m2s_mgmt_uart0_bte;
-wire [31:0] wb_s2m_mgmt_uart0_dat;
-wire        wb_s2m_mgmt_uart0_ack;
-wire        wb_s2m_mgmt_uart0_err;
-wire        wb_s2m_mgmt_uart0_rty;
-wire [31:0] wb_m2s_mgmt_led0_adr;
-wire [31:0] wb_m2s_mgmt_led0_dat;
-wire  [3:0] wb_m2s_mgmt_led0_sel;
-wire        wb_m2s_mgmt_led0_we;
-wire        wb_m2s_mgmt_led0_cyc;
-wire        wb_m2s_mgmt_led0_stb;
-wire  [2:0] wb_m2s_mgmt_led0_cti;
-wire  [1:0] wb_m2s_mgmt_led0_bte;
-wire [31:0] wb_s2m_mgmt_led0_dat;
-wire        wb_s2m_mgmt_led0_ack;
-wire        wb_s2m_mgmt_led0_err;
-wire        wb_s2m_mgmt_led0_rty;
+wire [31:0] wb_m2s_cpu0_dbus_uart0_adr;
+wire [31:0] wb_m2s_cpu0_dbus_uart0_dat;
+wire  [3:0] wb_m2s_cpu0_dbus_uart0_sel;
+wire        wb_m2s_cpu0_dbus_uart0_we;
+wire        wb_m2s_cpu0_dbus_uart0_cyc;
+wire        wb_m2s_cpu0_dbus_uart0_stb;
+wire  [2:0] wb_m2s_cpu0_dbus_uart0_cti;
+wire  [1:0] wb_m2s_cpu0_dbus_uart0_bte;
+wire [31:0] wb_s2m_cpu0_dbus_uart0_dat;
+wire        wb_s2m_cpu0_dbus_uart0_ack;
+wire        wb_s2m_cpu0_dbus_uart0_err;
+wire        wb_s2m_cpu0_dbus_uart0_rty;
+wire [31:0] wb_m2s_cpu0_dbus_timer0_adr;
+wire [31:0] wb_m2s_cpu0_dbus_timer0_dat;
+wire  [3:0] wb_m2s_cpu0_dbus_timer0_sel;
+wire        wb_m2s_cpu0_dbus_timer0_we;
+wire        wb_m2s_cpu0_dbus_timer0_cyc;
+wire        wb_m2s_cpu0_dbus_timer0_stb;
+wire  [2:0] wb_m2s_cpu0_dbus_timer0_cti;
+wire  [1:0] wb_m2s_cpu0_dbus_timer0_bte;
+wire [31:0] wb_s2m_cpu0_dbus_timer0_dat;
+wire        wb_s2m_cpu0_dbus_timer0_ack;
+wire        wb_s2m_cpu0_dbus_timer0_err;
+wire        wb_s2m_cpu0_dbus_timer0_rty;
+
+wb_mux
+  #(.num_slaves (5),
+    .MATCH_ADDR ({32'h30000000, 32'h30001000, 32'h30fffd00, 32'h30fffe00, 32'h30ffff00}),
+    .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hffffff00, 32'hffffff00, 32'hffffff00}))
+ wb_mux_mgmt
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i (wb_mgmt_adr_i),
+    .wbm_dat_i (wb_mgmt_dat_i),
+    .wbm_sel_i (wb_mgmt_sel_i),
+    .wbm_we_i  (wb_mgmt_we_i),
+    .wbm_cyc_i (wb_mgmt_cyc_i),
+    .wbm_stb_i (wb_mgmt_stb_i),
+    .wbm_cti_i (wb_mgmt_cti_i),
+    .wbm_bte_i (wb_mgmt_bte_i),
+    .wbm_dat_o (wb_mgmt_dat_o),
+    .wbm_ack_o (wb_mgmt_ack_o),
+    .wbm_err_o (wb_mgmt_err_o),
+    .wbm_rty_o (wb_mgmt_rty_o),
+    .wbs_adr_o ({wb_m2s_mgmt_cpu0_rom_adr, wb_m2s_mgmt_cpu0_ram_adr, wb_m2s_mgmt_led0_adr, wb_m2s_mgmt_uart0_adr, wb_m2s_mgmt_timer0_adr}),
+    .wbs_dat_o ({wb_m2s_mgmt_cpu0_rom_dat, wb_m2s_mgmt_cpu0_ram_dat, wb_m2s_mgmt_led0_dat, wb_m2s_mgmt_uart0_dat, wb_m2s_mgmt_timer0_dat}),
+    .wbs_sel_o ({wb_m2s_mgmt_cpu0_rom_sel, wb_m2s_mgmt_cpu0_ram_sel, wb_m2s_mgmt_led0_sel, wb_m2s_mgmt_uart0_sel, wb_m2s_mgmt_timer0_sel}),
+    .wbs_we_o  ({wb_m2s_mgmt_cpu0_rom_we, wb_m2s_mgmt_cpu0_ram_we, wb_m2s_mgmt_led0_we, wb_m2s_mgmt_uart0_we, wb_m2s_mgmt_timer0_we}),
+    .wbs_cyc_o ({wb_m2s_mgmt_cpu0_rom_cyc, wb_m2s_mgmt_cpu0_ram_cyc, wb_m2s_mgmt_led0_cyc, wb_m2s_mgmt_uart0_cyc, wb_m2s_mgmt_timer0_cyc}),
+    .wbs_stb_o ({wb_m2s_mgmt_cpu0_rom_stb, wb_m2s_mgmt_cpu0_ram_stb, wb_m2s_mgmt_led0_stb, wb_m2s_mgmt_uart0_stb, wb_m2s_mgmt_timer0_stb}),
+    .wbs_cti_o ({wb_m2s_mgmt_cpu0_rom_cti, wb_m2s_mgmt_cpu0_ram_cti, wb_m2s_mgmt_led0_cti, wb_m2s_mgmt_uart0_cti, wb_m2s_mgmt_timer0_cti}),
+    .wbs_bte_o ({wb_m2s_mgmt_cpu0_rom_bte, wb_m2s_mgmt_cpu0_ram_bte, wb_m2s_mgmt_led0_bte, wb_m2s_mgmt_uart0_bte, wb_m2s_mgmt_timer0_bte}),
+    .wbs_dat_i ({wb_s2m_mgmt_cpu0_rom_dat, wb_s2m_mgmt_cpu0_ram_dat, wb_s2m_mgmt_led0_dat, wb_s2m_mgmt_uart0_dat, wb_s2m_mgmt_timer0_dat}),
+    .wbs_ack_i ({wb_s2m_mgmt_cpu0_rom_ack, wb_s2m_mgmt_cpu0_ram_ack, wb_s2m_mgmt_led0_ack, wb_s2m_mgmt_uart0_ack, wb_s2m_mgmt_timer0_ack}),
+    .wbs_err_i ({wb_s2m_mgmt_cpu0_rom_err, wb_s2m_mgmt_cpu0_ram_err, wb_s2m_mgmt_led0_err, wb_s2m_mgmt_uart0_err, wb_s2m_mgmt_timer0_err}),
+    .wbs_rty_i ({wb_s2m_mgmt_cpu0_rom_rty, wb_s2m_mgmt_cpu0_ram_rty, wb_s2m_mgmt_led0_rty, wb_s2m_mgmt_uart0_rty, wb_s2m_mgmt_timer0_rty}));
 
 wb_mux
   #(.num_slaves (1),
     .MATCH_ADDR ({32'h30000000}),
     .MATCH_MASK ({32'hfffff800}))
  wb_mux_cpu0_ibus
-   (.wb_clk_i  (wb_clk_i),
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
     .wb_rst_i  (wb_rst_i),
     .wbm_adr_i (wb_cpu0_ibus_adr_i),
     .wbm_dat_i (wb_cpu0_ibus_dat_i),
@@ -267,10 +314,15 @@
 
 wb_mux
   #(.num_slaves (5),
-    .MATCH_ADDR ({32'h30000000, 32'h30003000, 32'h40000000, 32'h40001000, 32'h40002000}),
-    .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hfffff000, 32'hfffff000, 32'hfffff000}))
+    .MATCH_ADDR ({32'h30000000, 32'h30001000, 32'h30fffd00, 32'h30fffe00, 32'h30ffff00}),
+    .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hffffff00, 32'hffffff00, 32'hffffff00}))
  wb_mux_cpu0_dbus
-   (.wb_clk_i  (wb_clk_i),
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
     .wb_rst_i  (wb_rst_i),
     .wbm_adr_i (wb_cpu0_dbus_adr_i),
     .wbm_dat_i (wb_cpu0_dbus_dat_i),
@@ -284,68 +336,41 @@
     .wbm_ack_o (wb_cpu0_dbus_ack_o),
     .wbm_err_o (wb_cpu0_dbus_err_o),
     .wbm_rty_o (wb_cpu0_dbus_rty_o),
-    .wbs_adr_o ({wb_m2s_cpu0_dbus_cpu0_rom_adr, wb_m2s_cpu0_dbus_cpu0_ram_adr, wb_m2s_cpu0_dbus_timer0_adr, wb_m2s_cpu0_dbus_uart0_adr, wb_m2s_cpu0_dbus_led0_adr}),
-    .wbs_dat_o ({wb_m2s_cpu0_dbus_cpu0_rom_dat, wb_m2s_cpu0_dbus_cpu0_ram_dat, wb_m2s_cpu0_dbus_timer0_dat, wb_m2s_cpu0_dbus_uart0_dat, wb_m2s_cpu0_dbus_led0_dat}),
-    .wbs_sel_o ({wb_m2s_cpu0_dbus_cpu0_rom_sel, wb_m2s_cpu0_dbus_cpu0_ram_sel, wb_m2s_cpu0_dbus_timer0_sel, wb_m2s_cpu0_dbus_uart0_sel, wb_m2s_cpu0_dbus_led0_sel}),
-    .wbs_we_o  ({wb_m2s_cpu0_dbus_cpu0_rom_we, wb_m2s_cpu0_dbus_cpu0_ram_we, wb_m2s_cpu0_dbus_timer0_we, wb_m2s_cpu0_dbus_uart0_we, wb_m2s_cpu0_dbus_led0_we}),
-    .wbs_cyc_o ({wb_m2s_cpu0_dbus_cpu0_rom_cyc, wb_m2s_cpu0_dbus_cpu0_ram_cyc, wb_m2s_cpu0_dbus_timer0_cyc, wb_m2s_cpu0_dbus_uart0_cyc, wb_m2s_cpu0_dbus_led0_cyc}),
-    .wbs_stb_o ({wb_m2s_cpu0_dbus_cpu0_rom_stb, wb_m2s_cpu0_dbus_cpu0_ram_stb, wb_m2s_cpu0_dbus_timer0_stb, wb_m2s_cpu0_dbus_uart0_stb, wb_m2s_cpu0_dbus_led0_stb}),
-    .wbs_cti_o ({wb_m2s_cpu0_dbus_cpu0_rom_cti, wb_m2s_cpu0_dbus_cpu0_ram_cti, wb_m2s_cpu0_dbus_timer0_cti, wb_m2s_cpu0_dbus_uart0_cti, wb_m2s_cpu0_dbus_led0_cti}),
-    .wbs_bte_o ({wb_m2s_cpu0_dbus_cpu0_rom_bte, wb_m2s_cpu0_dbus_cpu0_ram_bte, wb_m2s_cpu0_dbus_timer0_bte, wb_m2s_cpu0_dbus_uart0_bte, wb_m2s_cpu0_dbus_led0_bte}),
-    .wbs_dat_i ({wb_s2m_cpu0_dbus_cpu0_rom_dat, wb_s2m_cpu0_dbus_cpu0_ram_dat, wb_s2m_cpu0_dbus_timer0_dat, wb_s2m_cpu0_dbus_uart0_dat, wb_s2m_cpu0_dbus_led0_dat}),
-    .wbs_ack_i ({wb_s2m_cpu0_dbus_cpu0_rom_ack, wb_s2m_cpu0_dbus_cpu0_ram_ack, wb_s2m_cpu0_dbus_timer0_ack, wb_s2m_cpu0_dbus_uart0_ack, wb_s2m_cpu0_dbus_led0_ack}),
-    .wbs_err_i ({wb_s2m_cpu0_dbus_cpu0_rom_err, wb_s2m_cpu0_dbus_cpu0_ram_err, wb_s2m_cpu0_dbus_timer0_err, wb_s2m_cpu0_dbus_uart0_err, wb_s2m_cpu0_dbus_led0_err}),
-    .wbs_rty_i ({wb_s2m_cpu0_dbus_cpu0_rom_rty, wb_s2m_cpu0_dbus_cpu0_ram_rty, wb_s2m_cpu0_dbus_timer0_rty, wb_s2m_cpu0_dbus_uart0_rty, wb_s2m_cpu0_dbus_led0_rty}));
-
-wb_mux
-  #(.num_slaves (5),
-    .MATCH_ADDR ({32'h30000000, 32'h30003000, 32'h40000000, 32'h40001000, 32'h40002000}),
-    .MATCH_MASK ({32'hfffff800, 32'hfffff800, 32'hfffff000, 32'hfffff000, 32'hfffff000}))
- wb_mux_mgmt
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i (wb_mgmt_adr_i),
-    .wbm_dat_i (wb_mgmt_dat_i),
-    .wbm_sel_i (wb_mgmt_sel_i),
-    .wbm_we_i  (wb_mgmt_we_i),
-    .wbm_cyc_i (wb_mgmt_cyc_i),
-    .wbm_stb_i (wb_mgmt_stb_i),
-    .wbm_cti_i (wb_mgmt_cti_i),
-    .wbm_bte_i (wb_mgmt_bte_i),
-    .wbm_dat_o (wb_mgmt_dat_o),
-    .wbm_ack_o (wb_mgmt_ack_o),
-    .wbm_err_o (wb_mgmt_err_o),
-    .wbm_rty_o (wb_mgmt_rty_o),
-    .wbs_adr_o ({wb_m2s_mgmt_cpu0_rom_adr, wb_m2s_mgmt_cpu0_ram_adr, wb_m2s_mgmt_timer0_adr, wb_m2s_mgmt_uart0_adr, wb_m2s_mgmt_led0_adr}),
-    .wbs_dat_o ({wb_m2s_mgmt_cpu0_rom_dat, wb_m2s_mgmt_cpu0_ram_dat, wb_m2s_mgmt_timer0_dat, wb_m2s_mgmt_uart0_dat, wb_m2s_mgmt_led0_dat}),
-    .wbs_sel_o ({wb_m2s_mgmt_cpu0_rom_sel, wb_m2s_mgmt_cpu0_ram_sel, wb_m2s_mgmt_timer0_sel, wb_m2s_mgmt_uart0_sel, wb_m2s_mgmt_led0_sel}),
-    .wbs_we_o  ({wb_m2s_mgmt_cpu0_rom_we, wb_m2s_mgmt_cpu0_ram_we, wb_m2s_mgmt_timer0_we, wb_m2s_mgmt_uart0_we, wb_m2s_mgmt_led0_we}),
-    .wbs_cyc_o ({wb_m2s_mgmt_cpu0_rom_cyc, wb_m2s_mgmt_cpu0_ram_cyc, wb_m2s_mgmt_timer0_cyc, wb_m2s_mgmt_uart0_cyc, wb_m2s_mgmt_led0_cyc}),
-    .wbs_stb_o ({wb_m2s_mgmt_cpu0_rom_stb, wb_m2s_mgmt_cpu0_ram_stb, wb_m2s_mgmt_timer0_stb, wb_m2s_mgmt_uart0_stb, wb_m2s_mgmt_led0_stb}),
-    .wbs_cti_o ({wb_m2s_mgmt_cpu0_rom_cti, wb_m2s_mgmt_cpu0_ram_cti, wb_m2s_mgmt_timer0_cti, wb_m2s_mgmt_uart0_cti, wb_m2s_mgmt_led0_cti}),
-    .wbs_bte_o ({wb_m2s_mgmt_cpu0_rom_bte, wb_m2s_mgmt_cpu0_ram_bte, wb_m2s_mgmt_timer0_bte, wb_m2s_mgmt_uart0_bte, wb_m2s_mgmt_led0_bte}),
-    .wbs_dat_i ({wb_s2m_mgmt_cpu0_rom_dat, wb_s2m_mgmt_cpu0_ram_dat, wb_s2m_mgmt_timer0_dat, wb_s2m_mgmt_uart0_dat, wb_s2m_mgmt_led0_dat}),
-    .wbs_ack_i ({wb_s2m_mgmt_cpu0_rom_ack, wb_s2m_mgmt_cpu0_ram_ack, wb_s2m_mgmt_timer0_ack, wb_s2m_mgmt_uart0_ack, wb_s2m_mgmt_led0_ack}),
-    .wbs_err_i ({wb_s2m_mgmt_cpu0_rom_err, wb_s2m_mgmt_cpu0_ram_err, wb_s2m_mgmt_timer0_err, wb_s2m_mgmt_uart0_err, wb_s2m_mgmt_led0_err}),
-    .wbs_rty_i ({wb_s2m_mgmt_cpu0_rom_rty, wb_s2m_mgmt_cpu0_ram_rty, wb_s2m_mgmt_timer0_rty, wb_s2m_mgmt_uart0_rty, wb_s2m_mgmt_led0_rty}));
+    .wbs_adr_o ({wb_m2s_cpu0_dbus_cpu0_rom_adr, wb_m2s_cpu0_dbus_cpu0_ram_adr, wb_m2s_cpu0_dbus_led0_adr, wb_m2s_cpu0_dbus_uart0_adr, wb_m2s_cpu0_dbus_timer0_adr}),
+    .wbs_dat_o ({wb_m2s_cpu0_dbus_cpu0_rom_dat, wb_m2s_cpu0_dbus_cpu0_ram_dat, wb_m2s_cpu0_dbus_led0_dat, wb_m2s_cpu0_dbus_uart0_dat, wb_m2s_cpu0_dbus_timer0_dat}),
+    .wbs_sel_o ({wb_m2s_cpu0_dbus_cpu0_rom_sel, wb_m2s_cpu0_dbus_cpu0_ram_sel, wb_m2s_cpu0_dbus_led0_sel, wb_m2s_cpu0_dbus_uart0_sel, wb_m2s_cpu0_dbus_timer0_sel}),
+    .wbs_we_o  ({wb_m2s_cpu0_dbus_cpu0_rom_we, wb_m2s_cpu0_dbus_cpu0_ram_we, wb_m2s_cpu0_dbus_led0_we, wb_m2s_cpu0_dbus_uart0_we, wb_m2s_cpu0_dbus_timer0_we}),
+    .wbs_cyc_o ({wb_m2s_cpu0_dbus_cpu0_rom_cyc, wb_m2s_cpu0_dbus_cpu0_ram_cyc, wb_m2s_cpu0_dbus_led0_cyc, wb_m2s_cpu0_dbus_uart0_cyc, wb_m2s_cpu0_dbus_timer0_cyc}),
+    .wbs_stb_o ({wb_m2s_cpu0_dbus_cpu0_rom_stb, wb_m2s_cpu0_dbus_cpu0_ram_stb, wb_m2s_cpu0_dbus_led0_stb, wb_m2s_cpu0_dbus_uart0_stb, wb_m2s_cpu0_dbus_timer0_stb}),
+    .wbs_cti_o ({wb_m2s_cpu0_dbus_cpu0_rom_cti, wb_m2s_cpu0_dbus_cpu0_ram_cti, wb_m2s_cpu0_dbus_led0_cti, wb_m2s_cpu0_dbus_uart0_cti, wb_m2s_cpu0_dbus_timer0_cti}),
+    .wbs_bte_o ({wb_m2s_cpu0_dbus_cpu0_rom_bte, wb_m2s_cpu0_dbus_cpu0_ram_bte, wb_m2s_cpu0_dbus_led0_bte, wb_m2s_cpu0_dbus_uart0_bte, wb_m2s_cpu0_dbus_timer0_bte}),
+    .wbs_dat_i ({wb_s2m_cpu0_dbus_cpu0_rom_dat, wb_s2m_cpu0_dbus_cpu0_ram_dat, wb_s2m_cpu0_dbus_led0_dat, wb_s2m_cpu0_dbus_uart0_dat, wb_s2m_cpu0_dbus_timer0_dat}),
+    .wbs_ack_i ({wb_s2m_cpu0_dbus_cpu0_rom_ack, wb_s2m_cpu0_dbus_cpu0_ram_ack, wb_s2m_cpu0_dbus_led0_ack, wb_s2m_cpu0_dbus_uart0_ack, wb_s2m_cpu0_dbus_timer0_ack}),
+    .wbs_err_i ({wb_s2m_cpu0_dbus_cpu0_rom_err, wb_s2m_cpu0_dbus_cpu0_ram_err, wb_s2m_cpu0_dbus_led0_err, wb_s2m_cpu0_dbus_uart0_err, wb_s2m_cpu0_dbus_timer0_err}),
+    .wbs_rty_i ({wb_s2m_cpu0_dbus_cpu0_rom_rty, wb_s2m_cpu0_dbus_cpu0_ram_rty, wb_s2m_cpu0_dbus_led0_rty, wb_s2m_cpu0_dbus_uart0_rty, wb_s2m_cpu0_dbus_timer0_rty}));
 
 wb_arbiter
   #(.num_masters (2))
  wb_arbiter_timer0
-   (.wb_clk_i  (wb_clk_i),
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
     .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_cpu0_dbus_timer0_adr, wb_m2s_mgmt_timer0_adr}),
-    .wbm_dat_i ({wb_m2s_cpu0_dbus_timer0_dat, wb_m2s_mgmt_timer0_dat}),
-    .wbm_sel_i ({wb_m2s_cpu0_dbus_timer0_sel, wb_m2s_mgmt_timer0_sel}),
-    .wbm_we_i  ({wb_m2s_cpu0_dbus_timer0_we, wb_m2s_mgmt_timer0_we}),
-    .wbm_cyc_i ({wb_m2s_cpu0_dbus_timer0_cyc, wb_m2s_mgmt_timer0_cyc}),
-    .wbm_stb_i ({wb_m2s_cpu0_dbus_timer0_stb, wb_m2s_mgmt_timer0_stb}),
-    .wbm_cti_i ({wb_m2s_cpu0_dbus_timer0_cti, wb_m2s_mgmt_timer0_cti}),
-    .wbm_bte_i ({wb_m2s_cpu0_dbus_timer0_bte, wb_m2s_mgmt_timer0_bte}),
-    .wbm_dat_o ({wb_s2m_cpu0_dbus_timer0_dat, wb_s2m_mgmt_timer0_dat}),
-    .wbm_ack_o ({wb_s2m_cpu0_dbus_timer0_ack, wb_s2m_mgmt_timer0_ack}),
-    .wbm_err_o ({wb_s2m_cpu0_dbus_timer0_err, wb_s2m_mgmt_timer0_err}),
-    .wbm_rty_o ({wb_s2m_cpu0_dbus_timer0_rty, wb_s2m_mgmt_timer0_rty}),
+    .wbm_adr_i ({wb_m2s_mgmt_timer0_adr, wb_m2s_cpu0_dbus_timer0_adr}),
+    .wbm_dat_i ({wb_m2s_mgmt_timer0_dat, wb_m2s_cpu0_dbus_timer0_dat}),
+    .wbm_sel_i ({wb_m2s_mgmt_timer0_sel, wb_m2s_cpu0_dbus_timer0_sel}),
+    .wbm_we_i  ({wb_m2s_mgmt_timer0_we, wb_m2s_cpu0_dbus_timer0_we}),
+    .wbm_cyc_i ({wb_m2s_mgmt_timer0_cyc, wb_m2s_cpu0_dbus_timer0_cyc}),
+    .wbm_stb_i ({wb_m2s_mgmt_timer0_stb, wb_m2s_cpu0_dbus_timer0_stb}),
+    .wbm_cti_i ({wb_m2s_mgmt_timer0_cti, wb_m2s_cpu0_dbus_timer0_cti}),
+    .wbm_bte_i ({wb_m2s_mgmt_timer0_bte, wb_m2s_cpu0_dbus_timer0_bte}),
+    .wbm_dat_o ({wb_s2m_mgmt_timer0_dat, wb_s2m_cpu0_dbus_timer0_dat}),
+    .wbm_ack_o ({wb_s2m_mgmt_timer0_ack, wb_s2m_cpu0_dbus_timer0_ack}),
+    .wbm_err_o ({wb_s2m_mgmt_timer0_err, wb_s2m_cpu0_dbus_timer0_err}),
+    .wbm_rty_o ({wb_s2m_mgmt_timer0_rty, wb_s2m_cpu0_dbus_timer0_rty}),
     .wbs_adr_o (wb_timer0_adr_o),
     .wbs_dat_o (wb_timer0_dat_o),
     .wbs_sel_o (wb_timer0_sel_o),
@@ -362,20 +387,25 @@
 wb_arbiter
   #(.num_masters (2))
  wb_arbiter_uart0
-   (.wb_clk_i  (wb_clk_i),
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
     .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_cpu0_dbus_uart0_adr, wb_m2s_mgmt_uart0_adr}),
-    .wbm_dat_i ({wb_m2s_cpu0_dbus_uart0_dat, wb_m2s_mgmt_uart0_dat}),
-    .wbm_sel_i ({wb_m2s_cpu0_dbus_uart0_sel, wb_m2s_mgmt_uart0_sel}),
-    .wbm_we_i  ({wb_m2s_cpu0_dbus_uart0_we, wb_m2s_mgmt_uart0_we}),
-    .wbm_cyc_i ({wb_m2s_cpu0_dbus_uart0_cyc, wb_m2s_mgmt_uart0_cyc}),
-    .wbm_stb_i ({wb_m2s_cpu0_dbus_uart0_stb, wb_m2s_mgmt_uart0_stb}),
-    .wbm_cti_i ({wb_m2s_cpu0_dbus_uart0_cti, wb_m2s_mgmt_uart0_cti}),
-    .wbm_bte_i ({wb_m2s_cpu0_dbus_uart0_bte, wb_m2s_mgmt_uart0_bte}),
-    .wbm_dat_o ({wb_s2m_cpu0_dbus_uart0_dat, wb_s2m_mgmt_uart0_dat}),
-    .wbm_ack_o ({wb_s2m_cpu0_dbus_uart0_ack, wb_s2m_mgmt_uart0_ack}),
-    .wbm_err_o ({wb_s2m_cpu0_dbus_uart0_err, wb_s2m_mgmt_uart0_err}),
-    .wbm_rty_o ({wb_s2m_cpu0_dbus_uart0_rty, wb_s2m_mgmt_uart0_rty}),
+    .wbm_adr_i ({wb_m2s_mgmt_uart0_adr, wb_m2s_cpu0_dbus_uart0_adr}),
+    .wbm_dat_i ({wb_m2s_mgmt_uart0_dat, wb_m2s_cpu0_dbus_uart0_dat}),
+    .wbm_sel_i ({wb_m2s_mgmt_uart0_sel, wb_m2s_cpu0_dbus_uart0_sel}),
+    .wbm_we_i  ({wb_m2s_mgmt_uart0_we, wb_m2s_cpu0_dbus_uart0_we}),
+    .wbm_cyc_i ({wb_m2s_mgmt_uart0_cyc, wb_m2s_cpu0_dbus_uart0_cyc}),
+    .wbm_stb_i ({wb_m2s_mgmt_uart0_stb, wb_m2s_cpu0_dbus_uart0_stb}),
+    .wbm_cti_i ({wb_m2s_mgmt_uart0_cti, wb_m2s_cpu0_dbus_uart0_cti}),
+    .wbm_bte_i ({wb_m2s_mgmt_uart0_bte, wb_m2s_cpu0_dbus_uart0_bte}),
+    .wbm_dat_o ({wb_s2m_mgmt_uart0_dat, wb_s2m_cpu0_dbus_uart0_dat}),
+    .wbm_ack_o ({wb_s2m_mgmt_uart0_ack, wb_s2m_cpu0_dbus_uart0_ack}),
+    .wbm_err_o ({wb_s2m_mgmt_uart0_err, wb_s2m_cpu0_dbus_uart0_err}),
+    .wbm_rty_o ({wb_s2m_mgmt_uart0_rty, wb_s2m_cpu0_dbus_uart0_rty}),
     .wbs_adr_o (wb_uart0_adr_o),
     .wbs_dat_o (wb_uart0_dat_o),
     .wbs_sel_o (wb_uart0_sel_o),
@@ -392,20 +422,25 @@
 wb_arbiter
   #(.num_masters (2))
  wb_arbiter_led0
-   (.wb_clk_i  (wb_clk_i),
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
     .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_cpu0_dbus_led0_adr, wb_m2s_mgmt_led0_adr}),
-    .wbm_dat_i ({wb_m2s_cpu0_dbus_led0_dat, wb_m2s_mgmt_led0_dat}),
-    .wbm_sel_i ({wb_m2s_cpu0_dbus_led0_sel, wb_m2s_mgmt_led0_sel}),
-    .wbm_we_i  ({wb_m2s_cpu0_dbus_led0_we, wb_m2s_mgmt_led0_we}),
-    .wbm_cyc_i ({wb_m2s_cpu0_dbus_led0_cyc, wb_m2s_mgmt_led0_cyc}),
-    .wbm_stb_i ({wb_m2s_cpu0_dbus_led0_stb, wb_m2s_mgmt_led0_stb}),
-    .wbm_cti_i ({wb_m2s_cpu0_dbus_led0_cti, wb_m2s_mgmt_led0_cti}),
-    .wbm_bte_i ({wb_m2s_cpu0_dbus_led0_bte, wb_m2s_mgmt_led0_bte}),
-    .wbm_dat_o ({wb_s2m_cpu0_dbus_led0_dat, wb_s2m_mgmt_led0_dat}),
-    .wbm_ack_o ({wb_s2m_cpu0_dbus_led0_ack, wb_s2m_mgmt_led0_ack}),
-    .wbm_err_o ({wb_s2m_cpu0_dbus_led0_err, wb_s2m_mgmt_led0_err}),
-    .wbm_rty_o ({wb_s2m_cpu0_dbus_led0_rty, wb_s2m_mgmt_led0_rty}),
+    .wbm_adr_i ({wb_m2s_mgmt_led0_adr, wb_m2s_cpu0_dbus_led0_adr}),
+    .wbm_dat_i ({wb_m2s_mgmt_led0_dat, wb_m2s_cpu0_dbus_led0_dat}),
+    .wbm_sel_i ({wb_m2s_mgmt_led0_sel, wb_m2s_cpu0_dbus_led0_sel}),
+    .wbm_we_i  ({wb_m2s_mgmt_led0_we, wb_m2s_cpu0_dbus_led0_we}),
+    .wbm_cyc_i ({wb_m2s_mgmt_led0_cyc, wb_m2s_cpu0_dbus_led0_cyc}),
+    .wbm_stb_i ({wb_m2s_mgmt_led0_stb, wb_m2s_cpu0_dbus_led0_stb}),
+    .wbm_cti_i ({wb_m2s_mgmt_led0_cti, wb_m2s_cpu0_dbus_led0_cti}),
+    .wbm_bte_i ({wb_m2s_mgmt_led0_bte, wb_m2s_cpu0_dbus_led0_bte}),
+    .wbm_dat_o ({wb_s2m_mgmt_led0_dat, wb_s2m_cpu0_dbus_led0_dat}),
+    .wbm_ack_o ({wb_s2m_mgmt_led0_ack, wb_s2m_cpu0_dbus_led0_ack}),
+    .wbm_err_o ({wb_s2m_mgmt_led0_err, wb_s2m_cpu0_dbus_led0_err}),
+    .wbm_rty_o ({wb_s2m_mgmt_led0_rty, wb_s2m_cpu0_dbus_led0_rty}),
     .wbs_adr_o (wb_led0_adr_o),
     .wbs_dat_o (wb_led0_dat_o),
     .wbs_sel_o (wb_led0_sel_o),
@@ -420,52 +455,27 @@
     .wbs_rty_i (wb_led0_rty_i));
 
 wb_arbiter
-  #(.num_masters (3))
- wb_arbiter_cpu0_rom
-   (.wb_clk_i  (wb_clk_i),
-    .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_cpu0_ibus_cpu0_rom_adr, wb_m2s_cpu0_dbus_cpu0_rom_adr, wb_m2s_mgmt_cpu0_rom_adr}),
-    .wbm_dat_i ({wb_m2s_cpu0_ibus_cpu0_rom_dat, wb_m2s_cpu0_dbus_cpu0_rom_dat, wb_m2s_mgmt_cpu0_rom_dat}),
-    .wbm_sel_i ({wb_m2s_cpu0_ibus_cpu0_rom_sel, wb_m2s_cpu0_dbus_cpu0_rom_sel, wb_m2s_mgmt_cpu0_rom_sel}),
-    .wbm_we_i  ({wb_m2s_cpu0_ibus_cpu0_rom_we, wb_m2s_cpu0_dbus_cpu0_rom_we, wb_m2s_mgmt_cpu0_rom_we}),
-    .wbm_cyc_i ({wb_m2s_cpu0_ibus_cpu0_rom_cyc, wb_m2s_cpu0_dbus_cpu0_rom_cyc, wb_m2s_mgmt_cpu0_rom_cyc}),
-    .wbm_stb_i ({wb_m2s_cpu0_ibus_cpu0_rom_stb, wb_m2s_cpu0_dbus_cpu0_rom_stb, wb_m2s_mgmt_cpu0_rom_stb}),
-    .wbm_cti_i ({wb_m2s_cpu0_ibus_cpu0_rom_cti, wb_m2s_cpu0_dbus_cpu0_rom_cti, wb_m2s_mgmt_cpu0_rom_cti}),
-    .wbm_bte_i ({wb_m2s_cpu0_ibus_cpu0_rom_bte, wb_m2s_cpu0_dbus_cpu0_rom_bte, wb_m2s_mgmt_cpu0_rom_bte}),
-    .wbm_dat_o ({wb_s2m_cpu0_ibus_cpu0_rom_dat, wb_s2m_cpu0_dbus_cpu0_rom_dat, wb_s2m_mgmt_cpu0_rom_dat}),
-    .wbm_ack_o ({wb_s2m_cpu0_ibus_cpu0_rom_ack, wb_s2m_cpu0_dbus_cpu0_rom_ack, wb_s2m_mgmt_cpu0_rom_ack}),
-    .wbm_err_o ({wb_s2m_cpu0_ibus_cpu0_rom_err, wb_s2m_cpu0_dbus_cpu0_rom_err, wb_s2m_mgmt_cpu0_rom_err}),
-    .wbm_rty_o ({wb_s2m_cpu0_ibus_cpu0_rom_rty, wb_s2m_cpu0_dbus_cpu0_rom_rty, wb_s2m_mgmt_cpu0_rom_rty}),
-    .wbs_adr_o (wb_cpu0_rom_adr_o),
-    .wbs_dat_o (wb_cpu0_rom_dat_o),
-    .wbs_sel_o (wb_cpu0_rom_sel_o),
-    .wbs_we_o  (wb_cpu0_rom_we_o),
-    .wbs_cyc_o (wb_cpu0_rom_cyc_o),
-    .wbs_stb_o (wb_cpu0_rom_stb_o),
-    .wbs_cti_o (wb_cpu0_rom_cti_o),
-    .wbs_bte_o (wb_cpu0_rom_bte_o),
-    .wbs_dat_i (wb_cpu0_rom_dat_i),
-    .wbs_ack_i (wb_cpu0_rom_ack_i),
-    .wbs_err_i (wb_cpu0_rom_err_i),
-    .wbs_rty_i (wb_cpu0_rom_rty_i));
-
-wb_arbiter
   #(.num_masters (2))
  wb_arbiter_cpu0_ram
-   (.wb_clk_i  (wb_clk_i),
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
     .wb_rst_i  (wb_rst_i),
-    .wbm_adr_i ({wb_m2s_cpu0_dbus_cpu0_ram_adr, wb_m2s_mgmt_cpu0_ram_adr}),
-    .wbm_dat_i ({wb_m2s_cpu0_dbus_cpu0_ram_dat, wb_m2s_mgmt_cpu0_ram_dat}),
-    .wbm_sel_i ({wb_m2s_cpu0_dbus_cpu0_ram_sel, wb_m2s_mgmt_cpu0_ram_sel}),
-    .wbm_we_i  ({wb_m2s_cpu0_dbus_cpu0_ram_we, wb_m2s_mgmt_cpu0_ram_we}),
-    .wbm_cyc_i ({wb_m2s_cpu0_dbus_cpu0_ram_cyc, wb_m2s_mgmt_cpu0_ram_cyc}),
-    .wbm_stb_i ({wb_m2s_cpu0_dbus_cpu0_ram_stb, wb_m2s_mgmt_cpu0_ram_stb}),
-    .wbm_cti_i ({wb_m2s_cpu0_dbus_cpu0_ram_cti, wb_m2s_mgmt_cpu0_ram_cti}),
-    .wbm_bte_i ({wb_m2s_cpu0_dbus_cpu0_ram_bte, wb_m2s_mgmt_cpu0_ram_bte}),
-    .wbm_dat_o ({wb_s2m_cpu0_dbus_cpu0_ram_dat, wb_s2m_mgmt_cpu0_ram_dat}),
-    .wbm_ack_o ({wb_s2m_cpu0_dbus_cpu0_ram_ack, wb_s2m_mgmt_cpu0_ram_ack}),
-    .wbm_err_o ({wb_s2m_cpu0_dbus_cpu0_ram_err, wb_s2m_mgmt_cpu0_ram_err}),
-    .wbm_rty_o ({wb_s2m_cpu0_dbus_cpu0_ram_rty, wb_s2m_mgmt_cpu0_ram_rty}),
+    .wbm_adr_i ({wb_m2s_mgmt_cpu0_ram_adr, wb_m2s_cpu0_dbus_cpu0_ram_adr}),
+    .wbm_dat_i ({wb_m2s_mgmt_cpu0_ram_dat, wb_m2s_cpu0_dbus_cpu0_ram_dat}),
+    .wbm_sel_i ({wb_m2s_mgmt_cpu0_ram_sel, wb_m2s_cpu0_dbus_cpu0_ram_sel}),
+    .wbm_we_i  ({wb_m2s_mgmt_cpu0_ram_we, wb_m2s_cpu0_dbus_cpu0_ram_we}),
+    .wbm_cyc_i ({wb_m2s_mgmt_cpu0_ram_cyc, wb_m2s_cpu0_dbus_cpu0_ram_cyc}),
+    .wbm_stb_i ({wb_m2s_mgmt_cpu0_ram_stb, wb_m2s_cpu0_dbus_cpu0_ram_stb}),
+    .wbm_cti_i ({wb_m2s_mgmt_cpu0_ram_cti, wb_m2s_cpu0_dbus_cpu0_ram_cti}),
+    .wbm_bte_i ({wb_m2s_mgmt_cpu0_ram_bte, wb_m2s_cpu0_dbus_cpu0_ram_bte}),
+    .wbm_dat_o ({wb_s2m_mgmt_cpu0_ram_dat, wb_s2m_cpu0_dbus_cpu0_ram_dat}),
+    .wbm_ack_o ({wb_s2m_mgmt_cpu0_ram_ack, wb_s2m_cpu0_dbus_cpu0_ram_ack}),
+    .wbm_err_o ({wb_s2m_mgmt_cpu0_ram_err, wb_s2m_cpu0_dbus_cpu0_ram_err}),
+    .wbm_rty_o ({wb_s2m_mgmt_cpu0_ram_rty, wb_s2m_cpu0_dbus_cpu0_ram_rty}),
     .wbs_adr_o (wb_cpu0_ram_adr_o),
     .wbs_dat_o (wb_cpu0_ram_dat_o),
     .wbs_sel_o (wb_cpu0_ram_sel_o),
@@ -479,4 +489,39 @@
     .wbs_err_i (wb_cpu0_ram_err_i),
     .wbs_rty_i (wb_cpu0_ram_rty_i));
 
+wb_arbiter
+  #(.num_masters (3))
+ wb_arbiter_cpu0_rom
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i  (wb_clk_i),
+    .wb_rst_i  (wb_rst_i),
+    .wbm_adr_i ({wb_m2s_mgmt_cpu0_rom_adr, wb_m2s_cpu0_ibus_cpu0_rom_adr, wb_m2s_cpu0_dbus_cpu0_rom_adr}),
+    .wbm_dat_i ({wb_m2s_mgmt_cpu0_rom_dat, wb_m2s_cpu0_ibus_cpu0_rom_dat, wb_m2s_cpu0_dbus_cpu0_rom_dat}),
+    .wbm_sel_i ({wb_m2s_mgmt_cpu0_rom_sel, wb_m2s_cpu0_ibus_cpu0_rom_sel, wb_m2s_cpu0_dbus_cpu0_rom_sel}),
+    .wbm_we_i  ({wb_m2s_mgmt_cpu0_rom_we, wb_m2s_cpu0_ibus_cpu0_rom_we, wb_m2s_cpu0_dbus_cpu0_rom_we}),
+    .wbm_cyc_i ({wb_m2s_mgmt_cpu0_rom_cyc, wb_m2s_cpu0_ibus_cpu0_rom_cyc, wb_m2s_cpu0_dbus_cpu0_rom_cyc}),
+    .wbm_stb_i ({wb_m2s_mgmt_cpu0_rom_stb, wb_m2s_cpu0_ibus_cpu0_rom_stb, wb_m2s_cpu0_dbus_cpu0_rom_stb}),
+    .wbm_cti_i ({wb_m2s_mgmt_cpu0_rom_cti, wb_m2s_cpu0_ibus_cpu0_rom_cti, wb_m2s_cpu0_dbus_cpu0_rom_cti}),
+    .wbm_bte_i ({wb_m2s_mgmt_cpu0_rom_bte, wb_m2s_cpu0_ibus_cpu0_rom_bte, wb_m2s_cpu0_dbus_cpu0_rom_bte}),
+    .wbm_dat_o ({wb_s2m_mgmt_cpu0_rom_dat, wb_s2m_cpu0_ibus_cpu0_rom_dat, wb_s2m_cpu0_dbus_cpu0_rom_dat}),
+    .wbm_ack_o ({wb_s2m_mgmt_cpu0_rom_ack, wb_s2m_cpu0_ibus_cpu0_rom_ack, wb_s2m_cpu0_dbus_cpu0_rom_ack}),
+    .wbm_err_o ({wb_s2m_mgmt_cpu0_rom_err, wb_s2m_cpu0_ibus_cpu0_rom_err, wb_s2m_cpu0_dbus_cpu0_rom_err}),
+    .wbm_rty_o ({wb_s2m_mgmt_cpu0_rom_rty, wb_s2m_cpu0_ibus_cpu0_rom_rty, wb_s2m_cpu0_dbus_cpu0_rom_rty}),
+    .wbs_adr_o (wb_cpu0_rom_adr_o),
+    .wbs_dat_o (wb_cpu0_rom_dat_o),
+    .wbs_sel_o (wb_cpu0_rom_sel_o),
+    .wbs_we_o  (wb_cpu0_rom_we_o),
+    .wbs_cyc_o (wb_cpu0_rom_cyc_o),
+    .wbs_stb_o (wb_cpu0_rom_stb_o),
+    .wbs_cti_o (wb_cpu0_rom_cti_o),
+    .wbs_bte_o (wb_cpu0_rom_bte_o),
+    .wbs_dat_i (wb_cpu0_rom_dat_i),
+    .wbs_ack_i (wb_cpu0_rom_ack_i),
+    .wbs_err_i (wb_cpu0_rom_err_i),
+    .wbs_rty_i (wb_cpu0_rom_rty_i));
+
 endmodule
diff --git a/openlane/user_proj/src/wb_interconnect.vh b/openlane/user_proj/src/wb_interconnect.vh
new file mode 100644
index 0000000..43e5d85
--- /dev/null
+++ b/openlane/user_proj/src/wb_interconnect.vh
@@ -0,0 +1,204 @@
+// THIS FILE IS AUTOGENERATED BY wb_interconA_gen
+// ANY MANUAL CHANGES WILL BE LOST
+wire [31:0] wb_m2s_mgmt_adr;
+wire [31:0] wb_m2s_mgmt_dat;
+wire  [3:0] wb_m2s_mgmt_sel;
+wire        wb_m2s_mgmt_we;
+wire        wb_m2s_mgmt_cyc;
+wire        wb_m2s_mgmt_stb;
+wire  [2:0] wb_m2s_mgmt_cti;
+wire  [1:0] wb_m2s_mgmt_bte;
+wire [31:0] wb_s2m_mgmt_dat;
+wire        wb_s2m_mgmt_ack;
+wire        wb_s2m_mgmt_err;
+wire        wb_s2m_mgmt_rty;
+wire [31:0] wb_m2s_cpu0_ibus_adr;
+wire [31:0] wb_m2s_cpu0_ibus_dat;
+wire  [3:0] wb_m2s_cpu0_ibus_sel;
+wire        wb_m2s_cpu0_ibus_we;
+wire        wb_m2s_cpu0_ibus_cyc;
+wire        wb_m2s_cpu0_ibus_stb;
+wire  [2:0] wb_m2s_cpu0_ibus_cti;
+wire  [1:0] wb_m2s_cpu0_ibus_bte;
+wire [31:0] wb_s2m_cpu0_ibus_dat;
+wire        wb_s2m_cpu0_ibus_ack;
+wire        wb_s2m_cpu0_ibus_err;
+wire        wb_s2m_cpu0_ibus_rty;
+wire [31:0] wb_m2s_cpu0_dbus_adr;
+wire [31:0] wb_m2s_cpu0_dbus_dat;
+wire  [3:0] wb_m2s_cpu0_dbus_sel;
+wire        wb_m2s_cpu0_dbus_we;
+wire        wb_m2s_cpu0_dbus_cyc;
+wire        wb_m2s_cpu0_dbus_stb;
+wire  [2:0] wb_m2s_cpu0_dbus_cti;
+wire  [1:0] wb_m2s_cpu0_dbus_bte;
+wire [31:0] wb_s2m_cpu0_dbus_dat;
+wire        wb_s2m_cpu0_dbus_ack;
+wire        wb_s2m_cpu0_dbus_err;
+wire        wb_s2m_cpu0_dbus_rty;
+wire [31:0] wb_m2s_timer0_adr;
+wire [31:0] wb_m2s_timer0_dat;
+wire  [3:0] wb_m2s_timer0_sel;
+wire        wb_m2s_timer0_we;
+wire        wb_m2s_timer0_cyc;
+wire        wb_m2s_timer0_stb;
+wire  [2:0] wb_m2s_timer0_cti;
+wire  [1:0] wb_m2s_timer0_bte;
+wire [31:0] wb_s2m_timer0_dat;
+wire        wb_s2m_timer0_ack;
+wire        wb_s2m_timer0_err;
+wire        wb_s2m_timer0_rty;
+wire [31:0] wb_m2s_uart0_adr;
+wire [31:0] wb_m2s_uart0_dat;
+wire  [3:0] wb_m2s_uart0_sel;
+wire        wb_m2s_uart0_we;
+wire        wb_m2s_uart0_cyc;
+wire        wb_m2s_uart0_stb;
+wire  [2:0] wb_m2s_uart0_cti;
+wire  [1:0] wb_m2s_uart0_bte;
+wire [31:0] wb_s2m_uart0_dat;
+wire        wb_s2m_uart0_ack;
+wire        wb_s2m_uart0_err;
+wire        wb_s2m_uart0_rty;
+wire [31:0] wb_m2s_led0_adr;
+wire [31:0] wb_m2s_led0_dat;
+wire  [3:0] wb_m2s_led0_sel;
+wire        wb_m2s_led0_we;
+wire        wb_m2s_led0_cyc;
+wire        wb_m2s_led0_stb;
+wire  [2:0] wb_m2s_led0_cti;
+wire  [1:0] wb_m2s_led0_bte;
+wire [31:0] wb_s2m_led0_dat;
+wire        wb_s2m_led0_ack;
+wire        wb_s2m_led0_err;
+wire        wb_s2m_led0_rty;
+wire [31:0] wb_m2s_cpu0_ram_adr;
+wire [31:0] wb_m2s_cpu0_ram_dat;
+wire  [3:0] wb_m2s_cpu0_ram_sel;
+wire        wb_m2s_cpu0_ram_we;
+wire        wb_m2s_cpu0_ram_cyc;
+wire        wb_m2s_cpu0_ram_stb;
+wire  [2:0] wb_m2s_cpu0_ram_cti;
+wire  [1:0] wb_m2s_cpu0_ram_bte;
+wire [31:0] wb_s2m_cpu0_ram_dat;
+wire        wb_s2m_cpu0_ram_ack;
+wire        wb_s2m_cpu0_ram_err;
+wire        wb_s2m_cpu0_ram_rty;
+wire [31:0] wb_m2s_cpu0_rom_adr;
+wire [31:0] wb_m2s_cpu0_rom_dat;
+wire  [3:0] wb_m2s_cpu0_rom_sel;
+wire        wb_m2s_cpu0_rom_we;
+wire        wb_m2s_cpu0_rom_cyc;
+wire        wb_m2s_cpu0_rom_stb;
+wire  [2:0] wb_m2s_cpu0_rom_cti;
+wire  [1:0] wb_m2s_cpu0_rom_bte;
+wire [31:0] wb_s2m_cpu0_rom_dat;
+wire        wb_s2m_cpu0_rom_ack;
+wire        wb_s2m_cpu0_rom_err;
+wire        wb_s2m_cpu0_rom_rty;
+
+wb_interconA wb_interconA0
+   (
+`ifdef USE_POWER_PINS
+  .vccd1(vccd1),	// User area 1 1.8V power
+  .vssd1(vssd1),	// User area 1 digital ground
+`endif
+    .wb_clk_i           (wb_clk),
+    .wb_rst_i           (wb_rst),
+    .wb_mgmt_adr_i      (wb_m2s_mgmt_adr),
+    .wb_mgmt_dat_i      (wb_m2s_mgmt_dat),
+    .wb_mgmt_sel_i      (wb_m2s_mgmt_sel),
+    .wb_mgmt_we_i       (wb_m2s_mgmt_we),
+    .wb_mgmt_cyc_i      (wb_m2s_mgmt_cyc),
+    .wb_mgmt_stb_i      (wb_m2s_mgmt_stb),
+    .wb_mgmt_cti_i      (wb_m2s_mgmt_cti),
+    .wb_mgmt_bte_i      (wb_m2s_mgmt_bte),
+    .wb_mgmt_dat_o      (wb_s2m_mgmt_dat),
+    .wb_mgmt_ack_o      (wb_s2m_mgmt_ack),
+    .wb_mgmt_err_o      (wb_s2m_mgmt_err),
+    .wb_mgmt_rty_o      (wb_s2m_mgmt_rty),
+    .wb_cpu0_ibus_adr_i (wb_m2s_cpu0_ibus_adr),
+    .wb_cpu0_ibus_dat_i (wb_m2s_cpu0_ibus_dat),
+    .wb_cpu0_ibus_sel_i (wb_m2s_cpu0_ibus_sel),
+    .wb_cpu0_ibus_we_i  (wb_m2s_cpu0_ibus_we),
+    .wb_cpu0_ibus_cyc_i (wb_m2s_cpu0_ibus_cyc),
+    .wb_cpu0_ibus_stb_i (wb_m2s_cpu0_ibus_stb),
+    .wb_cpu0_ibus_cti_i (wb_m2s_cpu0_ibus_cti),
+    .wb_cpu0_ibus_bte_i (wb_m2s_cpu0_ibus_bte),
+    .wb_cpu0_ibus_dat_o (wb_s2m_cpu0_ibus_dat),
+    .wb_cpu0_ibus_ack_o (wb_s2m_cpu0_ibus_ack),
+    .wb_cpu0_ibus_err_o (wb_s2m_cpu0_ibus_err),
+    .wb_cpu0_ibus_rty_o (wb_s2m_cpu0_ibus_rty),
+    .wb_cpu0_dbus_adr_i (wb_m2s_cpu0_dbus_adr),
+    .wb_cpu0_dbus_dat_i (wb_m2s_cpu0_dbus_dat),
+    .wb_cpu0_dbus_sel_i (wb_m2s_cpu0_dbus_sel),
+    .wb_cpu0_dbus_we_i  (wb_m2s_cpu0_dbus_we),
+    .wb_cpu0_dbus_cyc_i (wb_m2s_cpu0_dbus_cyc),
+    .wb_cpu0_dbus_stb_i (wb_m2s_cpu0_dbus_stb),
+    .wb_cpu0_dbus_cti_i (wb_m2s_cpu0_dbus_cti),
+    .wb_cpu0_dbus_bte_i (wb_m2s_cpu0_dbus_bte),
+    .wb_cpu0_dbus_dat_o (wb_s2m_cpu0_dbus_dat),
+    .wb_cpu0_dbus_ack_o (wb_s2m_cpu0_dbus_ack),
+    .wb_cpu0_dbus_err_o (wb_s2m_cpu0_dbus_err),
+    .wb_cpu0_dbus_rty_o (wb_s2m_cpu0_dbus_rty),
+    .wb_timer0_adr_o    (wb_m2s_timer0_adr),
+    .wb_timer0_dat_o    (wb_m2s_timer0_dat),
+    .wb_timer0_sel_o    (wb_m2s_timer0_sel),
+    .wb_timer0_we_o     (wb_m2s_timer0_we),
+    .wb_timer0_cyc_o    (wb_m2s_timer0_cyc),
+    .wb_timer0_stb_o    (wb_m2s_timer0_stb),
+    .wb_timer0_cti_o    (wb_m2s_timer0_cti),
+    .wb_timer0_bte_o    (wb_m2s_timer0_bte),
+    .wb_timer0_dat_i    (wb_s2m_timer0_dat),
+    .wb_timer0_ack_i    (wb_s2m_timer0_ack),
+    .wb_timer0_err_i    (wb_s2m_timer0_err),
+    .wb_timer0_rty_i    (wb_s2m_timer0_rty),
+    .wb_uart0_adr_o     (wb_m2s_uart0_adr),
+    .wb_uart0_dat_o     (wb_m2s_uart0_dat),
+    .wb_uart0_sel_o     (wb_m2s_uart0_sel),
+    .wb_uart0_we_o      (wb_m2s_uart0_we),
+    .wb_uart0_cyc_o     (wb_m2s_uart0_cyc),
+    .wb_uart0_stb_o     (wb_m2s_uart0_stb),
+    .wb_uart0_cti_o     (wb_m2s_uart0_cti),
+    .wb_uart0_bte_o     (wb_m2s_uart0_bte),
+    .wb_uart0_dat_i     (wb_s2m_uart0_dat),
+    .wb_uart0_ack_i     (wb_s2m_uart0_ack),
+    .wb_uart0_err_i     (wb_s2m_uart0_err),
+    .wb_uart0_rty_i     (wb_s2m_uart0_rty),
+    .wb_led0_adr_o      (wb_m2s_led0_adr),
+    .wb_led0_dat_o      (wb_m2s_led0_dat),
+    .wb_led0_sel_o      (wb_m2s_led0_sel),
+    .wb_led0_we_o       (wb_m2s_led0_we),
+    .wb_led0_cyc_o      (wb_m2s_led0_cyc),
+    .wb_led0_stb_o      (wb_m2s_led0_stb),
+    .wb_led0_cti_o      (wb_m2s_led0_cti),
+    .wb_led0_bte_o      (wb_m2s_led0_bte),
+    .wb_led0_dat_i      (wb_s2m_led0_dat),
+    .wb_led0_ack_i      (wb_s2m_led0_ack),
+    .wb_led0_err_i      (wb_s2m_led0_err),
+    .wb_led0_rty_i      (wb_s2m_led0_rty),
+    .wb_cpu0_ram_adr_o  (wb_m2s_cpu0_ram_adr),
+    .wb_cpu0_ram_dat_o  (wb_m2s_cpu0_ram_dat),
+    .wb_cpu0_ram_sel_o  (wb_m2s_cpu0_ram_sel),
+    .wb_cpu0_ram_we_o   (wb_m2s_cpu0_ram_we),
+    .wb_cpu0_ram_cyc_o  (wb_m2s_cpu0_ram_cyc),
+    .wb_cpu0_ram_stb_o  (wb_m2s_cpu0_ram_stb),
+    .wb_cpu0_ram_cti_o  (wb_m2s_cpu0_ram_cti),
+    .wb_cpu0_ram_bte_o  (wb_m2s_cpu0_ram_bte),
+    .wb_cpu0_ram_dat_i  (wb_s2m_cpu0_ram_dat),
+    .wb_cpu0_ram_ack_i  (wb_s2m_cpu0_ram_ack),
+    .wb_cpu0_ram_err_i  (wb_s2m_cpu0_ram_err),
+    .wb_cpu0_ram_rty_i  (wb_s2m_cpu0_ram_rty),
+    .wb_cpu0_rom_adr_o  (wb_m2s_cpu0_rom_adr),
+    .wb_cpu0_rom_dat_o  (wb_m2s_cpu0_rom_dat),
+    .wb_cpu0_rom_sel_o  (wb_m2s_cpu0_rom_sel),
+    .wb_cpu0_rom_we_o   (wb_m2s_cpu0_rom_we),
+    .wb_cpu0_rom_cyc_o  (wb_m2s_cpu0_rom_cyc),
+    .wb_cpu0_rom_stb_o  (wb_m2s_cpu0_rom_stb),
+    .wb_cpu0_rom_cti_o  (wb_m2s_cpu0_rom_cti),
+    .wb_cpu0_rom_bte_o  (wb_m2s_cpu0_rom_bte),
+    .wb_cpu0_rom_dat_i  (wb_s2m_cpu0_rom_dat),
+    .wb_cpu0_rom_ack_i  (wb_s2m_cpu0_rom_ack),
+    .wb_cpu0_rom_err_i  (wb_s2m_cpu0_rom_err),
+    .wb_cpu0_rom_rty_i  (wb_s2m_cpu0_rom_rty));
+
diff --git a/openlane/user_proj/src/wb_led.v b/openlane/user_proj/src/wb_led.v
index cc0a93f..5755d18 100644
--- a/openlane/user_proj/src/wb_led.v
+++ b/openlane/user_proj/src/wb_led.v
@@ -24,16 +24,14 @@
 // Wishbone register addresses
 localparam
     wb_r_DATA  = 1'b0,
-    wb_r_SHIFT = 1'b1,
     wb_r_MAX   = 1'b1;
 
 // register
 reg [31:0] data;
-reg [5:0] shift;
 
 // output generation
 always @(posedge i_clk) begin
-    o_led <= data[shift];
+    o_led <= data[0];
 end
 
 // Since the incoming wishbone address from the CPU increments by 4 bytes, we
@@ -45,7 +43,6 @@
     if (i_reset) begin
         o_wb_ack <= 0;
         data <= 0;
-        shift <= 0;
     end else begin
         // Wishbone interface logic
         o_wb_ack <= 1'b0;
@@ -55,14 +52,12 @@
             // Register read
             case (register_index)
                 wb_r_DATA: o_wb_dat <= data;
-                wb_r_SHIFT:o_wb_dat <= shift;
             endcase
 
             // Register write
             if (i_wb_we) begin
                 case (register_index)
                     wb_r_DATA: data <= i_wb_dat;
-                    wb_r_SHIFT: shift <= i_wb_dat;
                 endcase
             end
         end
diff --git a/openlane/user_proj/src/wb_openram_wrapper.v b/openlane/user_proj/src/wb_openram_wrapper.v
index a39c814..3b40509 100644
--- a/openlane/user_proj/src/wb_openram_wrapper.v
+++ b/openlane/user_proj/src/wb_openram_wrapper.v
@@ -15,74 +15,124 @@
 
 `default_nettype none
 
-module wb_openram_wrapper 
+module wb_openram_wrapper1
 #(
-    parameter BASE_ADDR = 32'h30c0_0000,
-    parameter ADDR_WIDTH = 8
+    parameter BASE_ADDR = 32'h3000_0000,
+    parameter ADDR_WIDTH = 9
 )
 (
 `ifdef USE_POWER_PINS
     inout vccd1,	// User area 1 1.8V supply
     inout vssd1,	// User area 1 digital ground
 `endif
+    input             wb_clk_i,
+    input             wb_rst_i,
+    input             wbs_stb_i,
+    input             wbs_cyc_i,
+    input             wbs_we_i,
+    input   [3:0]     wbs_sel_i,
+    input   [31:0]    wbs_dat_i,
+    input   [31:0]    wbs_adr_i,
+    output reg        wbs_ack_o,
+    output reg [31:0] wbs_dat_o,
 
-    // Wishbone port A
-    input           wb_clk_i,
-    input           wb_rst_i,
-    input           wbs_stb_i,
-    input           wbs_cyc_i,
-    input           wbs_we_i,
-    input   [3:0]   wbs_sel_i,
-    input   [31:0]  wbs_dat_i,
-    input   [31:0]  wbs_adr_i,
-    output          wbs_ack_o,
-    output  [31:0]  wbs_dat_o,
-
-    // OpenRAM interface - almost dual port: RW + R
-    // Port 0: RW
-    output                      ram_clk0,       // clock
-    output                      ram_csb0,       // active low chip select
-    output                      ram_web0,       // active low write control
-    output  [3:0]              	ram_wmask0,     // write (byte) mask
+    // OpenRAM interface - RW
+    output                      ram_csb0,
+    output                      ram_web0,
+    output  [3:0]              	ram_wmask0,
     output  [ADDR_WIDTH-1:0]    ram_addr0,
-    input   [31:0]              ram_din0,
-    output  [31:0]              ram_dout0,
-
-    // Port 1: R (UNUSED)
-    output                      ram_clk1,       // clock
-    output                      ram_csb1,       // active low chip select
-    output  [ADDR_WIDTH-1:0]    ram_addr1,  
-    output  [31:0]              ram_dout1
+    input   [31:0]              ram_dout0,
+    output reg [31:0]           ram_din0
 );
 
-parameter ADDR_LO_MASK = (1 << ADDR_WIDTH) - 1;
-parameter ADDR_HI_MASK = 32'hffff_ffff - ADDR_LO_MASK;
-
-wire ram_cs;
-assign ram_cs = wbs_stb_i && wbs_cyc_i && ((wbs_adr_i & ADDR_HI_MASK) == BASE_ADDR) && !wb_rst_i;
-
-reg ram_cs_r;
-reg ram_wbs_ack_r;
-always @(negedge wb_clk_i) begin
+always @(posedge wb_clk_i) begin
     if (wb_rst_i) begin
-        ram_cs_r <= 0;
-        ram_wbs_ack_r <= 0;
-    end
-    else begin
-        ram_cs_r <= !ram_cs_r && ram_cs;
-        ram_wbs_ack_r <= ram_cs_r;
+        wbs_ack_o <= 1'b0;
+    end else begin
+        wbs_ack_o <= 1'b0;
+        if (wbs_cyc_i & wbs_stb_i & ~wbs_ack_o) begin
+            wbs_ack_o <= 1'b1;
+            wbs_dat_o <= ram_dout0;
+            if (wbs_we_i) begin
+                ram_din0 <= wbs_dat_i;
+            end
+        end
     end
 end
-     
-assign ram_clk0 = wb_clk_i;
-assign ram_csb0 = !ram_cs_r;
+
+assign ram_csb0 = ~wbs_stb_i;
 assign ram_web0 = ~wbs_we_i;
 assign ram_wmask0 = wbs_sel_i;
 assign ram_addr0 = wbs_adr_i[ADDR_WIDTH-1:0];
-assign ram_dout0 = wbs_dat_i;
 
-assign wbs_dat_o = ram_din0;
-assign wbs_ack_o = ram_wbs_ack_r && ram_cs;
+endmodule	// wb_openram_wrapper
+
+module wb_openram_wrapper
+#(
+    parameter BASE_ADDR = 32'h3000_0000,
+    parameter ADDR_WIDTH = 9
+)
+(
+`ifdef USE_POWER_PINS
+    inout vccd1,	// User area 1 1.8V supply
+    inout vssd1,	// User area 1 digital ground
+`endif
+    input wb_clk_i,
+    input wb_rst_i,
+
+    input [31:0] wbs_adr_i,
+    input [31:0] wbs_dat_i,
+    input [3:0] wbs_sel_i,
+    input wbs_we_i,
+    input wbs_cyc_i,
+    input wbs_stb_i,
+
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // OpenRAM interface - RW
+    output                      ram_csb0,
+    output                      ram_web0,
+    output  [3:0]              	ram_wmask0,
+    output  [ADDR_WIDTH-1:0]    ram_addr0,
+    input   [31:0]              ram_dout0,
+    output  [31:0]              ram_din0
+);
+
+    wire valid;
+    wire ram_wen;
+    wire [3:0] wen; // write enable
+
+    assign valid = wbs_cyc_i & wbs_stb_i;
+    assign ram_wen = wbs_we_i && valid;
+
+    assign wen = wbs_sel_i & {4{ram_wen}} ;
+
+    /*
+        Ack Generation
+            - write transaction: asserted upon receiving adr_i & dat_i 
+            - read transaction : asserted one clock cycle after receiving the adr_i & dat_i
+    */
+
+    reg wb_ack_read;
+    reg wbs_ack_o;
+
+    always @(posedge wb_clk_i) begin
+        if (wb_rst_i == 1'b 1) begin
+            wb_ack_read <= 1'b0;
+            wbs_ack_o <= 1'b0;
+        end else begin
+            wb_ack_read <= (valid & !wbs_ack_o) & !wb_ack_read;
+            wbs_ack_o    <= wbs_we_i? (valid & !wbs_ack_o): wb_ack_read;
+        end
+    end
+
+    assign ram_csb0 = ~valid;
+    assign ram_web0 = ~|wen;
+    assign ram_wmask0 = wen;
+    assign ram_addr0 = wbs_adr_i[ADDR_WIDTH-1:0];
+    assign wbs_dat_o = ram_dout0;
+    assign ram_din0 = wbs_dat_i;
 
 endmodule	// wb_openram_wrapper
 
diff --git a/openlane/user_project_wrapper/src/user_project_wrapper.v b/openlane/user_project_wrapper/src/user_project_wrapper.v
index e42e954..99600b5 100644
--- a/openlane/user_project_wrapper/src/user_project_wrapper.v
+++ b/openlane/user_project_wrapper/src/user_project_wrapper.v
@@ -93,9 +93,6 @@
 wire [8:0] o_waddr0;
 wire [31:0]o_din0;
 wire [31:0]i_dout0;
-wire o_csb1;
-wire [8:0] o_addr1;
-wire [31:0]i_dout1;
 
 wire o_csb0_1;
 wire o_web0_1;
@@ -103,9 +100,6 @@
 wire [8:0] o_waddr0_1;
 wire [31:0]o_din0_1;
 wire [31:0]i_dout0_1;
-wire o_csb1_1;
-wire [8:0] o_addr1_1;
-wire [31:0]i_dout1_1;
 
 sky130_sram_2kbyte_1rw1r_32x512_8 sram (
 `ifdef USE_POWER_PINS
@@ -119,10 +113,9 @@
     .addr0  (o_waddr0),
     .din0   (o_din0),
     .dout0  (i_dout0),
-    .clk1   (wb_clk_i),
-    .csb1   (o_csb1),
-    .addr1  (o_addr1),
-    .dout1  (i_dout1)
+    .clk1   (1'b0),
+    .csb1   (1'b0),
+    .addr1  (9'h0)
 );
 
 sky130_sram_2kbyte_1rw1r_32x512_8 sram1 (
@@ -137,10 +130,9 @@
     .addr0  (o_waddr0_1),
     .din0   (o_din0_1),
     .dout0  (i_dout0_1),
-    .clk1   (wb_clk_i),
-    .csb1   (o_csb1_1),
-    .addr1  (o_addr1_1),
-    .dout1  (i_dout1_1)
+    .clk1   (1'b0),
+    .csb1   (1'b0),
+    .addr1  (9'h0)
 );
 
 user_proj mprj (
@@ -149,6 +141,9 @@
 	.vssd1(vssd1),	// User area 1 digital ground
 `endif
 
+    .clk_i(wb_clk_i),
+    .rst_i(wb_rst_i),
+
     .wb_clk_i(wb_clk_i),
     .wb_rst_i(wb_rst_i),
 
@@ -180,22 +175,16 @@
     .o_waddr0(o_waddr0),
     .o_din0(o_din0),
     .i_dout0(i_dout0),
-    .o_addr1(o_addr1),
-    .i_dout1(i_dout1),
     .o_web0(o_web0),
     .o_csb0(o_csb0),
-    .o_csb1(o_csb1),
 
     // SRAM1
     .o_wmask0_1(o_wmask0_1),
     .o_waddr0_1(o_waddr0_1),
     .o_din0_1(o_din0_1),
     .i_dout0_1(i_dout0_1),
-    .o_addr1_1(o_addr1_1),
-    .i_dout1_1(i_dout1_1),
     .o_web0_1(o_web0_1),
-    .o_csb0_1(o_csb0_1),
-    .o_csb1_1(o_csb1_1)
+    .o_csb0_1(o_csb0_1)
 );
 
 endmodule	// user_project_wrapper