)]}'
{
  "commit": "19eb8caf2e8df2f7e755d64bf9d2ffff484a8708",
  "tree": "0667b514acb3992e77facbd00424a092438eab1b",
  "parents": [
    "b063f479d16d3d5e67fbfad0d70fbea1e54bdf13"
  ],
  "author": {
    "name": "gatecat",
    "email": "gatecat@ds0.me",
    "time": "Fri Nov 05 18:26:39 2021 +0000"
  },
  "committer": {
    "name": "gatecat",
    "email": "gatecat@ds0.me",
    "time": "Wed Dec 22 07:32:14 2021 +0000"
  },
  "message": "Add info.yaml and top level gl verilog\n\nSigned-off-by: gatecat \u003cgatecat@ds0.me\u003e\n",
  "tree_diff": [
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      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "86523c887179d698f698fb09e4371f34b6a9a4ca",
      "new_mode": 33188,
      "new_path": "info.yaml"
    },
    {
      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6207febaa2ca097c56454330ce2aedd72af88635",
      "new_mode": 33188,
      "new_path": "verilog/gl/user_project_wrapper.v"
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}