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# Created by write_sdc
# Sat Nov 13 06:59:56 2021
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current_design sdrc_top
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# Timing Constraints
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create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk_i}]
create_clock -name sdram_clk -period 20.0000 [get_ports {sdram_clk}]
create_clock -name pad_sdram_clk -period 20.0000 [get_ports {io_in[29]}]

set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]


set_clock_groups -name async_clock -asynchronous \
 -group [get_clocks {sdram_clk pad_sdram_clk}]\
 -group [get_clocks {wb_clk}] -comment {Async Clock group}

set_false_path -from [get_ports {cfg_colbits[0]}]
set_false_path -from [get_ports {cfg_colbits[1]}]
set_false_path -from [get_ports {cfg_req_depth[0]}]
set_false_path -from [get_ports {cfg_req_depth[1]}]
set_false_path -from [get_ports {cfg_sdr_cas[0]}]
set_false_path -from [get_ports {cfg_sdr_cas[1]}]
set_false_path -from [get_ports {cfg_sdr_cas[2]}]
set_false_path -from [get_ports {cfg_sdr_en}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[0]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[10]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[11]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[12]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[1]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[2]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[3]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[4]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[5]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[6]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[7]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[8]}]
set_false_path -from [get_ports {cfg_sdr_mode_reg[9]}]
set_false_path -from [get_ports {cfg_sdr_rfmax[0]}]
set_false_path -from [get_ports {cfg_sdr_rfmax[1]}]
set_false_path -from [get_ports {cfg_sdr_rfmax[2]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[0]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[10]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[11]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[1]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[2]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[3]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[4]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[5]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[6]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[7]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[8]}]
set_false_path -from [get_ports {cfg_sdr_rfsh[9]}]
set_false_path -from [get_ports {cfg_sdr_tras_d[0]}]
set_false_path -from [get_ports {cfg_sdr_tras_d[1]}]
set_false_path -from [get_ports {cfg_sdr_tras_d[2]}]
set_false_path -from [get_ports {cfg_sdr_tras_d[3]}]
set_false_path -from [get_ports {cfg_sdr_trcar_d[0]}]
set_false_path -from [get_ports {cfg_sdr_trcar_d[1]}]
set_false_path -from [get_ports {cfg_sdr_trcar_d[2]}]
set_false_path -from [get_ports {cfg_sdr_trcar_d[3]}]
set_false_path -from [get_ports {cfg_sdr_trcd_d[0]}]
set_false_path -from [get_ports {cfg_sdr_trcd_d[1]}]
set_false_path -from [get_ports {cfg_sdr_trcd_d[2]}]
set_false_path -from [get_ports {cfg_sdr_trcd_d[3]}]
set_false_path -from [get_ports {cfg_sdr_trp_d[0]}]
set_false_path -from [get_ports {cfg_sdr_trp_d[1]}]
set_false_path -from [get_ports {cfg_sdr_trp_d[2]}]
set_false_path -from [get_ports {cfg_sdr_trp_d[3]}]
set_false_path -from [get_ports {cfg_sdr_twr_d[0]}]
set_false_path -from [get_ports {cfg_sdr_twr_d[1]}]
set_false_path -from [get_ports {cfg_sdr_twr_d[2]}]
set_false_path -from [get_ports {cfg_sdr_twr_d[3]}]
set_false_path -from [get_ports {cfg_sdr_width[0]}]
set_false_path -from [get_ports {cfg_sdr_width[1]}]

set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[0]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[0]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[10]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[10]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[11]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[11]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[12]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[12]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[13]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[13]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[14]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[14]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[15]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[15]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[16]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[16]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[17]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[17]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[18]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[18]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[19]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[19]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[1]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[1]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[20]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[20]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[21]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[21]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[22]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[22]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[23]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[23]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[24]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[24]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[25]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[25]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[26]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[26]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[27]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[27]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[28]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[28]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[2]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[2]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[3]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[3]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[4]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[4]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[5]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[5]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[6]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[6]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[7]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[7]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[8]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[8]}]
set_input_delay 1.0000 -clock [get_clocks {pad_sdram_clk}] -min -add_delay [get_ports {io_in[9]}]
set_input_delay 12.0000 -clock [get_clocks {pad_sdram_clk}] -max -add_delay [get_ports {io_in[9]}]

set_input_delay -max 6.0000 -clock [get_clocks {sdram_clk}] -add_delay [get_ports {sdram_resetn}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[0]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[10]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[11]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[12]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[13]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[14]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[15]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[16]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[17]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[18]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[19]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[1]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[20]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[21]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[22]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[23]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[24]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[25]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[26]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[27]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[28]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[29]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[2]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[30]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[31]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[3]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[4]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[5]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[6]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[7]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[8]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[9]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_cyc_i}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[0]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[10]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[11]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[12]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[13]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[14]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[15]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[16]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[17]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[18]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[19]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[1]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[20]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[21]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[22]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[23]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[24]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[25]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[26]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[27]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[28]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[29]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[2]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[30]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[31]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[3]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[4]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[5]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[6]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[7]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[8]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[9]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_stb_i}]
set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_we_i}]

set_input_delay -min 2.0000 -clock [get_clocks {sdram_clk}] -add_delay [get_ports {sdram_resetn}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[0]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[10]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[11]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[12]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[13]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[14]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[15]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[16]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[17]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[18]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[19]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[1]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[20]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[21]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[22]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[23]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[24]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[25]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[26]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[27]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[28]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[29]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[2]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[30]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[31]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[3]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[4]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[5]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[6]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[7]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[8]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_addr_i[9]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_cyc_i}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[0]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[10]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[11]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[12]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[13]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[14]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[15]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[16]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[17]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[18]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[19]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[1]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[20]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[21]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[22]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[23]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[24]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[25]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[26]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[27]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[28]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[29]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[2]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[30]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[31]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[3]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[4]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[5]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[6]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[7]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[8]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_i[9]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[0]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[1]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[2]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_sel_i[3]}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_stb_i}]
set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_we_i}]

set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[0]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[0]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[10]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[10]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[11]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[11]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[12]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[12]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[13]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[13]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[14]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[14]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[15]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[15]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[16]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[16]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[17]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[17]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[18]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[18]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[19]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[19]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[1]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[1]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[20]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[20]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[21]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[21]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[22]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[22]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[23]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[23]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[24]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[24]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[25]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[25]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[26]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[26]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[27]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[27]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[28]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[28]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[29]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[29]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[2]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[2]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[3]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[3]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[4]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[4]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[5]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[5]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[6]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[6]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[7]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[7]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[8]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[8]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_oeb[9]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_oeb[9]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[0]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[0]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[10]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[10]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[11]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[11]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[12]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[12]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[13]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[13]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[14]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[14]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[15]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[15]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[16]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[16]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[17]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[17]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[18]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[18]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[19]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[19]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[1]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[1]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[20]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[20]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[21]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[21]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[22]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[22]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[23]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[23]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[24]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[24]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[25]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[25]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[26]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[26]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[27]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[27]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[28]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[28]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[2]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[2]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[3]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[3]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[4]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[4]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[5]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[5]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[6]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[6]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[7]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[7]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[8]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[8]}]
set_output_delay -0.5000 -clock [get_clocks {sdram_clk}] -min -add_delay [get_ports {io_out[9]}]
set_output_delay 12.0000 -clock [get_clocks {sdram_clk}] -max -add_delay [get_ports {io_out[9]}]

set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sdr_init_done}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_ack_o}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[0]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[10]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[11]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[12]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[13]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[14]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[15]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[16]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[17]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[18]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[19]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[1]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[20]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[21]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[22]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[23]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[24]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[25]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[26]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[27]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[28]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[29]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[2]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[30]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[31]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[3]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[4]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[5]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[6]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[7]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[8]}]
set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[9]}]

set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sdr_init_done}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_ack_o}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[0]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[10]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[11]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[12]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[13]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[14]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[15]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[16]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[17]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[18]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[19]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[1]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[20]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[21]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[22]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[23]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[24]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[25]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[26]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[27]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[28]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[29]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[2]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[30]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[31]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[3]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[4]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[5]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[6]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[7]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[8]}]
set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dat_o[9]}]
###############################################################################
# Environment
###############################################################################
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set_load  $cap_load [all_outputs]

set ::env(SYNTH_TIMING_DERATE) 0.05
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
###############################################################################
# Design Rules
###############################################################################