)]}'
{
  "commit": "28d63000a1db02a7d1108b423bdcd4de04b5e910",
  "tree": "60359fd70ae2cbf64cc964fc9aee1216906efe3a",
  "parents": [
    "a89ab453447e6d64ecac9fb3972450bfda98a3e2"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Fri Nov 05 22:46:15 2021 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Fri Nov 05 22:46:15 2021 +0530"
  },
  "message": "riscv compliace submodule are removed to pass mpw-3 documentation precheck\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7fc79710a439a259bf4de291749e8c9fbbf39994",
      "old_mode": 33188,
      "old_path": ".gitmodules",
      "new_id": "03d7cd91a9fac5f98af7bc9e543aff69238927c6",
      "new_mode": 33188,
      "new_path": ".gitmodules"
    },
    {
      "type": "delete",
      "old_id": "7f420b6bdbff436810ef75381059944e2b0d79e8",
      "old_mode": 57344,
      "old_path": "verilog/rtl/syntacore/scr1/dependencies/coremark",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "d51259b2a949be3af02e776c39e135402675ac9b",
      "old_mode": 57344,
      "old_path": "verilog/rtl/syntacore/scr1/dependencies/riscv-compliance",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "delete",
      "old_id": "e30978a71921159aec38eeefd848fca4ed39a826",
      "old_mode": 57344,
      "old_path": "verilog/rtl/syntacore/scr1/dependencies/riscv-tests",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    }
  ]
}
