MPW-4 Timing clean-up and software signature added

commit: 14a28a8a258a27c718e9a0091f54f7c7fc68d00b [log] [tgz]
author: dineshannayya <dinesh.annayya@gmail.com> Wed Dec 22 12:33:40 2021 +0530
committer: dineshannayya <dinesh.annayya@gmail.com> Wed Dec 22 12:33:40 2021 +0530
tree: 3cac7da2b15c1f8d9f688b667cc165f1096e1625
parent: ba29eaf91ba0438a4ff1b41ccddbb40328fc1874 [diff]
diff --git a/.gitmodules b/.gitmodules
index 03d7cd9..ccca397 100644
--- a/.gitmodules
+++ b/.gitmodules

@@ -1,3 +1,3 @@
-[submodule "caravel1"]
+[submodule "caravel5"]
 	path = caravel
 	url = https://github.com/efabless/caravel-lite.git

diff --git a/caravel b/caravel
index c294344..ff960da 160000
--- a/caravel
+++ b/caravel

@@ -1 +1 @@
-Subproject commit c2943440e278814787f761585b99b9ea3c1f4121
+Subproject commit ff960da6e06dd9097e7e1152e90f5998235a7882

diff --git a/def/glbl_cfg.def.gz b/def/glbl_cfg.def.gz
index 16ed7f1..5b90c90 100644
--- a/def/glbl_cfg.def.gz
+++ b/def/glbl_cfg.def.gz
Binary files differ

diff --git a/def/sdram.def.gz b/def/sdram.def.gz
index 982920e..79027cc 100644
--- a/def/sdram.def.gz
+++ b/def/sdram.def.gz
Binary files differ

diff --git a/def/spi_master.def.gz b/def/spi_master.def.gz
index 542a8ee..63594a3 100644
--- a/def/spi_master.def.gz
+++ b/def/spi_master.def.gz
Binary files differ

diff --git a/def/syntacore.def.gz b/def/syntacore.def.gz
index 2ac5860..7411cf4 100644
--- a/def/syntacore.def.gz
+++ b/def/syntacore.def.gz
Binary files differ

diff --git a/def/uart_i2cm_usb.def.gz b/def/uart_i2cm_usb.def.gz
index b52ad1c..d4a2ba4 100644
--- a/def/uart_i2cm_usb.def.gz
+++ b/def/uart_i2cm_usb.def.gz
Binary files differ

diff --git a/def/user_project_wrapper.def.gz b/def/user_project_wrapper.def.gz
index 7686d19..6cd71d4 100644
--- a/def/user_project_wrapper.def.gz
+++ b/def/user_project_wrapper.def.gz
Binary files differ

diff --git a/def/wb_host.def.gz b/def/wb_host.def.gz
index 0345332..54a2007 100644
--- a/def/wb_host.def.gz
+++ b/def/wb_host.def.gz
Binary files differ

diff --git a/def/wb_interconnect.def.gz b/def/wb_interconnect.def.gz
index 77f232b..1018e54 100644
--- a/def/wb_interconnect.def.gz
+++ b/def/wb_interconnect.def.gz
Binary files differ

diff --git a/gds/glbl_cfg.gds.gz b/gds/glbl_cfg.gds.gz
index 5abcb78..36637cd 100644
--- a/gds/glbl_cfg.gds.gz
+++ b/gds/glbl_cfg.gds.gz
Binary files differ

diff --git a/gds/sdram.gds.gz b/gds/sdram.gds.gz
index f1cd656..7626058 100644
--- a/gds/sdram.gds.gz
+++ b/gds/sdram.gds.gz
Binary files differ

diff --git a/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz
index ecd9328..5582d32 100644
--- a/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz
+++ b/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds.gz
Binary files differ

diff --git a/gds/spi_master.gds.gz b/gds/spi_master.gds.gz
index b8625f7..39ce48e 100644
--- a/gds/spi_master.gds.gz
+++ b/gds/spi_master.gds.gz
Binary files differ

diff --git a/gds/syntacore.gds.gz b/gds/syntacore.gds.gz
index 0a6e278..f766af1 100644
--- a/gds/syntacore.gds.gz
+++ b/gds/syntacore.gds.gz
Binary files differ

diff --git a/gds/uart_i2cm_usb.gds.gz b/gds/uart_i2cm_usb.gds.gz
index c6147d6..99f0ba1 100644
--- a/gds/uart_i2cm_usb.gds.gz
+++ b/gds/uart_i2cm_usb.gds.gz
Binary files differ

diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz
index 4296426..f4627d9 100644
--- a/gds/user_project_wrapper.gds.gz
+++ b/gds/user_project_wrapper.gds.gz
Binary files differ

diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz
index 57f3f39..375655d 100644
--- a/gds/wb_host.gds.gz
+++ b/gds/wb_host.gds.gz
Binary files differ

diff --git a/gds/wb_interconnect.gds.gz b/gds/wb_interconnect.gds.gz
index 0455b85..b360506 100644
--- a/gds/wb_interconnect.gds.gz
+++ b/gds/wb_interconnect.gds.gz
Binary files differ

diff --git a/lef/glbl_cfg.lef.gz b/lef/glbl_cfg.lef.gz
index 9edd5c5..c66c552 100644
--- a/lef/glbl_cfg.lef.gz
+++ b/lef/glbl_cfg.lef.gz
Binary files differ

diff --git a/lef/sdram.lef.gz b/lef/sdram.lef.gz
index fdec3aa..438799a 100644
--- a/lef/sdram.lef.gz
+++ b/lef/sdram.lef.gz
Binary files differ

diff --git a/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz
index de7ae3f..4539f9c 100644
--- a/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz
+++ b/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef.gz
Binary files differ

diff --git a/lef/spi_master.lef.gz b/lef/spi_master.lef.gz
index 78eba8e..2436355 100644
--- a/lef/spi_master.lef.gz
+++ b/lef/spi_master.lef.gz
Binary files differ

diff --git a/lef/syntacore.lef.gz b/lef/syntacore.lef.gz
index e97bc4e..cb4e86f 100644
--- a/lef/syntacore.lef.gz
+++ b/lef/syntacore.lef.gz
Binary files differ

diff --git a/lef/uart_i2cm_usb.lef.gz b/lef/uart_i2cm_usb.lef.gz
index 60138e3..2806be1 100644
--- a/lef/uart_i2cm_usb.lef.gz
+++ b/lef/uart_i2cm_usb.lef.gz
Binary files differ

diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz
index d421dac..07f4242 100644
--- a/lef/user_project_wrapper.lef.gz
+++ b/lef/user_project_wrapper.lef.gz
Binary files differ

diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz
index bb7b5a9..cd44dc2 100644
--- a/lef/wb_host.lef.gz
+++ b/lef/wb_host.lef.gz
Binary files differ

diff --git a/lef/wb_interconnect.lef.gz b/lef/wb_interconnect.lef.gz
index 2fb3633..69dd406 100644
--- a/lef/wb_interconnect.lef.gz
+++ b/lef/wb_interconnect.lef.gz
Binary files differ

diff --git a/mag/glbl_cfg.mag.gz b/mag/glbl_cfg.mag.gz
index fff7c10..b8d90fd 100644
--- a/mag/glbl_cfg.mag.gz
+++ b/mag/glbl_cfg.mag.gz
Binary files differ

diff --git a/mag/sdram.mag.gz b/mag/sdram.mag.gz
index a200548..9386f3a 100644
--- a/mag/sdram.mag.gz
+++ b/mag/sdram.mag.gz
Binary files differ

diff --git a/mag/spi_master.mag.gz b/mag/spi_master.mag.gz
index d54eb29..f6a667b 100644
--- a/mag/spi_master.mag.gz
+++ b/mag/spi_master.mag.gz
Binary files differ

diff --git a/mag/syntacore.mag.gz b/mag/syntacore.mag.gz
index 3d3187a..387ddd6 100644
--- a/mag/syntacore.mag.gz
+++ b/mag/syntacore.mag.gz
Binary files differ

diff --git a/mag/uart_i2cm_usb.mag.gz b/mag/uart_i2cm_usb.mag.gz
index 21ee468..52e95d0 100644
--- a/mag/uart_i2cm_usb.mag.gz
+++ b/mag/uart_i2cm_usb.mag.gz
Binary files differ

diff --git a/mag/user_project_wrapper.mag.gz b/mag/user_project_wrapper.mag.gz
index a1f5a11..bb9e1d0 100644
--- a/mag/user_project_wrapper.mag.gz
+++ b/mag/user_project_wrapper.mag.gz
Binary files differ

diff --git a/mag/wb_host.mag.gz b/mag/wb_host.mag.gz
index 72563b9..4af1c22 100644
--- a/mag/wb_host.mag.gz
+++ b/mag/wb_host.mag.gz
Binary files differ

diff --git a/mag/wb_interconnect.mag.gz b/mag/wb_interconnect.mag.gz
index 1f1b75c..f360ef7 100644
--- a/mag/wb_interconnect.mag.gz
+++ b/mag/wb_interconnect.mag.gz
Binary files differ

diff --git a/maglef/glbl_cfg.mag.gz b/maglef/glbl_cfg.mag.gz
index f41af68..9e9db97 100644
--- a/maglef/glbl_cfg.mag.gz
+++ b/maglef/glbl_cfg.mag.gz
Binary files differ

diff --git a/maglef/sdram.mag.gz b/maglef/sdram.mag.gz
index 11a4eef..9160796 100644
--- a/maglef/sdram.mag.gz
+++ b/maglef/sdram.mag.gz
Binary files differ

diff --git a/maglef/spi_master.mag.gz b/maglef/spi_master.mag.gz
index f65e510..44ffb23 100644
--- a/maglef/spi_master.mag.gz
+++ b/maglef/spi_master.mag.gz
Binary files differ

diff --git a/maglef/syntacore.mag.gz b/maglef/syntacore.mag.gz
index 785e2b0..ac957d8 100644
--- a/maglef/syntacore.mag.gz
+++ b/maglef/syntacore.mag.gz
Binary files differ

diff --git a/maglef/uart_i2cm_usb.mag.gz b/maglef/uart_i2cm_usb.mag.gz
index b861f44..05bfec2 100644
--- a/maglef/uart_i2cm_usb.mag.gz
+++ b/maglef/uart_i2cm_usb.mag.gz
Binary files differ

diff --git a/maglef/user_project_wrapper.mag.gz b/maglef/user_project_wrapper.mag.gz
index 3aaabc7..1ee912a 100644
--- a/maglef/user_project_wrapper.mag.gz
+++ b/maglef/user_project_wrapper.mag.gz
Binary files differ

diff --git a/maglef/wb_host.mag.gz b/maglef/wb_host.mag.gz
index 4e4906a..ed020f3 100644
--- a/maglef/wb_host.mag.gz
+++ b/maglef/wb_host.mag.gz
Binary files differ

diff --git a/maglef/wb_interconnect.mag.gz b/maglef/wb_interconnect.mag.gz
index 9704e87..bbff7c9 100644
--- a/maglef/wb_interconnect.mag.gz
+++ b/maglef/wb_interconnect.mag.gz
Binary files differ

diff --git a/openlane/Makefile b/openlane/Makefile
index b0c8009..a960416 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile

@@ -19,8 +19,8 @@
 CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
 CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
 
-OPENLANE_TAG = mpw4
-OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_TAG ?= mpw4
+OPENLANE_IMAGE_NAME ?= dineshannayya/openlane:$(OPENLANE_TAG)
 OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
 

diff --git a/openlane/glbl_cfg/base.sdc b/openlane/glbl_cfg/base.sdc
index b9b1472..92de6af 100644
--- a/openlane/glbl_cfg/base.sdc
+++ b/openlane/glbl_cfg/base.sdc

@@ -7,14 +7,11 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name mclk -period 10.0000 [get_ports {mclk}]
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -setup 0.2000
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
 
 set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[0]}]
 set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[1]}]
@@ -398,204 +395,15 @@
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_en}]
-set_load -pin_load 0.0334 [get_ports {reg_ack}]
-set_load -pin_load 0.0334 [get_ports {soft_irq}]
-set_load -pin_load 0.0334 [get_ports {wbd_clk_glbl}]
-set_load -pin_load 0.0334 [get_ports {cfg_colbits[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_colbits[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_req_depth[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_req_depth[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_cas[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[12]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[11]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[10]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[9]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[8]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_mode_reg[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfmax[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[11]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[10]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[9]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[8]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_rfsh[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_tras_d[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcar_d[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trcd_d[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_trp_d[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_twr_d[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_width[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_sdr_width[0]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[31]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[30]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[29]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[28]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[27]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[26]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[25]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[24]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[23]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[22]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[21]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[20]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[19]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[18]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[17]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[16]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[15]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[14]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[13]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[12]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[11]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[10]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[9]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[8]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[7]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[6]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[5]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[4]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[3]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[2]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[1]}]
-set_load -pin_load 0.0334 [get_ports {fuse_mhartid[0]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[15]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[14]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[13]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[12]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[11]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[10]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[9]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[8]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[7]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[6]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[5]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[4]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[3]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[2]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[1]}]
-set_load -pin_load 0.0334 [get_ports {irq_lines[0]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
-set_load -pin_load 0.0334 [get_ports {user_irq[2]}]
-set_load -pin_load 0.0334 [get_ports {user_irq[1]}]
-set_load -pin_load 0.0334 [get_ports {user_irq[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdr_init_done}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_glbl[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 ###############################################################################
 # Design Rules
 ###############################################################################

diff --git a/openlane/glbl_cfg/config.tcl b/openlane/glbl_cfg/config.tcl
index 085b9b7..0347c4f 100755
--- a/openlane/glbl_cfg/config.tcl
+++ b/openlane/glbl_cfg/config.tcl

@@ -30,6 +30,11 @@
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -42,6 +47,7 @@
 	"
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 

diff --git a/openlane/sdram/base.sdc b/openlane/sdram/base.sdc
index 1d7a6de..a0337e3 100644
--- a/openlane/sdram/base.sdc
+++ b/openlane/sdram/base.sdc

@@ -9,30 +9,12 @@
 create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk_i}]
 create_clock -name sdram_clk -period 20.0000 [get_ports {sdram_clk}]
 create_clock -name pad_sdram_clk -period 20.0000 [get_ports {io_in[29]}]
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -hold 0.1500
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -hold 0.1500
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -hold 0.1500
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -hold 0.1500
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -rise_from [get_clocks {sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -rise_from [get_clocks {sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -fall_from [get_clocks {sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -fall_from [get_clocks {sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {pad_sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -rise_from [get_clocks {pad_sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {pad_sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -rise_from [get_clocks {pad_sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {pad_sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -fall_from [get_clocks {pad_sdram_clk}] -rise_to [get_clocks {sdram_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {pad_sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -hold 0.1500
-set_clock_uncertainty -fall_from [get_clocks {pad_sdram_clk}] -fall_to [get_clocks {sdram_clk}]  -setup 0.2000
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {sdram_clk pad_sdram_clk}]\
  -group [get_clocks {wb_clk}] -comment {Async Clock group}
@@ -494,310 +476,15 @@
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {sdr_init_done}]
-set_load -pin_load 0.0334 [get_ports {wb_ack_o}]
-set_load -pin_load 0.0334 [get_ports {wbd_clk_sdram}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[29]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[28]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[27]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[26]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[25]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[24]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[23]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[22]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[21]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[20]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[19]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[18]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[17]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[16]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[15]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[14]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[13]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[12]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[11]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[10]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[9]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[8]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[7]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[6]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
-set_load -pin_load 0.0334 [get_ports {io_out[29]}]
-set_load -pin_load 0.0334 [get_ports {io_out[28]}]
-set_load -pin_load 0.0334 [get_ports {io_out[27]}]
-set_load -pin_load 0.0334 [get_ports {io_out[26]}]
-set_load -pin_load 0.0334 [get_ports {io_out[25]}]
-set_load -pin_load 0.0334 [get_ports {io_out[24]}]
-set_load -pin_load 0.0334 [get_ports {io_out[23]}]
-set_load -pin_load 0.0334 [get_ports {io_out[22]}]
-set_load -pin_load 0.0334 [get_ports {io_out[21]}]
-set_load -pin_load 0.0334 [get_ports {io_out[20]}]
-set_load -pin_load 0.0334 [get_ports {io_out[19]}]
-set_load -pin_load 0.0334 [get_ports {io_out[18]}]
-set_load -pin_load 0.0334 [get_ports {io_out[17]}]
-set_load -pin_load 0.0334 [get_ports {io_out[16]}]
-set_load -pin_load 0.0334 [get_ports {io_out[15]}]
-set_load -pin_load 0.0334 [get_ports {io_out[14]}]
-set_load -pin_load 0.0334 [get_ports {io_out[13]}]
-set_load -pin_load 0.0334 [get_ports {io_out[12]}]
-set_load -pin_load 0.0334 [get_ports {io_out[11]}]
-set_load -pin_load 0.0334 [get_ports {io_out[10]}]
-set_load -pin_load 0.0334 [get_ports {io_out[9]}]
-set_load -pin_load 0.0334 [get_ports {io_out[8]}]
-set_load -pin_load 0.0334 [get_ports {io_out[7]}]
-set_load -pin_load 0.0334 [get_ports {io_out[6]}]
-set_load -pin_load 0.0334 [get_ports {io_out[5]}]
-set_load -pin_load 0.0334 [get_ports {io_out[4]}]
-set_load -pin_load 0.0334 [get_ports {io_out[3]}]
-set_load -pin_load 0.0334 [get_ports {io_out[2]}]
-set_load -pin_load 0.0334 [get_ports {io_out[1]}]
-set_load -pin_load 0.0334 [get_ports {io_out[0]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[31]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[30]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[29]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[28]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[27]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[26]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[25]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[24]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[23]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[22]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[21]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[20]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[19]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[18]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[17]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[16]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[15]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[14]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[13]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[12]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[11]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[10]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[9]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[8]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[7]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[6]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[5]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[4]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[3]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[2]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[1]}]
-set_load -pin_load 0.0334 [get_ports {sdram_debug[0]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wb_dat_o[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
 
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_en}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdram_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sdram_resetn}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_stb_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_colbits[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_colbits[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_ci[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_ci[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_ci[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_ci[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_co[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_co[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_co[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sd_co[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sdram[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sdram[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sdram[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sdram[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_req_depth[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_req_depth[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_cas[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_cas[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_cas[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_mode_reg[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfmax[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfmax[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfmax[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_rfsh[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_tras_d[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_tras_d[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_tras_d[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_tras_d[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcar_d[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcar_d[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcar_d[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcar_d[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcd_d[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcd_d[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcd_d[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trcd_d[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trp_d[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trp_d[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trp_d[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_trp_d[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_twr_d[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_twr_d[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_twr_d[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_twr_d[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_width[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_sdr_width[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_addr_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[0]}]
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 ###############################################################################
 # Design Rules
 ###############################################################################

diff --git a/openlane/sdram/config.tcl b/openlane/sdram/config.tcl
index 41c15fb..4826097 100755
--- a/openlane/sdram/config.tcl
+++ b/openlane/sdram/config.tcl

@@ -31,6 +31,11 @@
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -46,7 +51,9 @@
          $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v \
          $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v\ 
          $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v \
-         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v "
+         $script_dir/../../verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v \
+         $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+         "
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ]
 

diff --git a/openlane/spi_master/base.sdc b/openlane/spi_master/base.sdc
index 14ca6db..00e9241 100644
--- a/openlane/spi_master/base.sdc
+++ b/openlane/spi_master/base.sdc

@@ -23,35 +23,45 @@
 set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
 
 set_propagated_clock [get_clocks {spiclk}]
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}]      -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {mclk}] -fall_to [get_clocks {mclk}]      -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -rise_to [get_clocks {spiclk}]  -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {spiclk}] -fall_to [get_clocks {spiclk}]  -setup 0.2500
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_spi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_spi[3]}]
+
+
+set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_spi}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_spi
 
 #Static Clock Skew control
-set_false_path -from [get_ports {cfg_cska_sp_co[3]}]
-set_false_path -from [get_ports {cfg_cska_sp_co[2]}]
-set_false_path -from [get_ports {cfg_cska_sp_co[1]}]
-set_false_path -from [get_ports {cfg_cska_sp_co[0]}]
-set_false_path -from [get_ports {cfg_cska_spi[3]}]
-set_false_path -from [get_ports {cfg_cska_spi[2]}]
-set_false_path -from [get_ports {cfg_cska_spi[1]}]
-set_false_path -from [get_ports {cfg_cska_spi[0]}]
-set_max_delay 3  -to   [get_ports {wbd_clk_spi}]
-set_max_delay 3  -from [get_ports {wbd_clk_int}]
- 
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}]
+
 set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
 set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}]
 
@@ -338,171 +348,10 @@
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {io_out[0]}]
-set_load -pin_load 0.0334 [get_ports {io_out[1]}]
-set_load -pin_load 0.0334 [get_ports {io_out[2]}]
-set_load -pin_load 0.0334 [get_ports {io_out[3]}]
-set_load -pin_load 0.0334 [get_ports {io_out[4]}]
-set_load -pin_load 0.0334 [get_ports {io_out[5]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[2]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[3]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[4]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[5]}]
-set_load -pin_load 0.0334 [get_ports {wbd_ack_o}]
-set_load -pin_load 0.0334 [get_ports {wbd_clk_spi}]
-set_load -pin_load 0.0334 [get_ports {wbd_err_o}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[31]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[30]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[29]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[28]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[27]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[26]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[25]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[24]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[23]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[22]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[21]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[20]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[19]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[18]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[17]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[16]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[15]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[14]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[13]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[12]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[11]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[10]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[9]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[8]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[7]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[6]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[5]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[4]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[3]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[2]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[1]}]
-set_load -pin_load 0.0334 [get_ports {spi_debug[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dat_o[0]}]
-
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mclk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_stb_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_sp_co[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_spi[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_adr_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_sel_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
 ###############################################################################
 # Design Rules
 ###############################################################################

diff --git a/openlane/spi_master/config.tcl b/openlane/spi_master/config.tcl
index 6383c56..fee12ce 100755
--- a/openlane/spi_master/config.tcl
+++ b/openlane/spi_master/config.tcl

@@ -31,6 +31,11 @@
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -45,8 +50,11 @@
         $script_dir/../../verilog/rtl/spi_master/src/spim_clkgen.sv \
         $script_dir/../../verilog/rtl/spi_master/src/spim_ctrl.sv \
         $script_dir/../../verilog/rtl/spi_master/src/spim_rx.sv \
-        $script_dir/../../verilog/rtl/spi_master/src/spim_tx.sv "
+        $script_dir/../../verilog/rtl/spi_master/src/spim_tx.sv \
+        $script_dir/../../verilog/rtl/lib/ctech_cells.sv \
+        "
 
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"

diff --git a/openlane/syntacore/base.sdc b/openlane/syntacore/base.sdc
index 7c0ac5d..a811f4a 100644
--- a/openlane/syntacore/base.sdc
+++ b/openlane/syntacore/base.sdc

@@ -9,700 +9,108 @@
 create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
 create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
 create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]  -setup 0.2000
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -rise_to [get_clocks {core_clk}]  -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {core_clk}] -fall_to [get_clocks {core_clk}]  -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]    -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]    -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]    -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]    -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]    -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -rise_to [get_clocks {rtc_clk}]    -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]    -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {rtc_clk}] -fall_to [get_clocks {rtc_clk}]    -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]      -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]      -setup 0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]      -hold  0.2500
+set_clock_uncertainty -rise_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]      -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]      -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -rise_to [get_clocks {wb_clk}]      -setup 0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]      -hold  0.2500
+set_clock_uncertainty -fall_from [get_clocks {wb_clk}] -fall_to [get_clocks {wb_clk}]      -setup 0.2500
+
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {core_clk}]\
  -group [get_clocks {rtc_clk}]\
  -group [get_clocks {wb_clk}] -comment {Async Clock group}
 
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_riscv[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_riscv[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_riscv[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_riscv[3]}]
 
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[0]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[10]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[11]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[12]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[13]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[14]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[15]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[16]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[17]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[18]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[19]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[1]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[20]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[21]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[22]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[23]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[24]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[25]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[26]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[27]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[28]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[29]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[2]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[30]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[31]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[3]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[4]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[5]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[6]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[7]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[8]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[9]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[0]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[10]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[11]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[12]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[13]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[14]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[15]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[16]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[17]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[18]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[19]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[1]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[20]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[21]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[22]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[23]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[24]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[25]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[26]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[27]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[28]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[29]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[2]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[30]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[31]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[3]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[4]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[5]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[6]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[7]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[8]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[9]}]
 
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[0]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[10]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[11]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[12]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[13]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[14]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[15]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[16]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[17]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[18]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[19]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[1]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[20]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[21]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[22]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[23]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[24]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[25]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[26]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[27]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[28]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[29]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[2]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[30]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[31]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[3]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[4]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[5]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[6]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[7]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[8]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[9]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[0]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[10]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[11]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[12]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[13]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[14]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[15]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[16]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[17]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[18]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[19]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[1]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[20]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[21]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[22]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[23]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[24]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[25]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[26]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[27]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[28]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[29]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[2]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[30]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[31]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[3]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[4]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[5]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[6]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[7]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[8]}]
-set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[9]}]
+set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_riscv}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_riscv
 
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[8]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[*]}]
+
+set_input_delay -min 3.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout0[*]}]
+set_input_delay -min 3.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {sram_dout1[*]}]
+
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[*]}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb0}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb1}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[9]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[*]}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_web0}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[*]}]
 
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[8]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[8]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_addr1[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb0}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_csb1}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[10]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[11]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[12]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[13]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[14]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[15]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[16]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[17]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[18]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[19]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[20]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[21]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[22]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[23]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[24]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[25]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[26]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[27]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[28]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[29]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[30]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[31]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[8]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[9]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_din0[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_web0}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {sram_wmask0[*]}]
 
 
 set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}]
 set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[0]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[10]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[11]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[12]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[13]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[14]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[15]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[16]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[17]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[18]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[19]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[1]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[20]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[21]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[22]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[23]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[24]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[25]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[26]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[27]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[28]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[29]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[2]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[30]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[31]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[3]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[4]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[5]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[6]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[7]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[8]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[9]}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
 set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
 set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[0]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[10]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[11]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[12]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[13]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[14]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[15]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[16]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[17]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[18]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[19]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[1]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[20]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[21]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[22]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[23]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[24]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[25]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[26]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[27]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[28]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[29]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[2]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[30]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[31]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[3]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[4]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[5]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[6]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[7]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[8]}]
-set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[9]}]
+set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[*]}]
 set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}]
 
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[0]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[10]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[11]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[12]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[13]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[14]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[15]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[16]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[17]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[18]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[19]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[1]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[20]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[21]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[22]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[23]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[24]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[25]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[26]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[27]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[28]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[29]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[2]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[30]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[31]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[3]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[4]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[5]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[6]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[7]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[8]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[9]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
 set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_ack_i}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[0]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[10]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[11]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[12]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[13]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[14]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[15]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[16]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[17]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[18]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[19]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[1]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[20]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[21]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[22]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[23]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[24]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[25]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[26]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[27]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[28]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[29]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[2]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[30]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[31]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[3]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[4]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[5]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[6]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[7]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[8]}]
-set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[9]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_i[*]}]
 set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_err_i}]
 
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[9]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[9]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[9]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[9]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[*]}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}]
 set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}]
 
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[10]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[11]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[12]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[13]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[14]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[15]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[16]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[17]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[18]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[19]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[20]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[21]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[22]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[23]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[24]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[25]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[26]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[27]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[28]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[29]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[30]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[31]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[8]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[9]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[10]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[11]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[12]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[13]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[14]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[15]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[16]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[17]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[18]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[19]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[20]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[21]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[22]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[23]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[24]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[25]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[26]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[27]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[28]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[29]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[30]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[31]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[8]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[9]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[10]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[11]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[12]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[13]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[14]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[15]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[16]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[17]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[18]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[19]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[20]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[21]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[22]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[23]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[24]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[25]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[26]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[27]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[28]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[29]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[30]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[31]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[8]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[9]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[10]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[11]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[12]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[13]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[14]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[15]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[16]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[17]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[18]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[19]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[20]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[21]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[22]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[23]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[24]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[25]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[26]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[27]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[28]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[29]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[30]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[31]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[3]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[4]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[5]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[6]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[7]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[8]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[9]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[0]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[1]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[2]}]
-set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[3]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_sel_o[*]}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_stb_o}]
 set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_imem_we_o}]
 
@@ -828,455 +236,11 @@
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {sram_csb0}]
-set_load -pin_load 0.0334 [get_ports {sram_csb1}]
-set_load -pin_load 0.0334 [get_ports {sram_web0}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_stb_o}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_we_o}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_stb_o}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_we_o}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[63]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[62]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[61]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[60]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[59]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[58]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[57]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[56]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[55]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[54]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[53]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[52]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[51]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[50]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[49]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[48]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[47]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[46]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[45]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[44]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[43]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[42]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[41]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[40]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[39]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[38]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[37]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[36]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[35]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[34]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[33]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[32]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[31]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[30]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[29]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[28]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[27]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[26]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[25]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[24]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[23]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[22]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[21]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[20]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[19]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[18]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[17]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[16]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[15]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[14]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[13]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[12]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[11]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[10]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[9]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[8]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[7]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[6]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[5]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[4]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[3]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[2]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[1]}]
-set_load -pin_load 0.0334 [get_ports {riscv_debug[0]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[8]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[7]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[6]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[5]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[4]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[3]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[2]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[1]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr0[0]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[8]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[7]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[6]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[5]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[4]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[3]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[2]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[1]}]
-set_load -pin_load 0.0334 [get_ports {sram_addr1[0]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[31]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[30]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[29]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[28]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[27]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[26]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[25]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[24]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[23]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[22]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[21]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[20]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[19]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[18]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[17]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[16]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[15]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[14]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[13]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[12]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[11]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[10]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[9]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[8]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[7]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[6]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[5]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[4]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[3]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[2]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[1]}]
-set_load -pin_load 0.0334 [get_ports {sram_din0[0]}]
-set_load -pin_load 0.0334 [get_ports {sram_wmask0[3]}]
-set_load -pin_load 0.0334 [get_ports {sram_wmask0[2]}]
-set_load -pin_load 0.0334 [get_ports {sram_wmask0[1]}]
-set_load -pin_load 0.0334 [get_ports {sram_wmask0[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_dmem_sel_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbd_imem_sel_o[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {core_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cpu_rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pwrup_rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rtc_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {soft_irq}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_err_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_err_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {fuse_mhartid[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {irq_lines[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout0[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sram_dout1[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_dmem_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_imem_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
 ###############################################################################
 # Design Rules
 ###############################################################################

diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl
index 20a9534..649234a 100755
--- a/openlane/syntacore/config.tcl
+++ b/openlane/syntacore/config.tcl

@@ -30,6 +30,11 @@
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -70,6 +75,7 @@
 
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ]
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"

diff --git a/openlane/uart_i2cm_usb/base.sdc b/openlane/uart_i2cm_usb/base.sdc
index ee3e781..bf73912 100644
--- a/openlane/uart_i2cm_usb/base.sdc
+++ b/openlane/uart_i2cm_usb/base.sdc

@@ -7,313 +7,70 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name app_clk -period 10.0000 [get_ports {app_clk}]
-create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf/X}]
+create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf.u_mux/X}]
 create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}]
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -rise_to [get_clocks {usb_clk}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {usb_clk}] -fall_to [get_clocks {usb_clk}]  -setup 0.2000
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
+
+
 set_clock_groups -name async_clock -asynchronous \
  -group [get_clocks {app_clk}]\
- -group [get_clocks {line_clk}]\
- -group [get_clocks {usb_clk}] -comment {Async Clock group}
-set_input_delay 0.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {i2c_rstn}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {i2c_rstn}]
-set_input_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_in[0]}]
-set_input_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_in[0]}]
-set_input_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_in[1]}]
-set_input_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_in[1]}]
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {line_clk}] -comment {Async Clock group}
 
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[0]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[0]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[1]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[1]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[2]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[2]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_addr[3]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_addr[3]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[0]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[0]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[1]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[1]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[2]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[2]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_be[3]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_be[3]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_cs}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_cs}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[0]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[0]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[10]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[10]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[11]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[11]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[12]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[12]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[13]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[13]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[14]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[14]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[15]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[15]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[16]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[16]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[17]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[17]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[18]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[18]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[19]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[19]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[1]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[1]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[20]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[20]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[21]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[21]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[22]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[22]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[23]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[23]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[24]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[24]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[25]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[25]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[26]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[26]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[27]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[27]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[28]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[28]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[29]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[29]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[2]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[2]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[30]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[30]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[31]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[31]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[3]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[3]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[4]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[4]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[5]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[5]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[6]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[6]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[7]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[7]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[8]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[8]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wdata[9]}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wdata[9]}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_wr}]
-set_input_delay 6.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_wr}]
-set_input_delay 0.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {uart_rstn}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {uart_rstn}]
-set_input_delay 0.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {usb_rstn}]
-set_input_delay 2.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {usb_rstn}]
-set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_oeb[0]}]
-set_output_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_oeb[0]}]
-set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_oeb[1]}]
-set_output_delay 60.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_oeb[1]}]
-set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_out[0]}]
-set_output_delay 40.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_out[0]}]
-set_output_delay 2.0000 -clock [get_clocks {line_clk}] -min -add_delay [get_ports {io_out[1]}]
-set_output_delay 40.0000 -clock [get_clocks {line_clk}] -max -add_delay [get_ports {io_out[1]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_ack}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_ack}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[0]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[0]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[10]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[10]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[11]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[11]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[12]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[12]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[13]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[13]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[14]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[14]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[15]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[15]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[16]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[16]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[17]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[17]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[18]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[18]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[19]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[19]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[1]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[1]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[20]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[20]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[21]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[21]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[22]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[22]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[23]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[23]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[24]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[24]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[25]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[25]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[26]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[26]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[27]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[27]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[28]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[28]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[29]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[29]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[2]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[2]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[30]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[30]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[31]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[31]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[3]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[3]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[4]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[4]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[5]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[5]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[6]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[6]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[7]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[7]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[8]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[8]}]
-set_output_delay 2.0000 -clock [get_clocks {app_clk}] -min -add_delay [get_ports {reg_rdata[9]}]
-set_output_delay 4.0000 -clock [get_clocks {app_clk}] -max -add_delay [get_ports {reg_rdata[9]}]
-set_multicycle_path -hold\
-    -from [list [get_ports {reg_cs}]\
-           [get_ports {reg_wr}]]\
-    -to [get_ports {reg_ack}] 1
-set_multicycle_path -setup\
-    -from [list [get_ports {reg_cs}]\
-           [get_ports {reg_wr}]]\
-    -to [get_ports {reg_ack}] 2
-set_max_delay\
-    -from [list [get_ports {uart_i2c_usb_sel[0]}]\
-           [get_ports {uart_i2c_usb_sel[1]}]] 10.0000
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_uart[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_uart[3]}]
+
+
+set_max_delay 5 -from [get_ports {wbd_clk_int}]
+set_max_delay 5 -to   [get_ports {wbd_clk_uart}]
+set_max_delay 5 -from wbd_clk_int -to wbd_clk_uart
+
+
+
+set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
+set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
+set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
+
+
+set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
+set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay  -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
+
+set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
+set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_be[*]}]
+set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}]
+set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wdata[*]}]
+set_input_delay  -min 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wr}]
+
+
+set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+
+set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}]
+set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}]
+
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {reg_ack}]
-set_load -pin_load 0.0334 [get_ports {wbd_clk_uart}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[1]}]
-set_load -pin_load 0.0334 [get_ports {io_oeb[0]}]
-set_load -pin_load 0.0334 [get_ports {io_out[1]}]
-set_load -pin_load 0.0334 [get_ports {io_out[0]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[31]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[30]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[29]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[28]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[27]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[26]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[25]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[24]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[23]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[22]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[21]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[20]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[19]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[18]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[17]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[16]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[15]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[14]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[13]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[12]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[11]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[10]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[9]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[8]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[7]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[6]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[5]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[4]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[3]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[2]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[1]}]
-set_load -pin_load 0.0334 [get_ports {reg_rdata[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {app_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {i2c_rstn}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_cs}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wr}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_rstn}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_clk}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {usb_rstn}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_uart[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_in[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_addr[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_be[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reg_wdata[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_i2c_usb_sel[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {uart_i2c_usb_sel[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
 ###############################################################################
 # Design Rules
 ###############################################################################

diff --git a/openlane/uart_i2cm_usb/config.tcl b/openlane/uart_i2cm_usb/config.tcl
index 329046f..02427d2 100644
--- a/openlane/uart_i2cm_usb/config.tcl
+++ b/openlane/uart_i2cm_usb/config.tcl

@@ -27,10 +27,15 @@
 
 # Timing configuration
 set ::env(CLOCK_PERIOD) "10"
-set ::env(CLOCK_PORT) "app_clk usb_clk"
+set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.u_lineclk_buf.u_mux/X"
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -60,10 +65,12 @@
     $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\
     $script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv     \
     $script_dir/../../verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv\
+    $script_dir/../../verilog/rtl/lib/ctech_cells.sv     
     "
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
 set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
@@ -106,11 +113,7 @@
 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
 set ::env(DIODE_INSERTION_STRATEGY) 4
 
-
 set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
-set ::env(QUIT_ON_SETUP_VIOLATIONS) "0"
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
-

diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc
index f43c9d3..2841639 100644
--- a/openlane/wb_host/base.sdc
+++ b/openlane/wb_host/base.sdc

@@ -8,757 +8,94 @@
 ###############################################################################
 create_clock -name wbm_clk_i -period 10.0000 [get_ports {wbm_clk_i}]
 create_clock -name wbs_clk_i -period 10.0000 [get_ports {wbs_clk_i}]
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold  0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.4000
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold  0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -hold  0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -rise_to [get_clocks {wbm_clk_i}]  -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -hold  0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbm_clk_i}] -fall_to [get_clocks {wbm_clk_i}]  -setup 0.4000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold  0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.4000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold  0.2000
-set_clock_uncertainty -rise_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -hold  0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -rise_to [get_clocks {wbs_clk_i}]  -setup 0.4000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -hold  0.2000
-set_clock_uncertainty -fall_from [get_clocks {wbs_clk_i}] -fall_to [get_clocks {wbs_clk_i}]  -setup 0.4000
+
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
+
 set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {wbm_clk_i}]\
- -group [get_clocks {wbs_clk_i}] -comment {Async Clock group}
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {wbm_clk_i}] -comment {Async Clock group}
+
+### ClkSkew Adjust
+set_case_analysis 0 [get_ports {cfg_cska_wh[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wh[3]}]
+
+
+set_max_delay   3.5 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_wh}]
+set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_wh
 
 ### WBM I/F
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_cyc_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[9]}]
-set_input_delay -max 2.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_rst_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_stb_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_we_i}]
+#Strobe is registered inside the wb_host before generating chip select
+# So wbm_adr_i  wbm_we_i wbm_sel_i wbm_dat_i are having 2 cycle setup
+set_multicycle_path -setup  -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -setup  -from [get_ports {wbm_cyc_i}]  2
+set_multicycle_path -setup  -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -setup  -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -setup  -from [get_ports {wbm_we_i}] 2
 
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[0]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[10]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[11]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[12]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[13]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[14]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[15]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[16]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[17]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[18]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[19]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[1]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[20]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[21]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[22]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[23]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[24]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[25]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[26]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[27]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[28]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[29]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[2]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[30]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[31]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[3]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[4]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[5]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[6]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[7]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[8]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[9]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_cyc_i}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[0]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[10]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[11]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[12]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[13]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[14]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[15]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[16]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[17]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[18]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[19]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[1]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[20]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[21]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[22]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[23]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[24]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[25]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[26]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[27]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[28]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[29]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[2]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[30]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[31]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[3]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[4]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[5]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[6]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[7]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[8]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[9]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_rst_i}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[0]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[1]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[2]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[3]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_stb_i}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_we_i}]
+set_multicycle_path -hold  -from [get_ports {wbm_adr_i[*]}] 2
+set_multicycle_path -hold  -from [get_ports {wbm_cyc_i}]  2
+set_multicycle_path -hold  -from [get_ports {wbm_dat_i[*]}] 2
+set_multicycle_path -hold  -from [get_ports {wbm_sel_i[*]}] 2
+set_multicycle_path -hold  -from [get_ports {wbm_we_i}] 2
 
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[0]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[10]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[11]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[12]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[13]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[14]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[15]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[16]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[17]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[18]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[19]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[1]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[20]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[21]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[22]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[23]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[24]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[25]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[26]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[27]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[28]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[29]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[2]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[30]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[31]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[3]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[4]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[5]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[6]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[7]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[8]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[9]}]
-set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
+#
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 5.0000 -clock [get_clocks {wbm_clk_i}] -max -add_delay [get_ports {wbm_stb_i}]
+
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_rst_i}]
+set_input_delay 1.0000 -clock [get_clocks {wbm_clk_i}] -min -add_delay [get_ports {wbm_stb_i}]
+
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
+set_output_delay -max 5.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
 
 set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[0]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[10]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[11]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[12]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[13]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[14]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[15]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[16]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[17]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[18]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[19]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[1]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[20]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[21]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[22]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[23]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[24]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[25]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[26]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[27]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[28]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[29]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[2]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[30]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[31]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[3]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[4]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[5]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[6]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[7]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[8]}]
-set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[9]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[*]}]
 set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_err_o}]
 # WBS I/F
 set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
 
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}]
-set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[*]}]
 
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[9]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
 set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[0]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[1]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[2]}]
-set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[3]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
 set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
 set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
 
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[0]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[10]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[11]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[12]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[13]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[14]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[15]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[16]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[17]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[18]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[19]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[1]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[20]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[21]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[22]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[23]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[24]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[25]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[26]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[27]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[28]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[29]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[2]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[30]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[31]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[3]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[4]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[5]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[6]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[7]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[8]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[9]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[0]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[1]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[2]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[3]}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
-set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[*]}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}]
+set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}]
 
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {cpu_clk}]
-set_load -pin_load 0.0334 [get_ports {cpu_rst_n}]
-set_load -pin_load 0.0334 [get_ports {i2cm_rst_n}]
-set_load -pin_load 0.0334 [get_ports {rtc_clk}]
-set_load -pin_load 0.0334 [get_ports {sdram_clk}]
-set_load -pin_load 0.0334 [get_ports {sdram_rst_n}]
-set_load -pin_load 0.0334 [get_ports {spi_rst_n}]
-set_load -pin_load 0.0334 [get_ports {uart_rst_n}]
-set_load -pin_load 0.0334 [get_ports {usb_clk}]
-set_load -pin_load 0.0334 [get_ports {usb_rst_n}]
-set_load -pin_load 0.0334 [get_ports {wbd_clk_wh}]
-set_load -pin_load 0.0334 [get_ports {wbd_int_rst_n}]
-set_load -pin_load 0.0334 [get_ports {wbm_ack_o}]
-set_load -pin_load 0.0334 [get_ports {wbm_err_o}]
-set_load -pin_load 0.0334 [get_ports {wbs_clk_out}]
-set_load -pin_load 0.0334 [get_ports {wbs_cyc_o}]
-set_load -pin_load 0.0334 [get_ports {wbs_stb_o}]
-set_load -pin_load 0.0334 [get_ports {wbs_we_o}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[31]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[30]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[29]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[28]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[27]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[26]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[25]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[24]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[23]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[22]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[21]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[20]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[19]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[18]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[17]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[16]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[15]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[14]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[13]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[12]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[11]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[10]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[9]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[8]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl1[0]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[31]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[30]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[29]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[28]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[27]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[26]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[25]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[24]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[23]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[22]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[21]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[20]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[19]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[18]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[17]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[16]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[15]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[14]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[13]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[12]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[11]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[10]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[9]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[8]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[7]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[6]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[5]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[4]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[3]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[2]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[1]}]
-set_load -pin_load 0.0334 [get_ports {cfg_clk_ctrl2[0]}]
-set_load -pin_load 0.0334 [get_ports {uart_i2c_usb_sel[1]}]
-set_load -pin_load 0.0334 [get_ports {uart_i2c_usb_sel[0]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbm_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbs_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbs_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {wbs_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {wbs_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {wbs_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {wbs_sel_o[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock1}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_clock2}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_clk_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_rst_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_stb_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_clk_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_err_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wh[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_adr_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbm_sel_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbs_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 ###############################################################################
 # Design Rules
 ###############################################################################
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins u_cpu_ref_sel.u_mux/S]
+set_false_path -through [get_pins u_cpu_clk_sel.u_mux/S]
+set_false_path -through [get_pins u_wbs_clk_sel.u_mux/S]
+set_false_path -through [get_pins u_usb_clk_sel.u_mux/S]

diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 933faad..3f2aa4d 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl

@@ -31,6 +31,11 @@
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -45,6 +50,7 @@
      $script_dir/../../verilog/rtl/lib/registers.v"
 
 set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
 set ::env(SDC_FILE) "$script_dir/base.sdc"
 set ::env(BASE_SDC_FILE) "$script_dir/base.sdc"
 

diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc
index 380ebf5..ea74faa 100644
--- a/openlane/wb_interconnect/base.sdc
+++ b/openlane/wb_interconnect/base.sdc

@@ -7,224 +7,23 @@
 # Timing Constraints
 ###############################################################################
 create_clock -name clk_i -period 10.0000 [get_ports {clk_i}]
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -setup 0.2000
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -hold 0.1000
-set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}]  -setup 0.2000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -hold 0.1000
-set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}]  -setup 0.2000
 
-set_false_path -from [get_ports {cfg_cska_wi[0]}]
-set_false_path -from [get_ports {cfg_cska_wi[1]}]
-set_false_path -from [get_ports {cfg_cska_wi[2]}]
-set_false_path -from [get_ports {cfg_cska_wi[3]}]
+set_clock_transition 0.1500 [all_clocks]
+set_clock_uncertainty -setup 0.2500 [all_clocks]
+set_clock_uncertainty -hold 0.2500 [all_clocks]
 
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[10]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[11]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[12]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[13]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[14]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[15]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[16]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[17]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[18]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[19]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[20]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[21]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[22]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[23]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[24]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[25]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[26]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[27]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[28]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[29]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[30]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[31]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[3]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[4]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[5]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[6]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[7]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[8]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[9]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[0]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[1]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[2]}]
-set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[3]}]
+#Clock Skew adjustment
+set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[1]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[2]}]
+set_case_analysis 0 [get_ports {cfg_cska_wi[3]}]
+
+
+# Set max delay for clock skew
+set_max_delay 4.0 -from [get_ports {wbd_clk_int}]
+set_max_delay   2 -to   [get_ports {wbd_clk_wi}]
+set_max_delay 4.0 -from wbd_clk_int -to wbd_clk_wi
+##
 set_input_delay -max 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rst_n}]
 set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}]
 set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[0]}]
@@ -1381,697 +1180,15 @@
 ###############################################################################
 # Environment
 ###############################################################################
-set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_cyc_o}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_stb_o}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_we_o}]
-set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[31]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[30]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[29]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[28]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[27]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[26]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[25]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[24]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[23]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[22]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[21]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[20]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[19]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[18]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[17]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[16]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[15]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[14]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[13]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[12]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[11]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[10]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[9]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[8]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[31]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[30]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[29]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[28]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[27]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[26]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[25]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[24]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[23]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[22]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[21]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[20]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[19]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[18]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[17]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[16]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[15]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[14]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[13]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[12]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[11]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[10]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[9]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[8]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[31]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[30]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[29]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[28]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[27]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[26]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[25]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[24]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[23]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[22]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[21]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[20]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[19]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[18]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[17]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[16]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[15]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[14]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[13]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[12]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[11]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[10]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[9]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[8]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[7]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[6]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[5]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[4]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[0]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[3]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[2]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[1]}]
-set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_stb_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_cyc_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_stb_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_we_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_ack_i}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_sel_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_sel_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_sel_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[0]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[31]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[30]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[29]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[28]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[27]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[26]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[25]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[24]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[23]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[22]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[21]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[20]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[19]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[18]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[17]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[16]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[15]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[14]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[13]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[12]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[11]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[10]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[9]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[8]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[7]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[6]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[5]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[4]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[3]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[2]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[1]}]
-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[0]}]
+set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+set ::env(SYNTH_TIMING_DERATE) 0.05
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
 ###############################################################################
 # Design Rules
 ###############################################################################

diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 7102464..d17f0ac 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl

@@ -31,6 +31,11 @@
 
 set ::env(SYNTH_MAX_FANOUT) 4
 
+## CTS BUFFER
+set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
+set ::env(CTS_SINK_CLUSTERING_SIZE) "16"
+set ::env(CLOCK_BUFFER_FANOUT) "8"
+
 # Sources
 # -------
 
@@ -96,3 +101,14 @@
 set ::env(QUIT_ON_MAGIC_DRC) "1"
 set ::env(QUIT_ON_LVS_ERROR) "0"
 set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
+
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "1"
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1"
+set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "1000"
+set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "1.5"
+set ::env(PL_RESIZER_MAX_CAP_MARGIN) "5"
+
+## FANOUT Reduced to take care of long routes
+set ::env(SYNTH_MAX_FANOUT) "2"
+

diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg
index 5f42ec4..f450d67 100644
--- a/openlane/wb_interconnect/pin_order.cfg
+++ b/openlane/wb_interconnect/pin_order.cfg

@@ -338,55 +338,55 @@
 m2_wbd_err_o        
 m2_wbd_cyc_i        
 
-ch_data_in\[48\]    1200 0 2
-ch_data_in\[47\]
-ch_data_in\[46\]
-ch_data_in\[45\]
-ch_data_in\[44\]
-ch_data_in\[43\]
-ch_data_in\[42\]
-ch_data_in\[41\]
-ch_data_in\[40\]
-ch_data_in\[39\]
-ch_data_in\[38\]
-ch_data_in\[37\]
-ch_data_in\[36\]
-ch_data_in\[35\]
-ch_data_in\[34\]
-ch_data_in\[33\]
-ch_data_in\[32\]
-ch_data_in\[31\]
-ch_data_in\[30\]
-ch_data_in\[29\]
-ch_data_in\[28\]
-ch_data_in\[27\]
-ch_data_in\[26\]
-ch_data_in\[25\]
-ch_data_in\[24\]
-ch_data_in\[23\]
-ch_data_in\[22\]
-ch_data_in\[21\]
-ch_data_in\[20\]
-ch_data_in\[19\]
-ch_data_in\[18\]
-ch_data_in\[17\]
-ch_data_in\[16\]
-ch_data_in\[15\]
-ch_data_in\[14\]
-ch_data_in\[13\]
-ch_data_in\[12\]
-ch_data_in\[11\]
-ch_data_in\[10\]
-ch_data_in\[9\]
-ch_data_in\[8\]
-ch_data_in\[7\]
-ch_data_in\[6\]
-ch_data_in\[5\]
-ch_data_in\[4\]
-ch_data_in\[3\]
-ch_data_in\[2\]
-ch_data_in\[1\]
-ch_data_in\[0\]
+ch_data_out\[48\]    1200 0 2
+ch_data_out\[47\]
+ch_data_out\[46\]
+ch_data_out\[45\]
+ch_data_out\[44\]
+ch_data_out\[43\]
+ch_data_out\[42\]
+ch_data_out\[41\]
+ch_data_out\[40\]
+ch_data_out\[39\]
+ch_data_out\[38\]
+ch_data_out\[37\]
+ch_data_out\[36\]
+ch_data_out\[35\]
+ch_data_out\[34\]
+ch_data_out\[33\]
+ch_data_out\[32\]
+ch_data_out\[31\]
+ch_data_out\[30\]
+ch_data_out\[29\]
+ch_data_out\[28\]
+ch_data_out\[27\]
+ch_data_out\[26\]
+ch_data_out\[25\]
+ch_data_out\[24\]
+ch_data_out\[23\]
+ch_data_out\[22\]
+ch_data_out\[21\]
+ch_data_out\[20\]
+ch_data_out\[19\]
+ch_data_out\[18\]
+ch_data_out\[17\]
+ch_data_out\[16\]
+ch_data_out\[15\]
+ch_data_out\[14\]
+ch_data_out\[13\]
+ch_data_out\[12\]
+ch_data_out\[11\]
+ch_data_out\[10\]
+ch_data_out\[9\]
+ch_data_out\[8\]
+ch_data_out\[7\]
+ch_data_out\[6\]
+ch_data_out\[5\]
+ch_data_out\[4\]
+ch_data_out\[3\]
+ch_data_out\[2\]
+ch_data_out\[1\]
+ch_data_out\[0\]
 
 
 ch_data_out\[49] 1800 0 2
@@ -817,55 +817,55 @@
 s2_wbd_ack_i        
 s2_wbd_cyc_o        
 
-ch_data_out\[48\]    1600 0 2
-ch_data_out\[47\]
-ch_data_out\[46\]
-ch_data_out\[45\]
-ch_data_out\[44\]
-ch_data_out\[43\]
-ch_data_out\[42\]
-ch_data_out\[41\]
-ch_data_out\[40\]
-ch_data_out\[39\]
-ch_data_out\[38\]
-ch_data_out\[37\]
-ch_data_out\[36\]
-ch_data_out\[35\]
-ch_data_out\[34\]
-ch_data_out\[33\]
-ch_data_out\[32\]
-ch_data_out\[31\]
-ch_data_out\[30\]
-ch_data_out\[29\]
-ch_data_out\[28\]
-ch_data_out\[27\]
-ch_data_out\[26\]
-ch_data_out\[25\]
-ch_data_out\[24\]
-ch_data_out\[23\]
-ch_data_out\[22\]
-ch_data_out\[21\]
-ch_data_out\[20\]
-ch_data_out\[19\]
-ch_data_out\[18\]
-ch_data_out\[17\]
-ch_data_out\[16\]
-ch_data_out\[15\]
-ch_data_out\[14\]
-ch_data_out\[13\]
-ch_data_out\[12\]
-ch_data_out\[11\]
-ch_data_out\[10\]
-ch_data_out\[9\]
-ch_data_out\[8\]
-ch_data_out\[7\]
-ch_data_out\[6\]
-ch_data_out\[5\]
-ch_data_out\[4\]
-ch_data_out\[3\]
-ch_data_out\[2\]
-ch_data_out\[1\]
-ch_data_out\[0\]
+ch_data_in\[48\]    1600 0 2
+ch_data_in\[47\]
+ch_data_in\[46\]
+ch_data_in\[45\]
+ch_data_in\[44\]
+ch_data_in\[43\]
+ch_data_in\[42\]
+ch_data_in\[41\]
+ch_data_in\[40\]
+ch_data_in\[39\]
+ch_data_in\[38\]
+ch_data_in\[37\]
+ch_data_in\[36\]
+ch_data_in\[35\]
+ch_data_in\[34\]
+ch_data_in\[33\]
+ch_data_in\[32\]
+ch_data_in\[31\]
+ch_data_in\[30\]
+ch_data_in\[29\]
+ch_data_in\[28\]
+ch_data_in\[27\]
+ch_data_in\[26\]
+ch_data_in\[25\]
+ch_data_in\[24\]
+ch_data_in\[23\]
+ch_data_in\[22\]
+ch_data_in\[21\]
+ch_data_in\[20\]
+ch_data_in\[19\]
+ch_data_in\[18\]
+ch_data_in\[17\]
+ch_data_in\[16\]
+ch_data_in\[15\]
+ch_data_in\[14\]
+ch_data_in\[13\]
+ch_data_in\[12\]
+ch_data_in\[11\]
+ch_data_in\[10\]
+ch_data_in\[9\]
+ch_data_in\[8\]
+ch_data_in\[7\]
+ch_data_in\[6\]
+ch_data_in\[5\]
+ch_data_in\[4\]
+ch_data_in\[3\]
+ch_data_in\[2\]
+ch_data_in\[1\]
+ch_data_in\[0\]
 
 ch_clk_out\[0\]     1900 0 2
 s3_wbd_stb_o        

diff --git a/signoff/glbl_cfg/final_summary_report.csv b/signoff/glbl_cfg/final_summary_report.csv
index 6609eed..be3899e 100644
--- a/signoff/glbl_cfg/final_summary_report.csv
+++ b/signoff/glbl_cfg/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,flow_completed,0h8m10s,-1,58241.75824175825,0.091,29120.879120879126,37.05,616.96,2650,0,0,0,0,0,0,0,1,0,-1,-1,142475,25808,0.0,-0.42,-1,0.0,-1,0.0,-164.04,-1,0.0,-1,93786719.0,3.69,37.07,37.41,1.97,0.31,-1,3866,5893,2908,4935,0,0,0,1658,0,0,0,0,0,0,0,4,609,566,9,240,1159,0,1399,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/glbl_cfg,glbl_cfg,glbl_cfg,flow_completed,0h5m33s,-1,57978.02197802197,0.091,28989.010989010985,36.84,603.31,2638,0,0,0,0,0,0,0,1,0,-1,-1,146582,26144,0.0,-0.55,-1,0.0,-1,0.0,-214.84,-1,0.0,-1,97100024.0,3.32,37.6,37.97,3.48,0.84,-1,1507,3268,486,2247,0,0,0,1665,0,0,0,0,0,0,0,4,609,566,9,240,1159,0,1399,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/sdram/final_summary_report.csv b/signoff/sdram/final_summary_report.csv
index de4110e..8af4944 100644
--- a/signoff/sdram/final_summary_report.csv
+++ b/signoff/sdram/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/sdram,sdrc_top,sdram,flow_completed,0h10m51s,-1,40335.2380952381,0.2625,20167.61904761905,26.29,693.49,5294,0,0,0,0,0,0,0,1,0,-1,-1,303903,53159,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,221554291.0,3.79,35.37,19.46,2.9,0.07,-1,3629,7296,841,4469,0,0,0,4426,0,0,0,0,0,0,0,4,1522,1517,22,258,3471,0,3729,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/sdram,sdrc_top,sdram,flow_completed,0h8m45s,-1,40342.85714285714,0.2625,20171.42857142857,26.29,686.59,5295,0,0,0,0,0,0,0,1,0,-1,-1,303486,53123,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,221296251.0,5.14,35.8,19.34,2.71,0.0,-1,3629,7296,841,4469,0,0,0,4426,0,0,0,0,0,0,0,4,1522,1517,22,258,3471,0,3729,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/spi_master/final_summary_report.csv b/signoff/spi_master/final_summary_report.csv
index 41acc34..c7a2d1a 100644
--- a/signoff/spi_master/final_summary_report.csv
+++ b/signoff/spi_master/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/spi_master,spim_top,spi_master,flow_completed,0h12m41s,-1,60885.33333333334,0.234375,30442.66666666667,35.33,725.58,7135,0,0,0,0,0,0,0,1,0,-1,-1,345531,65168,0.0,-2.77,-1,-0.73,-1,0.0,-768.52,-1,-2.01,-1,230575024.0,0.0,30.77,38.35,2.29,1.52,-1,5846,8799,505,3457,0,0,0,6886,0,0,0,0,0,0,0,4,1765,2184,20,442,3122,0,3564,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/spi_master,spim_top,spi_master,flow_completed,0h11m8s,-1,60791.46666666666,0.234375,30395.73333333333,35.29,705.58,7124,0,0,0,0,0,0,0,1,0,-1,-1,340008,64604,0.0,-3.89,-1,0.0,-1,0.0,-1348.75,-1,0.0,-1,228595577.0,1.03,30.31,38.01,1.98,1.05,-1,5865,8818,529,3481,0,0,0,6881,0,0,0,0,0,0,0,4,1764,2182,20,442,3122,0,3564,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv
index d9c4b21..190958a 100644
--- a/signoff/syntacore/final_summary_report.csv
+++ b/signoff/syntacore/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h37m1s,-1,37152.0,1.125,18576.0,21.23,1246.52,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1370373,208356,-1.28,-17.61,-1,0.0,-1,-1532.9,-21285.41,-1,0.0,-1,1056577300.0,0.0,33.37,23.29,5.06,0.14,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,644,15552,0,16196,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h28m48s,-1,37152.0,1.125,18576.0,21.23,1233.9,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1367008,208261,-2.04,-18.67,-1,0.0,-1,-2459.49,-23069.28,-1,0.0,-1,1053431249.0,0.0,33.47,23.29,4.76,0.08,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,644,15552,0,16196,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/uart_i2cm_usb/final_summary_report.csv b/signoff/uart_i2cm_usb/final_summary_report.csv
index 1065f89..8c472be 100644
--- a/signoff/uart_i2cm_usb/final_summary_report.csv
+++ b/signoff/uart_i2cm_usb/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,flow_completed,0h14m5s,-1,53920.772946859914,0.388125,26960.386473429957,31.17,774.61,10464,0,-1,-1,-1,-1,0,0,1,0,-1,-1,391045,88618,-51.45,-52.01,-1,-51.96,-1,-164.77,-166.4,-1,-166.66,-1,244623737.0,0.08,26.08,23.01,0.44,0.18,-1,7699,11494,1125,4863,0,0,0,9113,0,0,0,0,0,0,0,4,2501,2501,26,480,5203,0,5683,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/uart_i2cm_usb,uart_i2c_usb_top,uart_i2cm_usb,flow_completed,0h13m41s,-1,54023.83252818035,0.388125,27011.916264090174,31.01,804.43,10484,0,0,0,0,0,0,0,1,0,-1,-1,398850,89025,-3.8,-4.11,-1,-4.04,-1,-3.8,-4.11,-1,-4.04,-1,251842588.0,0.0,26.47,23.45,0.63,0.22,-1,7738,11501,1123,4829,0,0,0,9082,0,0,0,0,0,0,0,4,2495,2500,26,480,5203,0,5683,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 7a4f02a..9882a86 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h29m37s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,526.07,8,0,0,0,0,0,0,-1,0,0,-1,-1,1294797,4656,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.73,1.29,5.74,0.29,0.3,-1,161,1941,161,1941,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h28m3s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,524.68,8,0,0,0,0,0,0,-1,0,0,-1,-1,1294816,4581,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.73,1.26,5.71,0.34,0.35,-1,161,1941,161,1941,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0

diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 0360127..142b9fc 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m56s,-1,38792.98245614035,0.1425,19396.491228070176,23.72,600.1,2764,0,-1,-1,-1,-1,0,0,-1,0,-1,-1,186843,28586,-3.95,-4.2,-1,-4.03,-1,-133.05,-139.83,-1,-134.98,-1,113493614.0,0.0,29.76,27.38,7.25,2.05,-1,1385,3193,727,2533,0,0,0,1485,0,0,0,0,0,0,0,4,792,958,13,204,1820,0,2024,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h5m9s,-1,38063.15789473685,0.1425,19031.578947368424,22.92,599.49,2712,0,-1,-1,-1,-1,0,0,-1,0,-1,-1,153525,25180,0.0,0.0,-1,-0.0,-1,0.0,0.0,-1,-0.0,-1,108621409.0,0.0,25.34,24.39,2.83,0.37,-1,1430,3048,738,2354,0,0,0,1452,0,0,0,0,0,0,0,4,790,952,13,204,1820,0,2024,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4

diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index d984e80..4af47de 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h11m5s,-1,8200.0,0.33,4100.0,3.99,653.68,1353,0,0,0,0,0,0,0,1,0,-1,-1,539137,25265,-4.17,-1.34,-1,-4.62,-1,-4.17,-1.34,-1,-4.62,-1,472264681.0,1.14,49.34,10.48,28.08,0.07,-1,840,2976,177,2313,0,0,0,1157,0,0,0,0,0,0,0,4,435,509,7,94,4140,0,4234,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h10m44s,-1,11296.969696969694,0.33,5648.484848484847,4.69,643.4,1864,0,-1,-1,-1,-1,0,0,1,0,-1,-1,599293,30333,-7.43,-7.45,-1,-7.65,-1,-64.17,-9.47,-1,-79.92,-1,521838525.0,3.52,48.76,12.62,37.86,0.12,-1,840,2976,177,2313,0,0,0,1157,0,0,0,0,0,0,0,4,435,509,10,94,4140,0,4234,90.9090909090909,11,10,AREA 0,2,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4

diff --git a/spef/glbl_cfg.spef.gz b/spef/glbl_cfg.spef.gz
new file mode 100644
index 0000000..7c975d9
--- /dev/null
+++ b/spef/glbl_cfg.spef.gz
Binary files differ

diff --git a/spef/scr1_top_wb.spef.gz b/spef/scr1_top_wb.spef.gz
new file mode 100644
index 0000000..97a7a71
--- /dev/null
+++ b/spef/scr1_top_wb.spef.gz
Binary files differ

diff --git a/spef/sdrc_top.spef.gz b/spef/sdrc_top.spef.gz
new file mode 100644
index 0000000..981c9b0
--- /dev/null
+++ b/spef/sdrc_top.spef.gz
Binary files differ

diff --git a/spef/spim_top.spef.gz b/spef/spim_top.spef.gz
new file mode 100644
index 0000000..321468a
--- /dev/null
+++ b/spef/spim_top.spef.gz
Binary files differ

diff --git a/spef/uart_i2c_usb_top.spef.gz b/spef/uart_i2c_usb_top.spef.gz
new file mode 100644
index 0000000..2177196
--- /dev/null
+++ b/spef/uart_i2c_usb_top.spef.gz
Binary files differ

diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz
new file mode 100644
index 0000000..f792034
--- /dev/null
+++ b/spef/user_project_wrapper.spef.gz
Binary files differ

diff --git a/spef/wb_host.spef.gz b/spef/wb_host.spef.gz
new file mode 100644
index 0000000..109ce2d
--- /dev/null
+++ b/spef/wb_host.spef.gz
Binary files differ

diff --git a/spef/wb_interconnect.spef.gz b/spef/wb_interconnect.spef.gz
new file mode 100644
index 0000000..ecb1f28
--- /dev/null
+++ b/spef/wb_interconnect.spef.gz
Binary files differ

diff --git a/spi/lvs/glbl_cfg.spice.gz b/spi/lvs/glbl_cfg.spice.gz
index 1b6fda2..97b68b2 100644
--- a/spi/lvs/glbl_cfg.spice.gz
+++ b/spi/lvs/glbl_cfg.spice.gz
Binary files differ

diff --git a/spi/lvs/sdram.spice.gz b/spi/lvs/sdram.spice.gz
index 5c57cd8..e0d5cb8 100644
--- a/spi/lvs/sdram.spice.gz
+++ b/spi/lvs/sdram.spice.gz
Binary files differ

diff --git a/spi/lvs/spi_master.spice.gz b/spi/lvs/spi_master.spice.gz
index 3ec00b7..8f6b0ca 100644
--- a/spi/lvs/spi_master.spice.gz
+++ b/spi/lvs/spi_master.spice.gz
Binary files differ

diff --git a/spi/lvs/syntacore.spice.gz b/spi/lvs/syntacore.spice.gz
index 7622fe4..0f4f273 100644
--- a/spi/lvs/syntacore.spice.gz
+++ b/spi/lvs/syntacore.spice.gz
Binary files differ

diff --git a/spi/lvs/uart_i2cm_usb.spice.gz b/spi/lvs/uart_i2cm_usb.spice.gz
index 25c7b39..ed18f58 100644
--- a/spi/lvs/uart_i2cm_usb.spice.gz
+++ b/spi/lvs/uart_i2cm_usb.spice.gz
Binary files differ

diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz
index 0e5274c..1964a78 100644
--- a/spi/lvs/user_project_wrapper.spice.gz
+++ b/spi/lvs/user_project_wrapper.spice.gz
Binary files differ

diff --git a/spi/lvs/wb_host.spice.gz b/spi/lvs/wb_host.spice.gz
index 5e2bd08..8349dd0 100644
--- a/spi/lvs/wb_host.spice.gz
+++ b/spi/lvs/wb_host.spice.gz
Binary files differ

diff --git a/spi/lvs/wb_interconnect.spice.gz b/spi/lvs/wb_interconnect.spice.gz
index 871de83..ea84c0d 100644
--- a/spi/lvs/wb_interconnect.spice.gz
+++ b/spi/lvs/wb_interconnect.spice.gz
Binary files differ

diff --git a/sta/Makefile b/sta/Makefile
new file mode 100644
index 0000000..535228e
--- /dev/null
+++ b/sta/Makefile

@@ -0,0 +1,51 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+BLOCKS = sar_adc wb_interconnect syntacore qspim uart_i2cm_usb_spi pinmux wb_host
+DEF = $(foreach block,$(BLOCKS), ../def/$(block).def)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+OPENLANE_TAG = mpw3
+OPENLANE_IMAGE_NAME = dineshannayya/openlane:$(OPENLANE_TAG)
+OPENLANE_NETLIST_COMMAND = "cd /project/sta && openroad -exit scripts/or_write_verilog.tcl | tee logs/$@.log"
+OPENLANE_STA_COMMAND = "cd /project/sta && sta scripts/sta.tcl | tee logs/sta.log"
+
+all: $(BLOCKS) run_sta
+
+$(DEF) :
+	@echo "Missing $@. Please create a def for that design"
+	@exit 1
+
+$(BLOCKS) : % : ../def/%.def  create 
+	docker run -it  -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_NETLIST_COMMAND)
+
+run_sta: $(BLOCKS)
+	#sta inside the docker is crashing with segmentation fault, so are running sta outside the docker
+	#docker run -it  -v $(PWD)/..:/project -e DESIGN_NAME=$@ -u $(shell id -u $(USER)):$(shell id -g $(USER)) $(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_STA_COMMAND)
+	sta scripts/sta.tcl | tee logs/sta.log
+
+create: clean
+	@echo "create temp directory :)"
+	mkdir -p netlist
+	mkdir -p logs
+	mkdir -p reports
+
+clean:
+	@echo "clean everything :)"
+	rm -rf netlist
+	rm -rf logs
+	rm -rf reports
+

diff --git a/sta/run_sta b/sta/run_sta
new file mode 100755
index 0000000..744d864
--- /dev/null
+++ b/sta/run_sta

@@ -0,0 +1,35 @@
+
+\rm -rf netlist
+\rm -rf logs
+\rm -rf reports
+mkdir  netlist
+mkdir  logs
+mkdir  reports
+
+echo "#################################################"
+echo "Genenerating Netlist winout power ports"
+echo "#################################################"
+export MERGED_LEF_UNPADDED=../lef/merged_unpadded.lef
+
+export DESIGN_NAME=sar_adc
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=wb_interconnect
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=syntacore
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=qspim
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=uart_i2cm_usb_spi
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=pinmux
+openroad -exit scripts/or_write_verilog.tcl 
+
+export DESIGN_NAME=wb_host
+openroad -exit scripts/or_write_verilog.tcl 
+
+sta scripts/sta.tcl | tee logs/sta.log

diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
new file mode 100644
index 0000000..d5346ff
--- /dev/null
+++ b/sta/scripts/caravel_timing.tcl

@@ -0,0 +1,184 @@
+
+        set ::env(USER_ROOT)    "../"
+        set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe"
+        set ::env(CARAVEL_PDK_ROOT)     "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+	read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v	
+	read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v	
+	read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/spi_master.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/syntacore.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/sdram.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/glbl_cfg.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v  
+
+
+	link_design caravel	
+
+	read_spef -path soc/DFFRAM_0                        $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef	
+	read_spef -path soc/core                            $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core.spef	
+	read_spef -path soc                                 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/mgmt_core_wrapper.spef	
+	read_spef -path padframe                            $::env(CARAVEL_ROOT)/spef/chip_io.spef	
+	read_spef -path rstb_level                          $::env(CARAVEL_ROOT)/spef/xres_buf.spef	
+	read_spef -path pll                                 $::env(CARAVEL_ROOT)/spef/digital_pll.spef	
+	read_spef -path housekeeping                        $::env(CARAVEL_ROOT)/spef/housekeeping.spef	
+	read_spef -path mgmt_buffers/powergood_check        $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef	
+	read_spef -path mgmt_buffers/mprj_logic_high_inst   $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef	
+	read_spef -path mgmt_buffers/mprj2_logic_high_inst  $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef	
+	read_spef -path clocking                            $::env(CARAVEL_ROOT)/spef/caravel_clocking.spef
+	read_spef -path mgmt_buffers                        $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef	
+	read_spef -path \gpio_control_bidir_1[0]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_1[1]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_2[1]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_2[2]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[0]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[10]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[1]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[2]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[3]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[4]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[5]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[6]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[7]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[8]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[9]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[0]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[1]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[2]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[3]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[4]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[5]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[0]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[10]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[11]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[12]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[13]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[14]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[15]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[1]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[2]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[3]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[4]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[5]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[6]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[7]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[8]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[9]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path gpio_defaults_block_0               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef	
+	read_spef -path gpio_defaults_block_1               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef	
+	read_spef -path gpio_defaults_block_2               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef	
+	read_spef -path gpio_defaults_block_3               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef	
+	read_spef -path gpio_defaults_block_4               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef	
+	read_spef -path gpio_defaults_block_5               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_6               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_7               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_8               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_9               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_10              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_11              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_12              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_13              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_14              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_15              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_16              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_17              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_18              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_19              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_20              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_21              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_22              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_23              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_24              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_25              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_26              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_27              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_28              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_29              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_30              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_31              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_32              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_33              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_34              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_35              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_36              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_37              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+
+	## User Project Spef
+        read_spef -path mprj/u_riscv_top         $::env(USER_ROOT)/spef/scr1_top_wb.spef
+        read_spef -path mprj/u_glbl_cfg          $::env(USER_ROOT)/spef/glbl_cfg.spef
+        read_spef -path mprj/u_sdram_ctrl        $::env(USER_ROOT)/spef/sdrc_top.spef
+        read_spef -path mprj/u_spi_master        $::env(USER_ROOT)/spef/spim_top.spef
+        read_spef -path mprj/u_uart_i2c_usb      $::env(USER_ROOT)/spef/uart_i2c_usb_top.spef
+        read_spef -path mprj/u_wb_host           $::env(USER_ROOT)/spef/wb_host.spef
+        read_spef -path mprj/u_intercon          $::env(USER_ROOT)/spef/wb_interconnect.spef
+        read_spef -path mprj                     $::env(USER_ROOT)/spef/user_project_wrapper.spef  
+
+
+	read_sdc -echo ./sdc/caravel.sdc	
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
+	echo "Wishbone Interface Timing.................." > wb.max.rpt
+	echo "Wishbone Interface Timing.................." > wb.min.rpt
+	set wb_port [get_pins {mprj/wbs_adr_i[*]}]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_cyc_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_i[*]}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_sel_i[*]}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_stb_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_we_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_ack_o}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_o[*]}]]
+	foreach pin $wb_port {
+	   echo "Wishbone Interface Timing for : [get_full_name $pin]"  >> wb.max.rpt
+           report_checks -path_delay max -fields {slew cap input nets fanout} -through $pin  >> wb.max.rpt 
+        }
+	foreach pin $wb_port {
+	   echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> wb.min.rpt
+        }
+        

diff --git a/sta/scripts/caravel_timing.tcl.1 b/sta/scripts/caravel_timing.tcl.1
new file mode 100644
index 0000000..5d95da6
--- /dev/null
+++ b/sta/scripts/caravel_timing.tcl.1

@@ -0,0 +1,184 @@
+
+        set ::env(USER_ROOT)    "../"
+        #set ::env(CARAVEL_PDK_ROOT)     "/opt/pdk_mpw4"
+
+        read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib	
+	read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib	
+	read_verilog $::env(CARAVEL_MGMT_ROOT)/verilog/gl/mgmt_core.v	
+	read_verilog $::env(CARAVEL_MGMT_ROOT)/verilog/gl/DFFRAM.v	
+	read_verilog $::env(CARAVEL_MGMT_ROOT)/verilog/gl/mgmt_core_wrapper.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel_clocking.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/digital_pll.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/housekeeping.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_control_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_0403.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/gpio_defaults_block_1803.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect_hv.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mprj2_logic_high.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/mgmt_protect.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/user_id_programming.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/xres_buf.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/spare_logic_block.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/chip_io.v	
+	read_verilog $::env(CARAVEL_ROOT)/verilog/gl/caravel.v	
+
+	# User project netlist
+        read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/syntacore.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v  
+        read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/mbist.v
+        read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v  
+
+
+	link_design caravel	
+
+	read_spef -path soc/DFFRAM_0                        $::env(CARAVEL_MGMT_ROOT)/spef/DFFRAM.spef	
+	read_spef -path soc/core                            $::env(CARAVEL_MGMT_ROOT)/spef/mgmt_core.spef	
+	read_spef -path soc                                 $::env(CARAVEL_MGMT_ROOT)/spef/mgmt_core_wrapper.spef	
+	read_spef -path padframe                            $::env(CARAVEL_ROOT)/spef/chip_io.spef	
+	read_spef -path rstb_level                          $::env(CARAVEL_ROOT)/spef/xres_buf.spef	
+	read_spef -path pll                                 $::env(CARAVEL_ROOT)/spef/digital_pll.spef	
+	read_spef -path housekeeping                        $::env(CARAVEL_ROOT)/spef/housekeeping.spef	
+	read_spef -path mgmt_buffers/powergood_check        $::env(CARAVEL_ROOT)/spef/mgmt_protect_hv.spef	
+	read_spef -path mgmt_buffers/mprj_logic_high_inst   $::env(CARAVEL_ROOT)/spef/mprj_logic_high.spef	
+	read_spef -path mgmt_buffers/mprj2_logic_high_inst  $::env(CARAVEL_ROOT)/spef/mprj2_logic_high.spef	
+	read_spef -path clocking                            $::env(CARAVEL_ROOT)/spef/caravel_clocking.spef
+	read_spef -path mgmt_buffers                        $::env(CARAVEL_ROOT)/spef/mgmt_protect.spef	
+	read_spef -path \gpio_control_bidir_1[0]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_1[1]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_2[1]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_bidir_2[2]            $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[0]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[10]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[1]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[2]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[3]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[4]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[5]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[6]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[7]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[8]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1[9]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[0]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[1]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[2]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[3]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[4]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_1a[5]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[0]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[10]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[11]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[12]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[13]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[14]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[15]              $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[1]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[2]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[3]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[4]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[5]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[6]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[7]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[8]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path \gpio_control_in_2[9]               $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef	
+	read_spef -path gpio_defaults_block_0               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef	
+	read_spef -path gpio_defaults_block_1               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef	
+	read_spef -path gpio_defaults_block_2               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef	
+	read_spef -path gpio_defaults_block_3               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef	
+	read_spef -path gpio_defaults_block_4               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef	
+	read_spef -path gpio_defaults_block_5               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_6               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_7               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_8               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_9               $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_10              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_11              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_12              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_13              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_14              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_15              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_16              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_17              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_18              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_19              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_20              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_21              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_22              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_23              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_24              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_25              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_26              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_27              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_28              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_29              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_30              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_31              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_32              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_33              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_34              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_35              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_36              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+	read_spef -path gpio_defaults_block_37              $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef	
+
+	## User Project Spef
+        read_spef -path mprj/u_mbist                       $::env(USER_ROOT)/spef/mbist_top.spef  
+
+        read_spef -path mprj/u_riscv_top         $::env(USER_ROOT)/spef/scr1_top_wb.spef
+        read_spef -path mprj/u_pinmux            $::env(USER_ROOT)/spef/pinmux.spef
+        read_spef -path mprj/u_qspi_master       $::env(USER_ROOT)/spef/qspim_top.spef
+        read_spef -path mprj/u_uart_i2c_usb_spi  $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef
+        read_spef -path mprj/u_wb_host           $::env(USER_ROOT)/spef/wb_host.spef
+        read_spef -path mprj/u_intercon          $::env(USER_ROOT)/spef/wb_interconnect.spef
+        read_spef -path mprj                     $::env(USER_ROOT)/spef/user_project_wrapper.spef  
+
+
+	read_sdc -echo ./sdc/caravel.sdc	
+	check_setup  -verbose >  unconstraints.rpt
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_checks -path_delay max -fields {slew cap input nets fanout} -format full_clock_expanded -group_count 50	
+	report_worst_slack -max 	
+	report_worst_slack -min 	
+	report_checks -path_delay min -fields {slew cap input nets fanout} -format full_clock_expanded -slack_max 0.18 -group_count 10	
+	report_check_types -max_slew -max_capacitance -max_fanout -violators  > slew.cap.fanout.vio.rpt
+
+	echo "Wishbone Interface Timing.................." > wb.max.rpt
+	echo "Wishbone Interface Timing.................." > wb.min.rpt
+	set wb_port [get_pins {mprj/wbs_adr_i[*]}]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_cyc_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_i[*]}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_sel_i[*]}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_stb_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_we_i}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_ack_o}]]
+	set wb_port [concat $wb_port [get_pins {mprj/wbs_dat_o[*]}]]
+	foreach pin $wb_port {
+	   echo "Wishbone Interface Timing for : [get_full_name $pin]"  >> wb.max.rpt
+           report_checks -path_delay max -fields {slew cap input nets fanout} -through $pin  >> wb.max.rpt 
+        }
+	foreach pin $wb_port {
+	   echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt
+           report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin  >> wb.min.rpt
+        }
+        

diff --git a/sta/scripts/or_write_verilog.tcl b/sta/scripts/or_write_verilog.tcl
new file mode 100644
index 0000000..e24c97e
--- /dev/null
+++ b/sta/scripts/or_write_verilog.tcl

@@ -0,0 +1,30 @@
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set ::env(MERGED_LEF_UNPADDED) "../lef/merged_unpadded.lef"
+set ::env(INPUT_DEF) "../def/$::env(DESIGN_NAME).def"
+set ::env(SAVE_NETLIST) "netlist/$::env(DESIGN_NAME).v"
+
+
+if {[catch {read_lef $::env(MERGED_LEF_UNPADDED)} errmsg]} {
+    puts stderr $errmsg
+    exit 1
+}
+
+if {[catch {read_def $::env(INPUT_DEF)} errmsg]} {
+    puts stderr $errmsg
+    exit 1
+}
+
+#write_verilog -include_pwr_gnd $::env(SAVE_POWER_NETLIST)
+write_verilog $::env(SAVE_NETLIST)
+

diff --git a/sta/scripts/sta.tcl b/sta/scripts/sta.tcl
new file mode 100644
index 0000000..acfab88
--- /dev/null
+++ b/sta/scripts/sta.tcl

@@ -0,0 +1,131 @@
+# SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+
+set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib"
+set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
+set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib"
+set ::env(DESIGN_NAME) "user_project_wrapper"
+set ::env(BASE_SDC_FILE) "base.sdc"
+set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8"
+set ::env(SYNTH_DRIVING_CELL_PIN) "Y"
+set ::env(SYNTH_CAP_LOAD) "17.65"
+set ::env(WIRE_RC_LAYER) "met1"
+
+#To disable empty filler cell black box get created
+#set link_make_black_boxes 0
+
+
+set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
+define_corners wc bc tt
+read_liberty -corner bc $::env(LIB_FASTEST)
+read_liberty -corner wc $::env(LIB_SLOWEST)
+read_liberty -corner tt $::env(LIB_TYPICAL)
+
+read_lib  -corner tt   ../lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+
+read_verilog netlist/qspim.v
+read_verilog netlist/syntacore.v  
+read_verilog netlist/uart_i2cm_usb_spi.v
+read_verilog netlist/wb_host.v  
+read_verilog netlist/wb_interconnect.v
+read_verilog netlist/pinmux.v
+read_verilog netlist/sar_adc.v
+read_verilog ../verilog/gl/user_project_wrapper.v  
+
+link_design  $::env(DESIGN_NAME)
+
+
+read_spef -path u_riscv_top         ../spef/scr1_top_wb.spef
+read_spef -path u_pinmux            ../spef/pinmux.spef
+read_spef -path u_qspi_master       ../spef/qspim_top.spef
+read_spef -path u_uart_i2c_usb_spi  ../spef/uart_i2c_usb_spi_top.spef
+read_spef -path u_wb_host           ../spef/wb_host.spef
+read_spef -path u_intercon          ../spef/wb_interconnect.spef
+read_spef                           ../spef/user_project_wrapper.spef  
+
+
+read_sdc -echo $::env(BASE_SDC_FILE)
+
+# check for missing constraints
+check_setup  -verbose > reports/unconstraints.rpt
+
+set_operating_conditions -analysis_type single
+# Propgate the clock
+set_propagated_clock [all_clocks]
+
+report_tns
+report_wns
+#report_power 
+#
+echo "################ CORNER : WC (MAX) TIMING Report ###################"                                              > reports/timing_ss_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100          -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbm_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbs_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  cpu_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  rtc_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  line_clk    -corner wc  -format full_clock_expanded >> reports/timing_ss_max.rpt
+report_checks                         -path_delay max                           -corner wc                              >> reports/timing_ss_max.rpt
+
+echo "################ CORNER : WC (MIN) TIMING Report ###################"                                              > reports/timing_ss_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100          -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbm_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbs_clk_i   -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  cpu_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  rtc_clk     -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  line_clk    -corner wc  -format full_clock_expanded >> reports/timing_ss_min.rpt
+report_checks                         -path_delay min                           -corner wc                              >> reports/timing_ss_min.rpt
+
+echo "################ CORNER : BC (MAX) TIMING Report ###################"                                              > reports/timing_ff_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100          -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbm_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbs_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  cpu_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  rtc_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  line_clk    -corner bc  -format full_clock_expanded >> reports/timing_ff_max.rpt
+report_checks                         -path_delay max                           -corner bc                              >> reports/timing_ff_max.rpt
+
+echo "################ CORNER : BC (MIN) TIMING Report ###################"                                              > reports/timing_ff_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100          -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbm_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbs_clk_i   -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  cpu_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  rtc_clk     -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  line_clk    -corner bc  -format full_clock_expanded >> reports/timing_ff_min.rpt
+report_checks                         -path_delay min                           -corner bc                              >> reports/timing_ff_min.rpt
+
+
+echo "################ CORNER : TT (MAX) TIMING Report ###################"                                              > reports/timing_tt_max.rpt
+report_checks -unique -slack_max -0.0 -path_delay max -group_count 100          -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbm_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  wbs_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  cpu_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  rtc_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks -group_count 100        -path_delay max  -path_group  line_clk    -corner tt  -format full_clock_expanded >> reports/timing_tt_max.rpt
+report_checks                         -path_delay max                           -corner tt                              >> reports/timing_tt_max.rpt
+
+echo "################ CORNER : TT (MIN) TIMING Report ###################"                                              > reports/timing_tt_min.rpt
+report_checks -unique -slack_max -0.0 -path_delay min -group_count 100          -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbm_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  wbs_clk_i   -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  cpu_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  rtc_clk     -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks -group_count 100        -path_delay min  -path_group  line_clk    -corner tt  -format full_clock_expanded >> reports/timing_tt_min.rpt
+report_checks                         -path_delay min                           -corner tt                              >> reports/timing_tt_min.rpt
+
+
+report_checks -path_delay min_max 
+
+#exit

diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
new file mode 100644
index 0000000..402f782
--- /dev/null
+++ b/sta/sdc/caravel.sdc

@@ -0,0 +1,261 @@
+set ::env(IO_PCT) "0.2"
+set ::env(SYNTH_MAX_FANOUT) "5"
+set ::env(SYNTH_CAP_LOAD) "1"
+set ::env(SYNTH_TIMING_DERATE) 0.05
+set ::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) 0.25
+set ::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) 0.25
+set ::env(SYNTH_CLOCK_TRANSITION) 0.15
+
+## MASTER CLOCKS
+create_clock [get_ports {"clock"} ] -name "clock"  -period 25
+create_clock [get_pins clocking/user_clk ] -name "user_clk2"  -period 25
+#create_clock [get_pins  housekeeping/_8847_/X ] -name "csclk"  -period 25
+#create_clock [get_pins  clocking/pll_clk ] -name "pll_clk"  -period 25
+#create_clock [get_pins  clocking/pll_clk90 ] -name "pll_clk90"  -period 25
+
+create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
+create_clock -name wbs_clk_i   -period 15.0000  [get_pins {mprj/u_wb_host/wbs_clk_out}]
+create_clock -name cpu_ref_clk -period 10.0000  [get_pins {mprj/u_wb_host/u_cpu_ref_sel.u_mux/X}]
+create_clock -name cpu_clk     -period 20.0000  [get_pins {mprj/u_wb_host/cpu_clk}]
+create_clock -name rtc_clk     -period 50.0000  [get_pins {mprj/u_wb_host/rtc_clk}]
+create_clock -name usb_clk     -period 20.0000  [get_pins {mprj/u_wb_host/usb_clk}]
+create_clock -name line_clk    -period 100.0000 [get_pins {mprj/u_uart_i2c_usb/u_uart_core.u_lineclk_buf.u_mux/X}]
+create_clock -name sdram_clk   -period 20.0000  [get_pins {mprj/u_wb_host/sdram_clk}]
+create_clock -name sdram_pad_clk -period 20.0000  [get_pins {mprj/io_in[29]}]
+
+## Case analysis
+
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}]
+set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}]
+set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_glbl_cfg/cfg_cska_glbl[0]}]
+set_case_analysis 0 [get_pins {mprj/u_glbl_cfg/cfg_cska_glbl[1]}]
+set_case_analysis 0 [get_pins {mprj/u_glbl_cfg/cfg_cska_glbl[2]}]
+set_case_analysis 1 [get_pins {mprj/u_glbl_cfg/cfg_cska_glbl[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sdram[0]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sdram[1]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sdram[2]}]
+set_case_analysis 1 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sdram[3]}]
+
+
+set_case_analysis 0 [get_pins {mprj/u_spi_master/cfg_cska_sp_co[0]}]
+set_case_analysis 0 [get_pins {mprj/u_spi_master/cfg_cska_sp_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_spi_master/cfg_cska_sp_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_spi_master/cfg_cska_sp_co[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_spi_master/cfg_cska_spi[0]}]
+set_case_analysis 0 [get_pins {mprj/u_spi_master/cfg_cska_spi[1]}]
+set_case_analysis 1 [get_pins {mprj/u_spi_master/cfg_cska_spi[2]}]
+set_case_analysis 0 [get_pins {mprj/u_spi_master/cfg_cska_spi[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}]
+set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}]
+
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
+set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}]
+set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb/cfg_cska_uart[0]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb/cfg_cska_uart[1]}]
+set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb/cfg_cska_uart[2]}]
+set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb/cfg_cska_uart[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_co[0]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_co[1]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_co[2]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_co[3]}]
+
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_ci[0]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_ci[1]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_ci[2]}]
+set_case_analysis 0 [get_pins {mprj/u_sdram_ctrl/cfg_cska_sd_ci[3]}]
+
+#disable clock gating check at static clock select pins
+set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S]
+
+set_propagated_clock [all_clocks]
+
+set_clock_groups -name async_clock -asynchronous \
+ -group [get_clocks {user_clk2}]\
+ -group [get_clocks {clock wb_clk}]\
+ -group [get_clocks {wbs_clk_i}]\
+ -group [get_clocks {cpu_clk}]\
+ -group [get_clocks {cpu_ref_clk}]\
+ -group [get_clocks {sdram_clk sdram_pad_clk}]\
+ -group [get_clocks {rtc_clk}]\
+ -group [get_clocks {usb_clk}]\
+ -group [get_clocks {line_clk}]\
+ -comment {Async Clock group}
+
+## INPUT/OUTPUT DELAYS
+set input_delay_value 1
+set output_delay_value [expr 25 * $::env(IO_PCT)]
+puts "\[INFO\]: Setting output delay to: $output_delay_value"
+puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {gpio}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[0]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[1]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[2]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[3]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[4]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[5]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[6]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[7]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[8]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[9]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[10]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[11]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[12]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[13]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[14]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[15]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[16]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[17]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[18]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[19]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[20]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[21]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[22]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[23]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[24]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[25]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[26]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[27]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[28]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[29]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[30]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[31]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[32]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[33]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[34]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[35]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[36]}]
+set_input_delay $input_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {mprj_io[37]}]
+
+set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_csb}]
+set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_clk}]
+set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}]
+set_output_delay $output_delay_value  -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}]
+
+set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled 
+set_case_analysis 0 [get_pins housekeeping/_4449_/S]
+set_case_analysis 0 [get_pins housekeeping/_4450_/S]
+
+## FALSE PATHS (ASYNCHRONOUS INPUTS)
+set_false_path -from [get_ports {resetb}]
+set_false_path -from [get_ports mprj_io[*]]
+set_false_path -from [get_ports gpio]
+
+## User Project static signals
+set_false_path -through [get_pins mprj/u_pinmux/bist_en]
+
+# TODO set this as parameter
+set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+puts "\[INFO\]: Setting load to: $cap_load"
+set_load  $cap_load [all_outputs]
+
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+
+puts "\[INFO\]: Setting clock setup uncertainity to: $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY)"
+puts "\[INFO\]: Setting clock hold uncertainity to: $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY)"
+set_clock_uncertainty -setup $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) [all_clocks]
+set_clock_uncertainty -setup $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks]
+
+
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
+#set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
+#
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_cyc_i}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_sel_i[*]}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_stb_i}]
+#set_output_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_we_i}]
+#
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
+#set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
+#
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_ack_o}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[0]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[10]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[11]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[12]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[13]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[14]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[15]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[16]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[17]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[18]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[19]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[1]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[20]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[21]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[22]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[23]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[24]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[25]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[26]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[27]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[28]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[29]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[2]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[30]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[31]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[3]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[4]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[5]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[6]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[7]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[8]}]
+#set_input_delay -min 1.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_dat_o[9]}]
+
+
+
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clock}]

diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 47539d4..d4aeea3 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v

@@ -384,148 +384,7 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VNB  = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VNB  = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VNB     =VSS;
-
-
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VNB     =VSS;
-
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VNB     =VSS;
-
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
-          
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;    end
+	end
 `endif    
 
 

diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 57964a4..32f3420 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v

@@ -311,117 +311,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
-          
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
     end
 `endif    
 

diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index e0cfb3e..cf6fe54 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v

@@ -235,6 +235,16 @@
 	  test_step = 10;
           wb_user_core_write('h3080_0000,{4'hF,4'hF,4'hF,8'hFF,3'b111,2'b00,7'h00});
 	  clock_monitor(5*CLK2_PERIOD,5*CLK2_PERIOD,257*CLK2_PERIOD,9*CLK2_PERIOD,5*CLK1_PERIOD);
+
+
+         $display("###################################################");
+         $display("Monitor: Checking the chip signature :");
+         // Remove Wb Reset
+         wb_user_core_write('h3080_0000,'h1);
+
+	 wb_user_core_read_check(32'h30000018,read_data,32'h5946_4956);
+	 wb_user_core_read_check(32'h3000001C,read_data,32'h2212_2021);
+	 wb_user_core_read_check(32'h30000020,read_data,32'h0001_8000);
       end
    
       begin
@@ -308,147 +318,8 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
 
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
-          
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
     end
 `endif    
 
@@ -566,6 +437,41 @@
 end
 endtask
 
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
 `ifdef GL
 
 wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;

diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 44b7bd8..2ec3612 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v

@@ -342,147 +342,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
-          
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
     end
 `endif    
 //------------------------------------------------------

diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index e90d033..0ac19cd 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v

@@ -255,147 +255,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
-          
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
     end
 `endif    
 

diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v
index 87ee8ff..0f53369 100644
--- a/verilog/dv/user_spi/user_spi_tb.v
+++ b/verilog/dv/user_spi/user_spi_tb.v

@@ -1117,147 +1117,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
-          
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
     end
 `endif    
 

diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 99d0149..db44d33 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v

@@ -295,147 +295,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force u_top.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio0.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio0.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio0.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio1.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio1.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio2.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio2.VNB    =VSS;
-
-	force u_top.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force u_top.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force u_top.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VPWR   =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VPB    =USER_VDD1V8;
-	force u_top.u_spi_master.u_buf_sdio3.VGND   =VSS;
-	force u_top.u_spi_master.u_buf_sdio3.VNB    =VSS;
-          
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force u_top.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force u_top.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force u_top.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force u_top.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force u_top.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
     end
 `endif    
 //------------------------------------------------------

diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 719cc9f..b9b0ef4 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v

@@ -168,148 +168,6 @@
 `ifndef GL // Drive Power for Hold Fix Buf
     // All standard cell need power hook-up for functionality work
     initial begin
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio0.VNB  = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio0.VNB  = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio0.VNB     =VSS;
-
-
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio1.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio1.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio1.VNB     =VSS;
-
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio2.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio2.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio2.VNB     =VSS;
-
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay1_sdio3.VNB = VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VPWR =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VPB  =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VGND =VSS;
-	force uut.mprj.u_spi_master.u_delay2_sdio3.VNB = VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VPWR    =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VPB     =USER_VDD1V8;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VGND    =VSS;
-	force uut.mprj.u_spi_master.u_buf_sdio3.VNB     =VSS;
-          
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPWR =USER_VDD1V8;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VPB  =USER_VDD1V8;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VGND =VSS;
-	force uut.mprj.u_uart_i2c_usb.u_uart_core.u_lineclk_buf.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_wb_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_cpu_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_spi_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_sdram_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_uart_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_i2cm_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VGND =VSS;
-	force uut.mprj.u_wb_host.u_buf_usb_rst.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_sdram.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_cpu.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_rtc.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VGND =VSS;
-	force uut.mprj.u_wb_host.u_clkbuf_usb.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_sdram_ref_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_sdram_clk_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_cpu_ref_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_cpu_clk_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_wbs_clk_sel.u_mux.VNB = VSS;
-
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPWR =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VPB  =USER_VDD1V8;
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VGND =VSS;
-	force uut.mprj.u_wb_host.u_usb_clk_sel.u_mux.VNB = VSS;
     end
 `endif    
 endmodule

diff --git a/verilog/gl/glbl_cfg.v b/verilog/gl/glbl_cfg.v
index 21e8649..92b6142 100644
--- a/verilog/gl/glbl_cfg.v
+++ b/verilog/gl/glbl_cfg.v

@@ -1968,6 +1968,26 @@
  wire _1902_;
  wire _1903_;
  wire _1904_;
+ wire _1905_;
+ wire _1906_;
+ wire _1907_;
+ wire _1908_;
+ wire _1909_;
+ wire _1910_;
+ wire _1911_;
+ wire _1912_;
+ wire _1913_;
+ wire _1914_;
+ wire _1915_;
+ wire _1916_;
+ wire _1917_;
+ wire _1918_;
+ wire _1919_;
+ wire _1920_;
+ wire _1921_;
+ wire _1922_;
+ wire _1923_;
+ wire _1924_;
  wire clknet_0_mclk;
  wire clknet_1_0_0_mclk;
  wire clknet_1_1_0_mclk;
@@ -2039,9 +2059,6 @@
  wire clknet_leaf_58_mclk;
  wire clknet_leaf_59_mclk;
  wire clknet_leaf_5_mclk;
- wire clknet_leaf_60_mclk;
- wire clknet_leaf_61_mclk;
- wire clknet_leaf_62_mclk;
  wire clknet_leaf_6_mclk;
  wire clknet_leaf_7_mclk;
  wire clknet_leaf_8_mclk;
@@ -2159,6 +2176,7 @@
  wire net199;
  wire net2;
  wire net20;
+ wire net200;
  wire net21;
  wire net22;
  wire net23;
@@ -2285,344 +2303,44 @@
  wire \sw_addr[3] ;
  wire sw_rd_en;
  wire sw_wr_en;
- wire \u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ;
- wire \u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ;
- wire \u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ;
- wire \u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ;
- wire \u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg10_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg10_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg10_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg10_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg11_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg11_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg11_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg11_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg12_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg12_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg12_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg12_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg13_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg13_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg13_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg13_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg14_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg14_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg14_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg14_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg15_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg15_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg15_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg15_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg1_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg1_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg1_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg1_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg2_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg2_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg2_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg2_be3.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ;
  wire \u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ;
  wire \u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ;
+ wire \u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ;
  wire \u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ;
  wire \u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ;
  wire \u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_out ;
  wire \u_reg4_be0.gen_bit_reg[0].u_bit_reg.data_out ;
  wire \u_reg4_be0.gen_bit_reg[1].u_bit_reg.data_out ;
@@ -2644,175 +2362,447 @@
  wire \u_reg4_be2.gen_bit_reg[1].u_bit_reg.data_out ;
  wire \u_reg4_be2.gen_bit_reg[2].u_bit_reg.data_out ;
  wire \u_reg4_be2.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ;
  wire \u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_out ;
+ wire \u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ;
  wire \u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_out ;
+ wire \u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ;
  wire \u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_out ;
+ wire \u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ;
  wire \u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg4_be3.gen_bit_reg[0].u_bit_reg.data_in ;
  wire \u_reg4_be3.gen_bit_reg[0].u_bit_reg.data_out ;
+ wire \u_reg4_be3.gen_bit_reg[1].u_bit_reg.data_in ;
  wire \u_reg4_be3.gen_bit_reg[1].u_bit_reg.data_out ;
+ wire \u_reg4_be3.gen_bit_reg[2].u_bit_reg.data_in ;
  wire \u_reg4_be3.gen_bit_reg[2].u_bit_reg.data_out ;
+ wire \u_reg4_be3.gen_bit_reg[3].u_bit_reg.data_in ;
  wire \u_reg4_be3.gen_bit_reg[3].u_bit_reg.data_out ;
+ wire \u_reg4_be3.gen_bit_reg[4].u_bit_reg.data_in ;
  wire \u_reg4_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg5_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg5_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg5_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg5_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg6_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg6_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg6_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg6_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg7_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg7_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg7_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg7_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg8_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg8_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg8_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg8_be3.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg9_be0.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg9_be1.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg9_be2.gen_bit_reg[7].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[0].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[1].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[2].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[3].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[4].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[5].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[6].u_bit_reg.data_out ;
- wire \u_reg9_be3.gen_bit_reg[7].u_bit_reg.data_out ;
+ wire \u_reg4_be3.gen_bit_reg[5].u_bit_reg.data_in ;
+ wire \u_reg_0.data_in[30] ;
+ wire \u_reg_0.data_in[31] ;
+ wire \u_reg_0.data_out[0] ;
+ wire \u_reg_0.data_out[10] ;
+ wire \u_reg_0.data_out[11] ;
+ wire \u_reg_0.data_out[12] ;
+ wire \u_reg_0.data_out[13] ;
+ wire \u_reg_0.data_out[14] ;
+ wire \u_reg_0.data_out[15] ;
+ wire \u_reg_0.data_out[16] ;
+ wire \u_reg_0.data_out[17] ;
+ wire \u_reg_0.data_out[18] ;
+ wire \u_reg_0.data_out[19] ;
+ wire \u_reg_0.data_out[1] ;
+ wire \u_reg_0.data_out[20] ;
+ wire \u_reg_0.data_out[21] ;
+ wire \u_reg_0.data_out[22] ;
+ wire \u_reg_0.data_out[23] ;
+ wire \u_reg_0.data_out[24] ;
+ wire \u_reg_0.data_out[25] ;
+ wire \u_reg_0.data_out[26] ;
+ wire \u_reg_0.data_out[27] ;
+ wire \u_reg_0.data_out[28] ;
+ wire \u_reg_0.data_out[29] ;
+ wire \u_reg_0.data_out[2] ;
+ wire \u_reg_0.data_out[30] ;
+ wire \u_reg_0.data_out[31] ;
+ wire \u_reg_0.data_out[3] ;
+ wire \u_reg_0.data_out[4] ;
+ wire \u_reg_0.data_out[5] ;
+ wire \u_reg_0.data_out[6] ;
+ wire \u_reg_0.data_out[7] ;
+ wire \u_reg_0.data_out[8] ;
+ wire \u_reg_0.data_out[9] ;
+ wire \u_reg_0.we[0] ;
+ wire \u_reg_0.we[1] ;
+ wire \u_reg_0.we[2] ;
+ wire \u_reg_0.we[3] ;
+ wire \u_reg_10.data_out[0] ;
+ wire \u_reg_10.data_out[10] ;
+ wire \u_reg_10.data_out[11] ;
+ wire \u_reg_10.data_out[12] ;
+ wire \u_reg_10.data_out[13] ;
+ wire \u_reg_10.data_out[14] ;
+ wire \u_reg_10.data_out[15] ;
+ wire \u_reg_10.data_out[16] ;
+ wire \u_reg_10.data_out[17] ;
+ wire \u_reg_10.data_out[18] ;
+ wire \u_reg_10.data_out[19] ;
+ wire \u_reg_10.data_out[1] ;
+ wire \u_reg_10.data_out[20] ;
+ wire \u_reg_10.data_out[21] ;
+ wire \u_reg_10.data_out[22] ;
+ wire \u_reg_10.data_out[23] ;
+ wire \u_reg_10.data_out[24] ;
+ wire \u_reg_10.data_out[25] ;
+ wire \u_reg_10.data_out[26] ;
+ wire \u_reg_10.data_out[27] ;
+ wire \u_reg_10.data_out[28] ;
+ wire \u_reg_10.data_out[29] ;
+ wire \u_reg_10.data_out[2] ;
+ wire \u_reg_10.data_out[30] ;
+ wire \u_reg_10.data_out[31] ;
+ wire \u_reg_10.data_out[3] ;
+ wire \u_reg_10.data_out[4] ;
+ wire \u_reg_10.data_out[5] ;
+ wire \u_reg_10.data_out[6] ;
+ wire \u_reg_10.data_out[7] ;
+ wire \u_reg_10.data_out[8] ;
+ wire \u_reg_10.data_out[9] ;
+ wire \u_reg_11.data_out[0] ;
+ wire \u_reg_11.data_out[10] ;
+ wire \u_reg_11.data_out[11] ;
+ wire \u_reg_11.data_out[12] ;
+ wire \u_reg_11.data_out[13] ;
+ wire \u_reg_11.data_out[14] ;
+ wire \u_reg_11.data_out[15] ;
+ wire \u_reg_11.data_out[16] ;
+ wire \u_reg_11.data_out[17] ;
+ wire \u_reg_11.data_out[18] ;
+ wire \u_reg_11.data_out[19] ;
+ wire \u_reg_11.data_out[1] ;
+ wire \u_reg_11.data_out[20] ;
+ wire \u_reg_11.data_out[21] ;
+ wire \u_reg_11.data_out[22] ;
+ wire \u_reg_11.data_out[23] ;
+ wire \u_reg_11.data_out[24] ;
+ wire \u_reg_11.data_out[25] ;
+ wire \u_reg_11.data_out[26] ;
+ wire \u_reg_11.data_out[27] ;
+ wire \u_reg_11.data_out[28] ;
+ wire \u_reg_11.data_out[29] ;
+ wire \u_reg_11.data_out[2] ;
+ wire \u_reg_11.data_out[30] ;
+ wire \u_reg_11.data_out[31] ;
+ wire \u_reg_11.data_out[3] ;
+ wire \u_reg_11.data_out[4] ;
+ wire \u_reg_11.data_out[5] ;
+ wire \u_reg_11.data_out[6] ;
+ wire \u_reg_11.data_out[7] ;
+ wire \u_reg_11.data_out[8] ;
+ wire \u_reg_11.data_out[9] ;
+ wire \u_reg_12.data_out[0] ;
+ wire \u_reg_12.data_out[10] ;
+ wire \u_reg_12.data_out[11] ;
+ wire \u_reg_12.data_out[12] ;
+ wire \u_reg_12.data_out[13] ;
+ wire \u_reg_12.data_out[14] ;
+ wire \u_reg_12.data_out[15] ;
+ wire \u_reg_12.data_out[16] ;
+ wire \u_reg_12.data_out[17] ;
+ wire \u_reg_12.data_out[18] ;
+ wire \u_reg_12.data_out[19] ;
+ wire \u_reg_12.data_out[1] ;
+ wire \u_reg_12.data_out[20] ;
+ wire \u_reg_12.data_out[21] ;
+ wire \u_reg_12.data_out[22] ;
+ wire \u_reg_12.data_out[23] ;
+ wire \u_reg_12.data_out[24] ;
+ wire \u_reg_12.data_out[25] ;
+ wire \u_reg_12.data_out[26] ;
+ wire \u_reg_12.data_out[27] ;
+ wire \u_reg_12.data_out[28] ;
+ wire \u_reg_12.data_out[29] ;
+ wire \u_reg_12.data_out[2] ;
+ wire \u_reg_12.data_out[30] ;
+ wire \u_reg_12.data_out[31] ;
+ wire \u_reg_12.data_out[3] ;
+ wire \u_reg_12.data_out[4] ;
+ wire \u_reg_12.data_out[5] ;
+ wire \u_reg_12.data_out[6] ;
+ wire \u_reg_12.data_out[7] ;
+ wire \u_reg_12.data_out[8] ;
+ wire \u_reg_12.data_out[9] ;
+ wire \u_reg_13.data_out[0] ;
+ wire \u_reg_13.data_out[10] ;
+ wire \u_reg_13.data_out[11] ;
+ wire \u_reg_13.data_out[12] ;
+ wire \u_reg_13.data_out[13] ;
+ wire \u_reg_13.data_out[14] ;
+ wire \u_reg_13.data_out[15] ;
+ wire \u_reg_13.data_out[16] ;
+ wire \u_reg_13.data_out[17] ;
+ wire \u_reg_13.data_out[18] ;
+ wire \u_reg_13.data_out[19] ;
+ wire \u_reg_13.data_out[1] ;
+ wire \u_reg_13.data_out[20] ;
+ wire \u_reg_13.data_out[21] ;
+ wire \u_reg_13.data_out[22] ;
+ wire \u_reg_13.data_out[23] ;
+ wire \u_reg_13.data_out[24] ;
+ wire \u_reg_13.data_out[25] ;
+ wire \u_reg_13.data_out[26] ;
+ wire \u_reg_13.data_out[27] ;
+ wire \u_reg_13.data_out[28] ;
+ wire \u_reg_13.data_out[29] ;
+ wire \u_reg_13.data_out[2] ;
+ wire \u_reg_13.data_out[30] ;
+ wire \u_reg_13.data_out[31] ;
+ wire \u_reg_13.data_out[3] ;
+ wire \u_reg_13.data_out[4] ;
+ wire \u_reg_13.data_out[5] ;
+ wire \u_reg_13.data_out[6] ;
+ wire \u_reg_13.data_out[7] ;
+ wire \u_reg_13.data_out[8] ;
+ wire \u_reg_13.data_out[9] ;
+ wire \u_reg_14.data_out[0] ;
+ wire \u_reg_14.data_out[10] ;
+ wire \u_reg_14.data_out[11] ;
+ wire \u_reg_14.data_out[12] ;
+ wire \u_reg_14.data_out[13] ;
+ wire \u_reg_14.data_out[14] ;
+ wire \u_reg_14.data_out[15] ;
+ wire \u_reg_14.data_out[16] ;
+ wire \u_reg_14.data_out[17] ;
+ wire \u_reg_14.data_out[18] ;
+ wire \u_reg_14.data_out[19] ;
+ wire \u_reg_14.data_out[1] ;
+ wire \u_reg_14.data_out[20] ;
+ wire \u_reg_14.data_out[21] ;
+ wire \u_reg_14.data_out[22] ;
+ wire \u_reg_14.data_out[23] ;
+ wire \u_reg_14.data_out[24] ;
+ wire \u_reg_14.data_out[25] ;
+ wire \u_reg_14.data_out[26] ;
+ wire \u_reg_14.data_out[27] ;
+ wire \u_reg_14.data_out[28] ;
+ wire \u_reg_14.data_out[29] ;
+ wire \u_reg_14.data_out[2] ;
+ wire \u_reg_14.data_out[30] ;
+ wire \u_reg_14.data_out[31] ;
+ wire \u_reg_14.data_out[3] ;
+ wire \u_reg_14.data_out[4] ;
+ wire \u_reg_14.data_out[5] ;
+ wire \u_reg_14.data_out[6] ;
+ wire \u_reg_14.data_out[7] ;
+ wire \u_reg_14.data_out[8] ;
+ wire \u_reg_14.data_out[9] ;
+ wire \u_reg_15.data_out[0] ;
+ wire \u_reg_15.data_out[10] ;
+ wire \u_reg_15.data_out[11] ;
+ wire \u_reg_15.data_out[12] ;
+ wire \u_reg_15.data_out[13] ;
+ wire \u_reg_15.data_out[14] ;
+ wire \u_reg_15.data_out[15] ;
+ wire \u_reg_15.data_out[16] ;
+ wire \u_reg_15.data_out[17] ;
+ wire \u_reg_15.data_out[18] ;
+ wire \u_reg_15.data_out[19] ;
+ wire \u_reg_15.data_out[1] ;
+ wire \u_reg_15.data_out[20] ;
+ wire \u_reg_15.data_out[21] ;
+ wire \u_reg_15.data_out[22] ;
+ wire \u_reg_15.data_out[23] ;
+ wire \u_reg_15.data_out[24] ;
+ wire \u_reg_15.data_out[25] ;
+ wire \u_reg_15.data_out[26] ;
+ wire \u_reg_15.data_out[27] ;
+ wire \u_reg_15.data_out[28] ;
+ wire \u_reg_15.data_out[29] ;
+ wire \u_reg_15.data_out[2] ;
+ wire \u_reg_15.data_out[30] ;
+ wire \u_reg_15.data_out[31] ;
+ wire \u_reg_15.data_out[3] ;
+ wire \u_reg_15.data_out[4] ;
+ wire \u_reg_15.data_out[5] ;
+ wire \u_reg_15.data_out[6] ;
+ wire \u_reg_15.data_out[7] ;
+ wire \u_reg_15.data_out[8] ;
+ wire \u_reg_15.data_out[9] ;
+ wire \u_reg_2.data_out[0] ;
+ wire \u_reg_2.data_out[10] ;
+ wire \u_reg_2.data_out[11] ;
+ wire \u_reg_2.data_out[12] ;
+ wire \u_reg_2.data_out[13] ;
+ wire \u_reg_2.data_out[14] ;
+ wire \u_reg_2.data_out[15] ;
+ wire \u_reg_2.data_out[16] ;
+ wire \u_reg_2.data_out[17] ;
+ wire \u_reg_2.data_out[18] ;
+ wire \u_reg_2.data_out[19] ;
+ wire \u_reg_2.data_out[1] ;
+ wire \u_reg_2.data_out[20] ;
+ wire \u_reg_2.data_out[21] ;
+ wire \u_reg_2.data_out[22] ;
+ wire \u_reg_2.data_out[23] ;
+ wire \u_reg_2.data_out[24] ;
+ wire \u_reg_2.data_out[25] ;
+ wire \u_reg_2.data_out[26] ;
+ wire \u_reg_2.data_out[27] ;
+ wire \u_reg_2.data_out[28] ;
+ wire \u_reg_2.data_out[29] ;
+ wire \u_reg_2.data_out[2] ;
+ wire \u_reg_2.data_out[30] ;
+ wire \u_reg_2.data_out[31] ;
+ wire \u_reg_2.data_out[3] ;
+ wire \u_reg_2.data_out[4] ;
+ wire \u_reg_2.data_out[5] ;
+ wire \u_reg_2.data_out[6] ;
+ wire \u_reg_2.data_out[7] ;
+ wire \u_reg_2.data_out[8] ;
+ wire \u_reg_2.data_out[9] ;
+ wire \u_reg_5.data_out[0] ;
+ wire \u_reg_5.data_out[10] ;
+ wire \u_reg_5.data_out[11] ;
+ wire \u_reg_5.data_out[12] ;
+ wire \u_reg_5.data_out[13] ;
+ wire \u_reg_5.data_out[14] ;
+ wire \u_reg_5.data_out[15] ;
+ wire \u_reg_5.data_out[16] ;
+ wire \u_reg_5.data_out[17] ;
+ wire \u_reg_5.data_out[18] ;
+ wire \u_reg_5.data_out[19] ;
+ wire \u_reg_5.data_out[1] ;
+ wire \u_reg_5.data_out[20] ;
+ wire \u_reg_5.data_out[21] ;
+ wire \u_reg_5.data_out[22] ;
+ wire \u_reg_5.data_out[23] ;
+ wire \u_reg_5.data_out[24] ;
+ wire \u_reg_5.data_out[25] ;
+ wire \u_reg_5.data_out[26] ;
+ wire \u_reg_5.data_out[27] ;
+ wire \u_reg_5.data_out[28] ;
+ wire \u_reg_5.data_out[29] ;
+ wire \u_reg_5.data_out[2] ;
+ wire \u_reg_5.data_out[30] ;
+ wire \u_reg_5.data_out[31] ;
+ wire \u_reg_5.data_out[3] ;
+ wire \u_reg_5.data_out[4] ;
+ wire \u_reg_5.data_out[5] ;
+ wire \u_reg_5.data_out[6] ;
+ wire \u_reg_5.data_out[7] ;
+ wire \u_reg_5.data_out[8] ;
+ wire \u_reg_5.data_out[9] ;
+ wire \u_reg_6.data_out[0] ;
+ wire \u_reg_6.data_out[10] ;
+ wire \u_reg_6.data_out[11] ;
+ wire \u_reg_6.data_out[12] ;
+ wire \u_reg_6.data_out[13] ;
+ wire \u_reg_6.data_out[14] ;
+ wire \u_reg_6.data_out[15] ;
+ wire \u_reg_6.data_out[16] ;
+ wire \u_reg_6.data_out[17] ;
+ wire \u_reg_6.data_out[18] ;
+ wire \u_reg_6.data_out[19] ;
+ wire \u_reg_6.data_out[1] ;
+ wire \u_reg_6.data_out[20] ;
+ wire \u_reg_6.data_out[21] ;
+ wire \u_reg_6.data_out[22] ;
+ wire \u_reg_6.data_out[23] ;
+ wire \u_reg_6.data_out[24] ;
+ wire \u_reg_6.data_out[25] ;
+ wire \u_reg_6.data_out[26] ;
+ wire \u_reg_6.data_out[27] ;
+ wire \u_reg_6.data_out[28] ;
+ wire \u_reg_6.data_out[29] ;
+ wire \u_reg_6.data_out[2] ;
+ wire \u_reg_6.data_out[30] ;
+ wire \u_reg_6.data_out[31] ;
+ wire \u_reg_6.data_out[3] ;
+ wire \u_reg_6.data_out[4] ;
+ wire \u_reg_6.data_out[5] ;
+ wire \u_reg_6.data_out[6] ;
+ wire \u_reg_6.data_out[7] ;
+ wire \u_reg_6.data_out[8] ;
+ wire \u_reg_6.data_out[9] ;
+ wire \u_reg_7.data_out[0] ;
+ wire \u_reg_7.data_out[10] ;
+ wire \u_reg_7.data_out[11] ;
+ wire \u_reg_7.data_out[12] ;
+ wire \u_reg_7.data_out[13] ;
+ wire \u_reg_7.data_out[14] ;
+ wire \u_reg_7.data_out[15] ;
+ wire \u_reg_7.data_out[16] ;
+ wire \u_reg_7.data_out[17] ;
+ wire \u_reg_7.data_out[18] ;
+ wire \u_reg_7.data_out[19] ;
+ wire \u_reg_7.data_out[1] ;
+ wire \u_reg_7.data_out[20] ;
+ wire \u_reg_7.data_out[21] ;
+ wire \u_reg_7.data_out[22] ;
+ wire \u_reg_7.data_out[23] ;
+ wire \u_reg_7.data_out[24] ;
+ wire \u_reg_7.data_out[25] ;
+ wire \u_reg_7.data_out[26] ;
+ wire \u_reg_7.data_out[27] ;
+ wire \u_reg_7.data_out[28] ;
+ wire \u_reg_7.data_out[29] ;
+ wire \u_reg_7.data_out[2] ;
+ wire \u_reg_7.data_out[30] ;
+ wire \u_reg_7.data_out[31] ;
+ wire \u_reg_7.data_out[3] ;
+ wire \u_reg_7.data_out[4] ;
+ wire \u_reg_7.data_out[5] ;
+ wire \u_reg_7.data_out[6] ;
+ wire \u_reg_7.data_out[7] ;
+ wire \u_reg_7.data_out[8] ;
+ wire \u_reg_7.data_out[9] ;
+ wire \u_reg_8.data_out[0] ;
+ wire \u_reg_8.data_out[10] ;
+ wire \u_reg_8.data_out[11] ;
+ wire \u_reg_8.data_out[12] ;
+ wire \u_reg_8.data_out[13] ;
+ wire \u_reg_8.data_out[14] ;
+ wire \u_reg_8.data_out[15] ;
+ wire \u_reg_8.data_out[16] ;
+ wire \u_reg_8.data_out[17] ;
+ wire \u_reg_8.data_out[18] ;
+ wire \u_reg_8.data_out[19] ;
+ wire \u_reg_8.data_out[1] ;
+ wire \u_reg_8.data_out[20] ;
+ wire \u_reg_8.data_out[21] ;
+ wire \u_reg_8.data_out[22] ;
+ wire \u_reg_8.data_out[23] ;
+ wire \u_reg_8.data_out[24] ;
+ wire \u_reg_8.data_out[25] ;
+ wire \u_reg_8.data_out[26] ;
+ wire \u_reg_8.data_out[27] ;
+ wire \u_reg_8.data_out[28] ;
+ wire \u_reg_8.data_out[29] ;
+ wire \u_reg_8.data_out[2] ;
+ wire \u_reg_8.data_out[30] ;
+ wire \u_reg_8.data_out[31] ;
+ wire \u_reg_8.data_out[3] ;
+ wire \u_reg_8.data_out[4] ;
+ wire \u_reg_8.data_out[5] ;
+ wire \u_reg_8.data_out[6] ;
+ wire \u_reg_8.data_out[7] ;
+ wire \u_reg_8.data_out[8] ;
+ wire \u_reg_8.data_out[9] ;
+ wire \u_reg_9.data_out[0] ;
+ wire \u_reg_9.data_out[10] ;
+ wire \u_reg_9.data_out[11] ;
+ wire \u_reg_9.data_out[12] ;
+ wire \u_reg_9.data_out[13] ;
+ wire \u_reg_9.data_out[14] ;
+ wire \u_reg_9.data_out[15] ;
+ wire \u_reg_9.data_out[16] ;
+ wire \u_reg_9.data_out[17] ;
+ wire \u_reg_9.data_out[18] ;
+ wire \u_reg_9.data_out[19] ;
+ wire \u_reg_9.data_out[1] ;
+ wire \u_reg_9.data_out[20] ;
+ wire \u_reg_9.data_out[21] ;
+ wire \u_reg_9.data_out[22] ;
+ wire \u_reg_9.data_out[23] ;
+ wire \u_reg_9.data_out[24] ;
+ wire \u_reg_9.data_out[25] ;
+ wire \u_reg_9.data_out[26] ;
+ wire \u_reg_9.data_out[27] ;
+ wire \u_reg_9.data_out[28] ;
+ wire \u_reg_9.data_out[29] ;
+ wire \u_reg_9.data_out[2] ;
+ wire \u_reg_9.data_out[30] ;
+ wire \u_reg_9.data_out[31] ;
+ wire \u_reg_9.data_out[3] ;
+ wire \u_reg_9.data_out[4] ;
+ wire \u_reg_9.data_out[5] ;
+ wire \u_reg_9.data_out[6] ;
+ wire \u_reg_9.data_out[7] ;
+ wire \u_reg_9.data_out[8] ;
+ wire \u_reg_9.data_out[9] ;
  wire \u_skew_glbl.clk_d1 ;
  wire \u_skew_glbl.clk_d10 ;
  wire \u_skew_glbl.clk_d11 ;
@@ -2842,1452 +2832,1493 @@
  wire \u_skew_glbl.d13 ;
  wire \u_skew_glbl.d20 ;
  wire \u_skew_glbl.d21 ;
- wire \wr_be[0] ;
- wire \wr_be[1] ;
- wire \wr_be[2] ;
- wire \wr_be[3] ;
 
- sky130_fd_sc_hd__diode_2 ANTENNA__1912__B1 (.DIODE(net180),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1925__A (.DIODE(sw_wr_en),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1913__B1 (.DIODE(net178),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1928__A (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1917__B1 (.DIODE(net176),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1930__A (.DIODE(\sw_addr[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1919__B1 (.DIODE(net175),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1932__A (.DIODE(\sw_addr[3] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1921__B1 (.DIODE(net173),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1934__A (.DIODE(\sw_addr[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1927__B1 (.DIODE(net169),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1935__A (.DIODE(_0575_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1929__A1 (.DIODE(\reg_out[19] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1936__A (.DIODE(\u_reg_0.we[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1931__A1 (.DIODE(\reg_out[18] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1939__A (.DIODE(_0579_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1932__A1 (.DIODE(\reg_out[17] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1940__A (.DIODE(_0579_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1933__A1 (.DIODE(\reg_out[16] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1942__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1949__A1 (.DIODE(\reg_out[7] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1943__A (.DIODE(\sw_addr[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1951__A1 (.DIODE(\reg_out[6] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1945__B (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1952__A1 (.DIODE(\reg_out[5] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1945__C (.DIODE(\sw_addr[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1953__A1 (.DIODE(\reg_out[4] ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1945__D (.DIODE(\sw_addr[3] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1961__A (.DIODE(_0590_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1946__A (.DIODE(_0585_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1968__A (.DIODE(_0597_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1947__A (.DIODE(\u_reg_0.we[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1975__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1950__A (.DIODE(_0589_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1985__A (.DIODE(_0613_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1951__A (.DIODE(_0589_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1987__A (.DIODE(_0615_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1953__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1988__A (.DIODE(_0615_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1954__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1990__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1955__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1992__A (.DIODE(_0619_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1956__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1994__A (.DIODE(_0621_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1957__A (.DIODE(_0589_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1995__A (.DIODE(_0621_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1959__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1997__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1960__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1998__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1961__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__1999__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1962__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2000__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1965__B (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2001__A (.DIODE(_0621_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1965__C (.DIODE(\sw_addr[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2003__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1968__A (.DIODE(_0599_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2004__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1969__A (.DIODE(_0599_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2005__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1971__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2007__A (.DIODE(_0627_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1972__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2009__A (.DIODE(_0629_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1973__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2010__A (.DIODE(_0629_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1974__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2012__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1975__A (.DIODE(_0599_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2013__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1977__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2014__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1978__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2015__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1979__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2016__A (.DIODE(_0615_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1980__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2018__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1981__A (.DIODE(\sw_addr[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2019__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1981__C (.DIODE(\sw_addr[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2020__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1985__A (.DIODE(_0608_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2021__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1986__A (.DIODE(_0608_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2023__A (.DIODE(_0635_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1988__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2028__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1989__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2029__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1990__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2030__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1991__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2031__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1992__A (.DIODE(_0608_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2032__A (.DIODE(_0629_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1994__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2034__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1995__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2035__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1996__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2036__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__1997__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2037__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2005__B2 (.DIODE(_0620_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2043__A (.DIODE(_0647_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2006__B1 (.DIODE(net180),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2048__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2006__B2 (.DIODE(_0620_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2049__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2007__A1 (.DIODE(\reg_out[29] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2050__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2007__B2 (.DIODE(_0620_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2051__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2010__A1 (.DIODE(\reg_out[28] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2054__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2018__B1 (.DIODE(net172),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2055__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2019__A1 (.DIODE(\reg_out[22] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2056__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2020__A1 (.DIODE(\reg_out[21] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2057__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2022__A1 (.DIODE(\reg_out[20] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2065__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2022__B1 (.DIODE(net169),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2066__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2025__A1 (.DIODE(\reg_out[18] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2067__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2046__A1 (.DIODE(\reg_out[5] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2068__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2055__A (.DIODE(_0638_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2071__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2056__A (.DIODE(_0638_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2072__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2058__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2073__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2059__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2074__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2060__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2079__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2061__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2080__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2062__A (.DIODE(_0638_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2081__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2064__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2082__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2065__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2085__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2066__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2086__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2067__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2087__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2070__D (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2088__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2072__A (.DIODE(\u_reg_0.we[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2090__A (.DIODE(_0670_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2074__B (.DIODE(_0647_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2091__A (.DIODE(_0670_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2075__A (.DIODE(_0650_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2093__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2076__A (.DIODE(_0650_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2094__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2078__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2095__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2079__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2096__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2080__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2099__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2081__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2100__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2082__A (.DIODE(_0650_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2101__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2084__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2102__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2085__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2106__A (.DIODE(_0678_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2086__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2107__A (.DIODE(_0678_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2087__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2109__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2091__A (.DIODE(_0658_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2110__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2092__A (.DIODE(_0658_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2111__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2094__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2112__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2095__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2113__A (.DIODE(_0670_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2096__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2115__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2097__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2116__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2098__A (.DIODE(_0658_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2117__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2100__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2118__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2101__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2121__A (.DIODE(_0613_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2102__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2126__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2103__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2127__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2106__B (.DIODE(\sw_addr[3] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2128__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2112__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2129__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2113__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2130__A (.DIODE(_0678_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2114__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2132__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2115__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2133__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2118__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2134__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2119__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2135__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2120__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2137__A (.DIODE(_0693_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2121__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2138__A (.DIODE(_0693_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2122__A (.DIODE(\sw_addr[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2140__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2128__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2141__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2129__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2142__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2130__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2143__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2131__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2146__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2134__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2147__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2135__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2148__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2136__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2149__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2137__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2154__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2140__B (.DIODE(_0682_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2155__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2141__A (.DIODE(_0684_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2156__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2142__A (.DIODE(_0684_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2157__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2144__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2158__A (.DIODE(_0693_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2145__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2160__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2146__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2161__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2147__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2162__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2148__A (.DIODE(_0684_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2163__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2150__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2170__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2151__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2171__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2152__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2172__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2153__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2173__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2155__A (.DIODE(\sw_addr[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2176__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2155__D (.DIODE(\sw_addr[3] ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2161__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2162__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2163__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2164__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2167__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2168__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2169__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2170__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+    .VGND(vssd1),
+    .VNB(vssd1),
+    .VPB(vccd1),
+    .VPWR(vccd1));
+ sky130_fd_sc_hd__diode_2 ANTENNA__2171__B (.DIODE(_0682_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2177__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2172__A (.DIODE(_0699_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2178__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2173__A (.DIODE(_0699_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2179__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2175__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2186__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2176__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2187__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2177__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2188__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2178__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2189__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2179__A (.DIODE(_0699_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2192__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2181__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2193__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2182__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2194__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2183__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2195__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2184__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2196__A (.DIODE(_0627_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2187__A (.DIODE(_0706_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2198__A (.DIODE(_0722_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2188__A (.DIODE(_0706_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2199__A (.DIODE(_0722_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2190__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2201__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2191__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2202__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2192__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2203__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2193__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2204__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2194__A (.DIODE(_0706_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2207__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2196__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2208__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2197__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2209__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2198__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2210__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2199__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2211__A (.DIODE(_0635_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2202__A (.DIODE(_0713_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2216__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2203__A (.DIODE(_0713_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2217__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2205__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2218__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2206__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2219__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2207__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2220__A (.DIODE(_0722_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2208__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2222__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2209__A (.DIODE(_0713_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2223__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2211__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2224__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2212__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2225__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2213__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2227__A (.DIODE(_0735_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2214__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2229__A (.DIODE(_0737_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2220__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2230__A (.DIODE(_0737_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2221__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2232__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2222__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2233__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2223__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2234__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2226__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2235__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2227__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2238__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2228__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2239__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2229__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2240__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2231__A (.DIODE(_0726_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2241__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2232__A (.DIODE(_0726_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2244__A (.DIODE(_0744_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2234__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2245__A (.DIODE(_0744_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2235__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2247__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2236__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2248__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2237__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2249__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2238__A (.DIODE(_0726_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2250__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2240__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2251__A (.DIODE(_0737_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2241__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2253__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2242__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2254__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2243__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2255__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2244__A (.DIODE(\sw_addr[2] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2256__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2244__C (.DIODE(\sw_addr[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2258__A (.DIODE(_0750_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2244__D (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2259__A (.DIODE(_0750_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2250__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2261__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2251__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2262__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2252__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2263__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2253__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2264__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2256__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2265__A (.DIODE(_0744_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2257__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2267__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2258__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2268__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2259__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2269__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2264__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2270__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2265__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2272__A (.DIODE(_0756_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2266__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2273__A (.DIODE(_0756_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2267__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2275__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2270__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2276__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2271__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2277__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2272__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2278__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2273__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2279__A (.DIODE(_0750_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2277__A (.DIODE(_0748_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2281__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2278__A (.DIODE(_0748_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2282__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2280__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2283__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2281__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2284__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2282__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2289__A (.DIODE(_0765_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2283__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2290__A (.DIODE(_0765_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2284__A (.DIODE(_0748_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2292__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2286__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2293__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2287__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2294__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2288__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2295__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2289__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2296__A (.DIODE(_0756_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2295__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2298__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2296__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2299__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2297__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2300__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2298__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2301__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2301__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2302__A (.DIODE(_0590_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2302__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2305__A (.DIODE(_0773_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2303__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2306__A (.DIODE(_0773_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2304__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2308__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2305__C (.DIODE(\sw_addr[0] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2309__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2305__D (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2310__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2307__B (.DIODE(_0762_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2311__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2308__A (.DIODE(_0763_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2312__A (.DIODE(_0765_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2309__A (.DIODE(_0763_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2314__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2311__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2315__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2312__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2316__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2313__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2317__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2314__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2322__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2315__A (.DIODE(_0763_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2323__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2317__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2324__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2318__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2325__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2319__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2326__A (.DIODE(_0773_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2320__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2328__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2321__B (.DIODE(\sw_addr[1] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2329__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2321__D (.DIODE(\sw_addr[3] ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2330__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2324__A (.DIODE(_0771_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2331__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2325__A (.DIODE(_0771_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2333__A (.DIODE(_0785_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2327__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2334__A (.DIODE(_0785_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2328__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2336__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2329__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2337__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2330__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2338__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2331__A (.DIODE(_0771_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2339__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2333__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2342__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2334__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2343__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2335__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2344__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2336__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2345__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2344__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2349__A (.DIODE(_0793_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2345__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2350__A (.DIODE(_0793_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2346__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2352__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2347__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2353__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2350__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2354__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2351__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2355__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2352__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2356__A (.DIODE(_0785_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2353__B1 (.DIODE(\u_reg3_be0.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2358__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2357__A (.DIODE(_0788_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2359__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2358__A (.DIODE(_0788_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2360__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2360__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2361__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2361__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2362__A (.DIODE(_0597_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2362__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2363__A (.DIODE(_0613_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2363__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2368__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2364__A (.DIODE(_0788_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2369__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2366__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2370__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2367__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2371__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2368__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2374__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2369__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2375__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2375__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2376__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2376__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2377__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2377__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2380__A (.DIODE(_0808_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2378__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2381__A (.DIODE(_0808_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2381__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2383__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2382__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2384__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2383__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2385__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2384__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2386__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2386__A (.DIODE(_0801_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2389__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2387__A (.DIODE(_0801_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2390__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2389__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2391__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2390__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2392__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2391__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2394__A (.DIODE(_0814_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2392__B1 (.DIODE(\u_reg4_be2.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2395__A (.DIODE(_0814_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2393__A (.DIODE(_0801_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2397__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2395__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2398__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2396__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2399__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2397__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2400__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2398__B1 (.DIODE(\u_reg3_be2.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
@@ -4297,1937 +4328,1932 @@
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2403__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2402__A (.DIODE(_0808_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2404__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2404__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2405__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2405__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2406__B1 (.DIODE(\u_reg0_be1.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2406__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2408__A (.DIODE(_0820_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2407__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2413__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2408__A (.DIODE(_0808_),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2414__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2410__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2415__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2411__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2416__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[2].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2412__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2417__A (.DIODE(_0814_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2413__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[0].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2419__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[3].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2418__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[7].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2420__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[4].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2419__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[6].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2421__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[5].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2420__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[5].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2422__B1 (.DIODE(\u_reg0_be0.gen_bit_reg[6].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2421__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[4].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2423__A (.DIODE(_0820_),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2424__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[3].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2428__B1 (.DIODE(\u_reg0_be2.gen_bit_reg[7].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2425__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[2].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2429__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[0].u_bit_reg.data_in ),
+ sky130_fd_sc_hd__diode_2 ANTENNA__2426__B1 (.DIODE(\u_reg3_be1.gen_bit_reg[1].u_bit_reg.data_in ),
     .VGND(vssd1),
     .VNB(vssd1),
     .VPB(vccd1),
     .VPWR(vccd1));
- sky130_fd_sc_hd__diode_2 ANTENNA__2430__B1 (.DIODE(\u_reg0_be3.gen_bit_reg[1].u_bit_reg.data_in ),
+ sky130_fd_s
commit	14a28a8a258a27c718e9a0091f54f7c7fc68d00b	[log] [tgz]
author	dineshannayya <dinesh.annayya@gmail.com>	Wed Dec 22 12:33:40 2021 +0530
committer	dineshannayya <dinesh.annayya@gmail.com>	Wed Dec 22 12:33:40 2021 +0530
tree	3cac7da2b15c1f8d9f688b667cc165f1096e1625
parent	ba29eaf91ba0438a4ff1b41ccddbb40328fc1874 [diff]