| /root/two_stage_cmos_opamp/Makefile |
| /root/two_stage_cmos_opamp/docs/environment.yml |
| /root/two_stage_cmos_opamp/docs/Makefile |
| /root/two_stage_cmos_opamp/docs/source/index.rst |
| /root/two_stage_cmos_opamp/docs/source/conf.py |
| /root/two_stage_cmos_opamp/verilog/dv/Makefile |
| /root/two_stage_cmos_opamp/verilog/dv/mprj_por/mprj_por_tb.v |
| /root/two_stage_cmos_opamp/verilog/dv/mprj_por/Makefile |
| /root/two_stage_cmos_opamp/verilog/dv/mprj_por/mprj_por.c |
| /root/two_stage_cmos_opamp/verilog/rtl/example_por.v |
| /root/two_stage_cmos_opamp/verilog/rtl/uprj_analog_netlists.v |
| /root/two_stage_cmos_opamp/verilog/rtl/user_analog_proj_example.v |
| /root/two_stage_cmos_opamp/verilog/rtl/user_analog_project_wrapper.v |
| /root/two_stage_cmos_opamp/mag/user_analog_project_wrapper.ext |
| /root/two_stage_cmos_opamp/mag/layout_opamp_3.ext |
| /root/two_stage_cmos_opamp/mag/layout_opamp.ext |
| /root/two_stage_cmos_opamp/mag/layout_opamp_2.ext |
| /root/two_stage_cmos_opamp/xschem/xschemrc |
| /root/two_stage_cmos_opamp/xschem/example_por.sch |
| /root/two_stage_cmos_opamp/xschem/example_por.sym |
| /root/two_stage_cmos_opamp/xschem/example_por_tb.spice.orig |
| /root/two_stage_cmos_opamp/xschem/test.data |
| /root/two_stage_cmos_opamp/xschem/user_analog_project_wrapper.sym |
| /root/two_stage_cmos_opamp/xschem/example_por_tb.sch |
| /root/two_stage_cmos_opamp/xschem/user_analog_project_wrapper.sch |
| /root/two_stage_cmos_opamp/xschem/analog_wrapper_tb.sch |
| /root/two_stage_cmos_opamp/xschem/.spiceinit |
| /root/two_stage_cmos_opamp/openlane/Makefile |
| /root/two_stage_cmos_opamp/netgen/run_lvs_wrapper_verilog.sh |
| /root/two_stage_cmos_opamp/netgen/run_lvs_por.sh |
| /root/two_stage_cmos_opamp/netgen/run_lvs_wrapper_xschem.sh |
