blob: 32188e3a13231bc442ae8602591dea812127adeb [file] [log] [blame]
module user_project_wrapper (user_clock2,
vccd1,
vccd2,
vdda1,
vdda2,
vssa1,
vssa2,
vssd1,
vssd2,
wb_clk_i,
wb_rst_i,
wbs_ack_o,
wbs_cyc_i,
wbs_stb_i,
wbs_we_i,
analog_io,
io_in,
io_oeb,
io_out,
la_data_in,
la_data_out,
la_oenb,
user_irq,
wbs_adr_i,
wbs_dat_i,
wbs_dat_o,
wbs_sel_i);
input user_clock2;
input vccd1;
input vccd2;
input vdda1;
input vdda2;
input vssa1;
input vssa2;
input vssd1;
input vssd2;
input wb_clk_i;
input wb_rst_i;
output wbs_ack_o;
input wbs_cyc_i;
input wbs_stb_i;
input wbs_we_i;
inout [28:0] analog_io;
input [37:0] io_in;
output [37:0] io_oeb;
output [37:0] io_out;
input [127:0] la_data_in;
output [127:0] la_data_out;
input [127:0] la_oenb;
output [2:0] user_irq;
input [31:0] wbs_adr_i;
input [31:0] wbs_dat_i;
output [31:0] wbs_dat_o;
input [3:0] wbs_sel_i;
multiplier MULT (.clk(user_clock2),
.vccd1(vccd1),
.vssd1(vssd1),
.input_a1({_NC1,
_NC2,
_NC3,
_NC4,
_NC5,
_NC6,
_NC7,
_NC8,
_NC9,
_NC10,
_NC11,
_NC12,
_NC13,
_NC14,
_NC15,
_NC16}),
.input_b1({_NC17,
_NC18,
_NC19,
_NC20,
_NC21,
_NC22,
_NC23,
_NC24,
_NC25,
_NC26,
_NC27,
_NC28,
_NC29,
_NC30,
_NC31,
_NC32}),
.product({la_data_in[31],
la_data_in[30],
la_data_in[29],
la_data_in[28],
la_data_in[27],
la_data_in[26],
la_data_in[25],
la_data_in[24],
la_data_in[23],
la_data_in[22],
la_data_in[21],
la_data_in[20],
la_data_in[19],
la_data_in[18],
la_data_in[17],
la_data_in[16],
la_data_in[15],
la_data_in[14],
la_data_in[13],
la_data_in[12],
la_data_in[11],
la_data_in[10],
la_data_in[9],
la_data_in[8],
la_data_in[7],
la_data_in[6],
la_data_in[5],
la_data_in[4],
la_data_in[3],
la_data_in[2],
la_data_in[1],
la_data_in[0]}));
endmodule