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/root/an_mssro-based_vcro/docs/source/conf.py
/root/an_mssro-based_vcro/verilog/dv/Makefile
/root/an_mssro-based_vcro/verilog/dv/mprj_por/mprj_por_tb.v
/root/an_mssro-based_vcro/verilog/dv/mprj_por/Makefile
/root/an_mssro-based_vcro/verilog/dv/mprj_por/mprj_por.c
/root/an_mssro-based_vcro/verilog/rtl/example_por.v
/root/an_mssro-based_vcro/verilog/rtl/uprj_analog_netlists.v
/root/an_mssro-based_vcro/verilog/rtl/user_analog_proj_example.v
/root/an_mssro-based_vcro/verilog/rtl/user_analog_project_wrapper.v
/root/an_mssro-based_vcro/spi/lvs/run_lvs.sh
/root/an_mssro-based_vcro/xschem/xschemrc
/root/an_mssro-based_vcro/xschem/user_analog_project_tb.sch
/root/an_mssro-based_vcro/xschem/Buffer_VCRO.sch
/root/an_mssro-based_vcro/xschem/user_analog_project_wrapper.sym
/root/an_mssro-based_vcro/xschem/user_analog_project_wrapper.sch
/root/an_mssro-based_vcro/xschem/Final_5_NSO.sch
/root/an_mssro-based_vcro/xschem/esd.sym
/root/an_mssro-based_vcro/xschem/Buffer_VCRO.sym
/root/an_mssro-based_vcro/xschem/esd.sch
/root/an_mssro-based_vcro/xschem/Final_5_NSO.sym
/root/an_mssro-based_vcro/openlane/Makefile
/root/an_mssro-based_vcro/mag_ext/user_analog_project_wrapper_flat.ext
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/root/an_mssro-based_vcro/mag_ext/VCO_Flat.ext
/root/an_mssro-based_vcro/netgen/run_lvs_wrapper_verilog.sh
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