diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 0000000..5bdfdae
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "caravel"]
+	path = caravel
+	url = https://github.com/efabless/caravel
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..261eeb9
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
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+      "License" shall mean the terms and conditions for use, reproduction,
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+      "You" (or "Your") shall mean an individual or Legal Entity
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+      "Work" shall mean the work of authorship, whether in Source or
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+      "Contribution" shall mean any work of authorship, including
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+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
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+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
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+
+   6. Trademarks. This License does not grant permission to use the trade
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+   7. Disclaimer of Warranty. Unless required by applicable law or
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+      Contributor provides its Contributions) on an "AS IS" BASIS,
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+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
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+      negligent acts) or agreed to in writing, shall any Contributor be
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+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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+   limitations under the License.
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..48224fd
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,172 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CARAVEL_ROOT?=$(PWD)/caravel
+PRECHECK_ROOT?=${HOME}/precheck
+SIM ?= RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+ifeq ($(CARAVEL_LITE),1) 
+	CARAVEL_NAME := caravel-lite
+	CARAVEL_REPO := https://github.com/efabless/caravel-lite 
+	CARAVEL_COMMIT := main
+else
+	CARAVEL_NAME := caravel
+	CARAVEL_REPO := https://github.com/efabless/caravel 
+	CARAVEL_COMMIT := master
+endif
+
+# Install caravel as submodule, (1): submodule, (0): clone
+SUBMODULE?=1
+
+# Include Caravel Makefile Targets
+.PHONY: %
+%: 
+	$(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+# Verify Target for running simulations
+.PHONY: verify
+verify:
+	cd ./verilog/dv/ && \
+	export SIM=${SIM} && \
+		$(MAKE) -j$(THREADS)
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+	docker pull efabless/dv_setup:latest
+
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+TARGET_PATH=$(shell pwd)
+PDK_PATH=${PDK_ROOT}/sky130A
+VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+$(DV_PATTERNS): verify-% : 
+	docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_PATH}:${PDK_PATH} \
+                -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+                -e TARGET_PATH=${TARGET_PATH} -e PDK_PATH=${PDK_PATH} \
+                -e CARAVEL_ROOT=${CARAVEL_ROOT} \
+                -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
+                sh -c $(VERIFY_COMMAND)
+				
+# Openlane Makefile Targets
+BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(BLOCKS)
+$(BLOCKS): %:
+	cd openlane && $(MAKE) $*
+
+# Install caravel
+.PHONY: install
+install:
+ifeq ($(SUBMODULE),1)
+	@echo "Installing $(CARAVEL_NAME) as a submodule.."
+# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
+	$(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
+	@if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
+	@git submodule update --init
+	@cd $(CARAVEL_ROOT); git checkout $(CARAVEL_COMMIT)
+	$(MAKE) simlink
+else
+	@echo "Installing $(CARAVEL_NAME).."
+	@git clone $(CARAVEL_REPO) $(CARAVEL_ROOT)
+	@cd $(CARAVEL_ROOT); git checkout $(CARAVEL_COMMIT)
+endif
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT 
+	$(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+	$(eval PIN_CFG_PATH  := $(shell realpath --relative-to=openlane/user_analog_project_wrapper $(CARAVEL_ROOT)/openlane/user_analog_project_wrapper_empty/pin_order.cfg))
+	mkdir -p openlane
+	mkdir -p openlane/user_project_wrapper
+	cd openlane &&\
+	ln -sf $(MAKEFILE_PATH) Makefile
+	cd openlane/user_project_wrapper &&\
+	ln -sf $(PIN_CFG_PATH) pin_order.cfg
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+ifeq ($(SUBMODULE),1)
+	@git submodule update --init --recursive
+	cd $(CARAVEL_ROOT) && \
+	git checkout $(CARAVEL_BRANCH) && \
+	git pull
+else
+	cd $(CARAVEL_ROOT)/ && \
+		git checkout $(CARAVEL_BRANCH) && \
+		git pull
+endif
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall: 
+ifeq ($(SUBMODULE),1)
+	git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)"
+	git add .gitmodules
+	git submodule deinit -f $(CARAVEL_ROOT)
+	git rm --cached $(CARAVEL_ROOT)
+	rm -rf .git/modules/$(CARAVEL_NAME)
+	rm -rf $(CARAVEL_ROOT)
+else
+	rm -rf $(CARAVEL_ROOT)
+endif
+
+# Install Openlane
+.PHONY: openlane
+openlane: 
+	cd openlane && $(MAKE) openlane
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck:
+	@git clone https://github.com/efabless/open_mpw_precheck.git --depth=1 $(PRECHECK_ROOT)
+	@docker pull efabless/open_mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-precheck check-pdk check-caravel
+	$(eval TARGET_PATH := $(shell pwd))
+	cd $(PRECHECK_ROOT) && \
+	docker run -v $(PRECHECK_ROOT):/usr/local/bin -v $(TARGET_PATH):$(TARGET_PATH) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/open_mpw_precheck:latest bash -c "python3 open_mpw_prechecker.py --pdk_root $(PDK_ROOT) --target_path $(TARGET_PATH) -c $(CARAVEL_ROOT)"
+
+# Clean 
+.PHONY: clean
+clean:
+	cd ./verilog/dv/ && \
+		$(MAKE) -j$(THREADS) clean
+
+check-caravel:
+	@if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+		echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+		exit 1; \
+	fi
+
+check-precheck:
+	@if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+		echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+		exit 1; \
+	fi
+
+check-pdk:
+	@if [ ! -d "$(PDK_ROOT)" ]; then \
+		echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+		exit 1; \
+	fi
\ No newline at end of file
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..ae8f926
--- /dev/null
+++ b/README.md
@@ -0,0 +1,12 @@
+# Caravel Analog User
+
+[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)
+
+---
+**NOTE**
+
+Fill this README with your caravel user project documentation. 
+
+---
+
+Refer to [README](docs/source/README.md) for this sample project documentation. 
diff --git a/caravel b/caravel
new file mode 160000
index 0000000..1f8e846
--- /dev/null
+++ b/caravel
@@ -0,0 +1 @@
+Subproject commit 1f8e8466fad1b08fa9a9f0bed49942d4035ebb27
diff --git a/info.yaml b/info.yaml
new file mode 100644
index 0000000..d7d414c
--- /dev/null
+++ b/info.yaml
@@ -0,0 +1,19 @@
+---
+project:
+  description: "A template analog project for Google sponsored Open MPW shuttles for SKY130."
+  foundry: "SkyWater"
+  git_url: "https://github.com/efabless/caravel_analog_user.git"
+  organization: "Efabless"
+  organization_url: "http://efabless.com"
+  owner: "Tim Edwards"
+  process: "SKY130"
+  project_name: "Caravel Analog User"
+  project_id: "00000000"
+  tags:
+    - "Open MPW"
+    - "Test Harness"
+  category: "Test Harness"
+  top_level_netlist: "caravel/verilog/gl/caravel.v"
+  user_level_netlist: "verilog/gl/user_project_wrapper.v"
+  version: "1.00"
+  cover_image: "docs/source/_static/caravel_harness.png"
diff --git a/openlane/.gitignore b/openlane/.gitignore
new file mode 100644
index 0000000..e4867d8
--- /dev/null
+++ b/openlane/.gitignore
@@ -0,0 +1,2 @@
+*/runs
+default.cvcrc
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 120000
index 0000000..48e5b4a
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1 @@
+../caravel/openlane/Makefile
\ No newline at end of file
diff --git a/openlane/user_analog_project_wrapper/config.tcl b/openlane/user_analog_project_wrapper/config.tcl
new file mode 100755
index 0000000..07f6245
--- /dev/null
+++ b/openlane/user_analog_project_wrapper/config.tcl
@@ -0,0 +1,54 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+# Base Configurations. Don't Touch
+# section begin
+set script_dir [file dirname [file normalize [info script]]]
+
+source $script_dir/../../caravel/openlane/user_analog_project_wrapper_empty/fixed_wrapper_cfgs.tcl
+
+set ::env(DESIGN_NAME) user_analog_project_wrapper
+#section end
+
+# User Configurations
+
+## Source Verilog Files
+set ::env(VERILOG_FILES) "\
+	$script_dir/../../caravel/verilog/rtl/defines.v \
+	$script_dir/../../verilog/rtl/user_analog_project_wrapper.v"
+
+## Clock configurations
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET)  "wb_clk_i"
+
+set ::env(CLOCK_PERIOD) "10"
+
+set ::env(GLB_RT_MAXLAYER) 5
+
+set ::env(FP_PDN_CHECK_NODES) 0
+
+# The following is because there are no std cells in the example wrapper project.
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
+set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
+
+set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(FILL_INSERTION) 0
+set ::env(TAP_DECAP_INSERTION) 0
+set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_analog_project_wrapper/pin_order.cfg b/openlane/user_analog_project_wrapper/pin_order.cfg
new file mode 120000
index 0000000..267d91c
--- /dev/null
+++ b/openlane/user_analog_project_wrapper/pin_order.cfg
@@ -0,0 +1 @@
+../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg
\ No newline at end of file
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
new file mode 100644
index 0000000..69ad6a8
--- /dev/null
+++ b/verilog/dv/Makefile
@@ -0,0 +1,39 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = 
+
+all:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+	done
+
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
+$(DV_PATTERNS): verify-% : 
+	cd $* && make
+
+clean:  ${PATTERNS}
+	for i in ${PATTERNS}; do \
+		( cd $$i && make clean ) ; \
+	done
+	rm -rf *.log
+	
+.PHONY: clean all
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..dbb16ab
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,129 @@
+<!---
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+-->
+
+# Simulation Environment Setup
+
+There are two options for setting up the simulation environment: 
+
+* Pulling a pre-built docker image 
+* Installing the dependecies locally
+
+## 1. Docker
+
+There is an available docker setup with the needed tools at [efabless/dockerized-verification-setup](https://github.com/efabless/dockerized-verification-setup) 
+
+Run the following to pull the image: 
+
+```
+docker pull efabless/dv_setup:latest
+```
+
+## 2. Local Installion (Linux)
+
+You will need to fullfil these dependecies: 
+
+* Icarus Verilog (10.2+)
+* RV32I Toolchain
+
+Using apt, you can install Icarus Verilog:
+
+```bash
+sudo apt-get install iverilog
+```
+
+Next, you will need to build the RV32I toolchain. Firstly, export the installation path for the RV32I toolchain, 
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+```
+
+Then, run the following: 
+
+```bash
+# packages needed:
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \
+    libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo \
+    gperf libtool patchutils bc zlib1g-dev git libexpat1-dev
+
+sudo mkdir $GCC_PATH
+sudo chown $USER $GCC_PATH
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-rv32i
+cd riscv-gnu-toolchain-rv32i
+git checkout 411d134
+git submodule update --init --recursive
+
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=$GCC_PATH
+make -j$(nproc)
+```
+
+# Running Simulation
+
+## Docker
+
+First, you will need to export a number of environment variables: 
+
+```bash
+export PDK_PATH=<pdk-location/sky130A>
+export CARAVEL_ROOT=<caravel_root>
+export UPRJ_ROOT=<user_project_root>
+```
+
+Then, run the following command to start the docker container :
+
+```
+docker run -it -v $CARAVEL_ROOT:$CARAVEL_ROOT -v $PDK_PATH:$PDK_PATH -v $UPRJ_ROOT:$UPRJ_ROOT -e CARAVEL_ROOT=$CARAVEL_ROOT -e PDK_PATH=$PDK_PATH -e UPRJ_ROOT=$UPRJ_ROOT -u $(id -u $USER):$(id -g $USER) efabless/dv_setup:latest
+```
+
+Then, navigate to the directory where the DV tests reside : 
+
+```bash
+cd $UPRJ_ROOT/verilog/dv/
+```
+
+Then, follow the instructions at [Both](#both) to run RTL/GL simulation.
+
+## Local
+
+You will need to export these environment variables: 
+
+```bash
+export GCC_PATH=<gcc-installation-path>
+export PDK_PATH=<pdk-location/sky130A>
+```
+
+Then, follow the instruction at [Both](#both) to run RTL/GL simulation.
+
+## Both
+
+To run RTL simulation for one of the DV tests, 
+
+```bash
+cd <dv-test>
+make
+```
+
+To run gate level simulation for one of the DV tests, 
+
+```bash
+cd <dv-test>
+SIM=GL make
+```
+
+# User Analog Project Example DV
\ No newline at end of file
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
new file mode 100644
index 0000000..8e592c0
--- /dev/null
+++ b/verilog/rtl/uprj_netlists.v
@@ -0,0 +1,26 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+// Include caravel global defines for the number of the user project IO pads 
+`include "defines.v"
+`define USE_POWER_PINS
+
+`ifdef GL
+    // Assume default net type to be wire because GL netlists don't have the wire definitions
+    `default_nettype wire
+    `include "gl/user_analog_project_wrapper.v"
+`else
+    `include "user_analog_project_wrapper.v"
+`endif
\ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
new file mode 100644
index 0000000..5fd2096
--- /dev/null
+++ b/verilog/rtl/user_project_wrapper.v
@@ -0,0 +1,126 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_analog_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user analog project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_analog_project_wrapper #(
+    parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    /* GPIOs.  There are 27 GPIOs, on either side of the analog.
+     * These have the following mapping to the GPIO padframe pins
+     * and memory-mapped registers, since the numbering remains the
+     * same as caravel but skips over the analog I/O:
+     *
+     * io_in/out/oeb/in_3v3 [26:14]  <--->  mprj_io[37:25]
+     * io_in/out/oeb/in_3v3 [13:0]   <--->  mprj_io[13:0]	
+     *
+     * When the GPIOs are configured by the Management SoC for
+     * user use, they have three basic bidirectional controls:
+     * in, out, and oeb (output enable, sense inverted).  For
+     * analog projects, a 3.3V copy of the signal input is
+     * available.  out and oeb must be 1.8V signals.
+     */
+
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in,
+    input  [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_in_3v3,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] io_oeb,
+
+    /* Analog (direct connection to GPIO pad---not for high voltage or
+     * high frequency use).  The management SoC must turn off both
+     * input and output buffers on these GPIOs to allow analog access.
+     * These signals may drive a voltage up to the value of VDDIO
+     * (3.3V typical, 5.5V maximum).
+     * 
+     * Note that analog I/O is not available on the 7 lowest-numbered
+     * GPIO pads, and so the analog_io indexing is offset from the
+     * GPIO indexing by 7, as follows:
+     *
+     * gpio_analog/noesd [18:7]  <--->  mprj_io[35:24]
+     * gpio_analog/noesd [6:0]   <--->  mprj_io[13:7]	
+     *
+     */
+    
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_analog,
+    inout [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] gpio_noesd,
+
+    /* Analog signals, direct through to pad.  These have no ESD at all,
+     * so ESD protection is the responsibility of the designer.
+     *
+     * user_analog[10:0]  <--->  mprj_io[24:14]
+     *
+     */
+    inout [`ANALOG_PADS-1:0] io_analog,
+
+    /* Additional power supply ESD clamps, one per analog pad.  The
+     * high side should be connected to a 3.3-5.5V power supply.
+     * The low side should be connected to ground.
+     *
+     * clamp_high[2:0]   <--->  mprj_io[20:18]
+     * clamp_low[2:0]    <--->  mprj_io[20:18]
+     *
+     */
+    inout [2:0] io_clamp_high,
+    inout [2:0] io_clamp_low,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+// Dummy assignment so that we can take it through the openlane flow
+assign io_out = io_in;
+
+endmodule	// user_analog_project_wrapper