)]}'
{
  "commit": "ac8021e143a2577ad2ba86f079c0e17bc2df9d95",
  "tree": "4c0af18515facece8e9ff577e539dd1e5f7df947",
  "parents": [
    "8a7ad6e9b3eb5bdabde994a99ecef9bd4a61eebb"
  ],
  "author": {
    "name": "adithyasunil26",
    "email": "adithyasunil26@gmail.com",
    "time": "Fri Dec 31 04:09:25 2021 +0530"
  },
  "committer": {
    "name": "adithyasunil26",
    "email": "adithyasunil26@gmail.com",
    "time": "Fri Dec 31 04:09:25 2021 +0530"
  },
  "message": "verilog\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "53a1c85f2a74a88e19715daa0e7a6f5ce4a432aa",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_analog_proj_example.v",
      "new_id": "0bfe631c389add7d5d2685a17283632c3225b5ef",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_analog_proj_example.v"
    }
  ]
}