)]}'
{
  "commit": "5a5d9ee67e8fa1bacb1703f6783ff9ec35273f2c",
  "tree": "b9c414430e45e52115541386329145fac352aa38",
  "parents": [
    "b0f0f4a50c61eb203515bedc03cc7472bce84818"
  ],
  "author": {
    "name": "adithyasunil26",
    "email": "adithyasunil26@gmail.com",
    "time": "Fri Dec 31 03:45:39 2021 +0530"
  },
  "committer": {
    "name": "adithyasunil26",
    "email": "adithyasunil26@gmail.com",
    "time": "Fri Dec 31 03:45:39 2021 +0530"
  },
  "message": "ver\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e86b40c0ff07f8570d029523a2269f78436a643a",
      "new_mode": 33188,
      "new_path": "verilog/rtl/cp.v"
    },
    {
      "type": "delete",
      "old_id": "d318fba1fdc9a49c6325e33013ee267d8be11dff",
      "old_mode": 33188,
      "old_path": "verilog/rtl/example_por.v",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "modify",
      "old_id": "94412daf1dafed3cc3d160a33fd66818b58bdfdb",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_analog_proj_example.v",
      "new_id": "53a1c85f2a74a88e19715daa0e7a6f5ce4a432aa",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_analog_proj_example.v"
    }
  ]
}