)]}'
{
  "commit": "1d231e853a5a19c2f7781378b3093a6e90e9869c",
  "tree": "686edc225872336525566264f1e19560d81e6419",
  "parents": [
    "ea5ff7d937a3422c805b506215ae5242935638b2"
  ],
  "author": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Dec 19 17:03:41 2021 -0500"
  },
  "committer": {
    "name": "Tim Edwards",
    "email": "tim@opencircuitdesign.com",
    "time": "Sun Dec 19 17:03:41 2021 -0500"
  },
  "message": "Modified the xschem schematics so that the wrapper level correctly\nrepresents the metal resistors that were added to the layout to\nmaintain all the pins on isolated nets.  The LVS with the xschem\nnetlist is now correct with the modified layout.  The verilog\nnetlist has not yet been updated.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "995533875e78646a3d729fdac4020e62ca57884d",
      "old_mode": 33188,
      "old_path": "netgen/comp.out",
      "new_id": "42163df1a65e3d5bebce47c45cd5ff06479146e8",
      "new_mode": 33188,
      "new_path": "netgen/comp.out"
    },
    {
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      "old_id": "a3f3994b2f5f934e41205610ffb7298132d66e69",
      "old_mode": 33188,
      "old_path": "netgen/user_analog_project_wrapper.spice",
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      "new_mode": 33188,
      "new_path": "netgen/user_analog_project_wrapper.spice"
    },
    {
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      "old_id": "a4a8c1a0b8b56d6de211a8b968bfe49b0400f389",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_analog_project_wrapper.v",
      "new_id": "7a73f7652e076589d7908122a3e80d2f75644fbc",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_analog_project_wrapper.v"
    },
    {
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      "old_mode": 33188,
      "old_path": "xschem/analog_wrapper_tb.sch",
      "new_id": "d9b605cbb3ac5b014832d5bb51ce92609cd4df04",
      "new_mode": 33188,
      "new_path": "xschem/analog_wrapper_tb.sch"
    },
    {
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      "old_mode": 33188,
      "old_path": "xschem/analog_wrapper_tb.spice",
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      "new_path": "xschem/analog_wrapper_tb.spice"
    },
    {
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      "old_mode": 33188,
      "old_path": "xschem/user_analog_project_wrapper.sch",
      "new_id": "e3cbcec29248b07720c9db52f8a179b50b7f5fb0",
      "new_mode": 33188,
      "new_path": "xschem/user_analog_project_wrapper.sch"
    },
    {
      "type": "modify",
      "old_id": "51374b26d6186aeeb14c3f8103f7791d422a090a",
      "old_mode": 33188,
      "old_path": "xschem/user_analog_project_wrapper.spice",
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      "new_path": "xschem/user_analog_project_wrapper.spice"
    }
  ]
}