)]}'
{
  "commit": "f83393aa1d078ac30aa18fcd0a8b2ad5143dc635",
  "tree": "6249b614a2cd6fa3ea8a59987365b2699fae94f6",
  "parents": [
    "d134e4ff196aee994d3160d8b8518a3ed8a51955"
  ],
  "author": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Mon Aug 23 13:28:08 2021 +0530"
  },
  "committer": {
    "name": "dineshannayya",
    "email": "dinesh.annayya@gmail.com",
    "time": "Mon Aug 23 13:28:08 2021 +0530"
  },
  "message": "riscv regression suite, riscv_isa and riscv_compliance test integrated\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a20fefdab060ede6a62d87e17a7eaefa292a961a",
      "old_mode": 33188,
      "old_path": ".gitmodules",
      "new_id": "8eccf3e767905c141f9a311ea3b7aec81b75d5d8",
      "new_mode": 33188,
      "new_path": ".gitmodules"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "c1bba74717c60b51fd1a44533c0e1b46130a011c",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8f12e4eba2346d71691d742b7eb89ac2b9b32398",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/riscv_runtests.sv"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e53865fd60992ff3087d069f74e271b7c1188b16",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/uprj_netlists.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "37d6fb28b77addc9103ceb0dd438aa14cb5d5298",
      "new_mode": 33188,
      "new_path": "verilog/dv/riscv_regress/user_risc_regress_tb.v"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1501a090fa54e8ed9c7a6654efaf5db7b97e7013",
      "new_mode": 33188,
      "new_path": "verilog/dv/vpi/system/system.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7f420b6bdbff436810ef75381059944e2b0d79e8",
      "new_mode": 57344,
      "new_path": "verilog/rtl/syntacore/scr1/dependencies/coremark"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9141cf9274b610d059199e8aa2e21f54a0bc6a6e",
      "new_mode": 57344,
      "new_path": "verilog/rtl/syntacore/scr1/dependencies/riscv-compliance"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e30978a71921159aec38eeefd848fca4ed39a826",
      "new_mode": 57344,
      "new_path": "verilog/rtl/syntacore/scr1/dependencies/riscv-tests"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "90ba8664db6494caaac45ab6f66c37eb43b54c7d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3c801f700c3509f5a0e1526a1932c0148b17dac4",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "857930fcf6fdfd2b21e1ababb692be2ab31201ef",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "7056489c0a7e7959b7ff9c6b7ea6c6e76a52cea3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "cba00598cdbe5443cc37e0802f0936136e3f1ba3",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d52acbb728777cd8ee017fd7aa082e0ae043aa1f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "140161f040f71d6649e847a25cfa15952fc39d86",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c"
    },
    {
      "type": "modify",
      "old_id": "b9c0e039845a9d86672c37dddd8926257a1f5d7a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/common/common.mk",
      "new_id": "8a1d0547734bf3461a274bc97d54c361eff17f5f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/common/common.mk"
    },
    {
      "type": "modify",
      "old_id": "790e8580dbff80b0094c248a6b70949f02ca4fab",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link.ld",
      "new_id": "31653f1a4f3978b053c141bb225f522af6062f1f",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link.ld"
    },
    {
      "type": "modify",
      "old_id": "1580b366073d6f940fd7c75fa2e82bd3710e98ec",
      "old_mode": 33188,
      "old_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld",
      "new_id": "d9074107d992063dd38c28e2af200dbd3cb5fade",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0f55d60f601a4d887cc5fbc1748a0ad1592d239e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/hello/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "52cf1bcff3a4b2354921044c9b62bc18b2b82c92",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/hello/hello.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "1c95e7473c43e9073f70045dd480b629e054bd2e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/isr_sample/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "68553707f9ecd65d07f8db5ad1ee6e9ac9adf003",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b81bcc8dbbdb1fcdcbd24ba58cfd5edc1ad70aba",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/isr_sample/timer.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "d2b210bd364217170e0a8e57a7fc1c23698bccbb",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3e052a17f704aa959445f9f89836d44a983bbb0b",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/aw_test_macros.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "5b7ca54960ecc30e2518f3337f65407a684019f8",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_io.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0c7e7f945f1c791829c76532e8a609dfe36a5c3d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_test.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "fdc615653bdd4549dbd7f880ac70fc595b6a0f28",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "6717bd43c821761dc3c18ad1f3c2d764da0983f7",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test_macros.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "b2c610e9635b04fae06bff4e3afaf52e2f6a9412",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/test_macros.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "945519cf509975e4d3bb71c2abb54cc76f0acc9e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "2b9ce0d1961e78302c221ecbc76644a6cb311092",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/riscv_test.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "62e5012a92e99fbb8eb7bbed83287e99424c717e",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/rv32_tests.inc"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "743918dceb8707fe527c52db4f89dbcba8cd4f17",
      "new_mode": 33188,
      "new_path": "verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/test_macros.h"
    }
  ]
}